JP2004310541A - Dc regulated power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DC regulated power supply circuit which responds quickly, consumes low power, does not use highly precise circuit element, and has a very high ripple removal rates. <P>SOLUTION: The circuit is equipped with; a means to generate a reference voltage and bias current; a voltage current output means to generate voltage output; an output detection means which detects error or fluctuation of output voltage; an error amplification means to amplify error voltage relative to the above reference voltage; and an activation control means to control output of the voltage current output means or output of the error amplification means, responding to the voltage of the voltage current output means and the reference voltage. The activation control means has; a prescribed inherent threshold which is set by the size of a component; a feature which converts the voltage in accordance with the output voltage of the voltage current output means and holds it; a terminal which drives the output of the reference voltage in a constant current manner, and a terminal which carries out drive control of the output of the error amplifier, and the drive control are carried out until the voltage output reaches the inherent threshold. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a stabilized DC power supply. In particular, the present invention relates to a method and circuit for achieving a low operating current and a high ripple noise elimination rate.
[0002]
[Prior art]
Generally, not only portable electronic devices but also other electronic devices always include a plurality of DC stabilized power supply circuits. Power supply circuits having characteristics suitable for digital circuits, high-frequency circuits, analog circuits, and the like are arranged. By the way, in the case of a mobile phone, if the ripple removal rate of the power supply of the transmitting unit is poor, the intelligibility of the call is degraded, so the highest possible ripple removal rate is required. Even in the case of digitally coded wireless communication means, power supply ripple noise has a bad influence on the error rate because transmission and reception modulate and demodulate a carrier signal in an analog manner. According to the prior art, for example, it is possible to supply a sufficient operating current of 100 μA to achieve a ripple removal rate of −80 dB. Although several inventions have been proposed, no proposal has been made yet to significantly reduce the low operating current and achieve a high ripple rejection ratio.
[0003]
The number of electronic devices operating worldwide is estimated to be in the billions. By the way, if one power supply circuit is operating at 200 μA, it means that 5 billion units are carrying 1,000,000 A, and if it is operating at 3 V, 3000 KW of power is consumed. It becomes a calculation.
[0004]
The present invention seeks to dramatically reduce the current consumption of DC voltage stabilizing circuits used in various electronic devices and improve characteristics thereof, thereby contributing to energy saving on the earth. Hereinafter, the prior art and the circuit theory under the prior art will be considered with reference to the drawings.
[0005]
[Conventional example 1]
FIG. 1 shows a configuration example of a conventional CMOS-type stabilized power supply circuit (see Patent Document 1).
[0006]
In FIG. 1, 1 and 2 indicate power supply terminals, and 3 indicates an output terminal. 50 is a reference voltage circuit that generates a reference voltage Vref, 60 is a bias current generation circuit that determines an operating current, 100 is an error amplifier circuit that amplifies an error voltage with respect to the reference voltage, 30 is a voltage output circuit that generates an output of a power supply circuit, Reference numeral 40 denotes an output voltage dividing circuit that detects a change in the output voltage and divides the voltage.
[0007]
A specific example of this conventional stabilized power supply circuit is shown in FIG. 2 (see Patent Document 2). The error amplifier 100 has a two-stage configuration. The differential amplifier circuit 10 is a first stage, and the phase inversion amplifier 20 is a second stage. Reference numeral 30 denotes an output circuit example, and reference numeral 40 denotes an output voltage dividing circuit example.
[0008]
FIG. 3 is a graph showing the DC characteristics of the conventional circuit of FIG. 1. The horizontal axis represents the power supply voltage Vdd, and the vertical axis represents the operating current 31 of the entire circuit, the gate voltage 32 of the output transistor P4, the output voltage Vout33, and the reference voltage. The characteristics are shown by taking the voltage Vref34.
[0009]
FIG. 4 is a graph showing the characteristics of the output voltage Vout and the reference voltage Vref of FIG. A curve 41 in FIG. 4A shows a characteristic curve of the output voltage Vout, and curves 42, 43, and 44 in FIGS. 4B, 4C, and 4D show characteristic curves of the reference voltage Vref, respectively.
[0010]
As can be seen from the reference voltage curve 42 of FIG. 4, the reference voltage source generally has a positive power supply voltage coefficient, and its output increases as the power supply voltage increases. This is very bad for ripple removal, and the power supply dependence coefficient of the reference voltage greatly affects the ripple removal ratio in the low frequency range. Although it is not impossible to make the power supply voltage coefficient zero, it is necessary to use trimming and a special voltage coefficient element, so that it is very expensive in a widely used semiconductor manufacturing method.
[0011]
[Patent Document 1]
JP-A-11-338559 (FIG. 6)
[Patent Document 2]
JP-A-2000-284843 (FIG. 8).
[0012]
[Theoretical consideration of conventional circuit]
Considering the output voltage theoretically, the output voltage Vout is expressed by the following equation.
[0013]
Vout = Vref * (Av / 1 + K * Av) + So (1)
Vref is a reference voltage, Av is a voltage gain of the error amplifier, K is a voltage dividing ratio of the voltage dividing circuit, and So is a system offset voltage of the error amplifier.
[0014]
Since the reference voltage Vref is affected by the fluctuation of the power supply voltage Vdd, the rate of change is represented by a power supply voltage coefficient ΔVref of Vref = (δVref / δv) / K.
[0015]
Since K is the voltage dividing ratio of the output voltage dividing resistor, K <1 and the ripple ΔVref on Vref must be removed by a filter to obtain a high PSRR (Power Supply Rejection Ratio), which indicates the rate of output change when the power supply changes by, for example, 1V. By the way, if the voltage changes by 1 mV, the PSRR becomes 1 mV / 1 V = −60 dB.) However, since the ripple of Vref is included from a very low frequency to a high frequency, a large time constant is required for the filter. However, it has not been possible to integrate filters for removing all frequency bands on the same semiconductor chip.
[0016]
In FIG. 4B, in the characteristic curve 42 of the reference voltage Vref, the power supply voltage Vdd increases by about 10 μV (−100 dB) between 4 V and 5 V (0 dB). Vout41 is increased by about 100 μV (−80 dB).
[0017]
The power supply voltage dependency (δVref / δv) of the reference voltage Vref has a large difference depending on the type of the reference voltage circuit. The reference voltage curve 42 in FIG. 4B shows the case of the circuit shown in FIG. The cases of the circuits of FIGS. 7B and 7C are shown in reference voltage curves 43 and 44 of FIGS. 4C and 4D, respectively. Incidentally, in the reference voltage curve 43, δVref / δv is about (−80 dB), and in the case of 44, δVref / δv is about (−64 dB).
[0018]
An important element of the reference voltage source is a transient response characteristic at power-on. In FIG. 7, since the circuits (b) and (c) have two operation stable points, no voltage may be generated depending on the rise time of the power supply voltage and the load capacity.
[0019]
K is a voltage dividing ratio of the output voltage dividing circuit and is represented by the following equation.
[0020]
K = R1 / R1 + R2
R1 and R2 are resistors of the output voltage dividing circuit, and if they are made of polysilicon, the influence of the power supply voltage Vdd can be neglected, so that the rate of change of Vdd is not considered. The value of K is a divided voltage value that determines the output voltage, and the reference voltage Vref is generally 0.2 V to 0.8 V and cannot be set to an extremely small or large value. No contribution. In the example of the reference voltage curve 43 in FIG. 4C, when K = 0.2, δVref / δv is about 100 μV.
ΔVref = 100 μV / 0.2 = 500 μV. As a solution to this, there is a configuration according to the present invention. If a stabilized output is input as the power supply for the reference voltage source, it can be expected that ΔVref will be greatly improved.
[0021]
So represents a system offset voltage, which is inevitably generated in the circuit configuration, and was introduced by assuming its existence from an experimental value by a concept not conventionally adopted. Equation (1) shows that it is known empirically that it is affected by the power supply voltage Vdd, and usually has a positive coefficient.
[0022]
Power supply voltage coefficient of So ΔSo = δSo / δv
Since Av is an amplification factor of the entire circuit and has an open-loop gain, and naturally has a dependency on the power supply voltage Vdd, the rate of change is expressed by the following differential equation.
[0023]
ΔAv = (δAv / δv) / (1 + KAv)²
By the way, Av = 10000 times (80 dB), K = 0.5, and when the power supply voltage rises by 1V, it changes from 10,000 times to 12000 times, so that δAv = 2000 times, δV = 1v
ΔAv = 80 × 10^{− 6}
It can be seen that when Vref = 1.2 V, the ripple component is not negligible, corresponding to 96 μV (−80.5 dB).
[0024]
From the above theoretical considerations, the ripple component of the total output voltage Vout is expressed by the following equation.
[0025]
ΔVout = ΔVref + Vref * ΔAv + ΔSo (2).
[0026]
[Consideration of operation stability]
Next, regarding the stability, the frequency theoretical formula of the gain of each amplification stage and the pole and zero points will be examined.
[0027]
Here we refer to the following text:
ANALOG INTEGRATED CIRCUIT DESIGN, BY JOHNS and MARTIN, JOHN WILEY & SONS, INC. 223-224.
[0028]
In FIG. 2, the operational amplifier circuit 10 in the first stage of the error amplifier 100, the phase inverting circuit 20 in the second stage, and the output transistor also have an amplifying function. Therefore, when the voltage gains are Av1, Av2, and Av3 as the third stage, respectively.
Av = Av1 * Av2 * Av3,
Avi represents the gain of the i-th amplification stage by the following equation.
[0029]
Avi = Gmi * Zoi (3)
Here, Gmi and Zoi are the conductance and output impedance of the i-th stage amplifier.
[0030]
Zoi = Rpi // Rni // Coi
Here, Rpi // Rni // Coi represents the parallel impedance of the output resistance Rpi of the i-th output P-type transistor, the output resistance Rni of the N-type transistor, and the capacitance Coi of the i-th output. For example, assuming that the drain gate voltage is Vdgi and the threshold value is Vtpi, the output resistance of the i-th P-FET is represented by the following equation.
[0031]
Rpi = α (Li / Idi) √ (Vdgi + Vtpi) (4)
Here, α, Li, and Idi are correction coefficients, each of which is approximately 5 × 10⁶√V / m, the channel length and drain current of the i-th transistor.
[0032]
The conductance of the i-th amplifier is expressed by the following equation.
[0033]
Gmi = {2 μp Cox (Wi / Li) Idi} (5)
Here, μp, Cox, and Wi are the carrier mobility of the P-type FET, the unit capacity of the gate oxide film, and the channel width of the i-th transistor i, respectively.
[0034]
Next, the frequency characteristics will be considered.
[0035]
The first-stage, second-stage, and third-stage amplifier circuits each have a pole at the frequency of Fpi.
[0036]
Fpi = 1 / 2π * Zoi (6)
The output of each stage begins to attenuate at -6 dB / octave at frequency Fpi.
[0037]
With respect to the ripple noise elimination rate, from the above equation (2), it can be seen that the smaller the ripple component of the output voltage Vout, the better the gain Av is. As can be seen from equation (5), it can be estimated that increasing the drain current Idi to some extent is effective in increasing the circuit gain. On the other hand, equation (4) indicates that when the drain current Idi is reduced, the output impedance increases and the gain increases. Equations (4) and (6) show that when the drain current Idi is reduced, the pole frequency decreases and the gain does not increase to higher frequencies.
[0038]
At this stage, it is still insufficient to consider the stability and the ripple elimination rate, and the frequency characteristic further depends on the existence of a zero point. At the pole frequency, the gain attenuates at -6 dB / octave and at the zero point frequency rises at +6 dB / octave, but normally the gain shows a flat characteristic because the pole frequency is low.
[0039]
In the conventional circuit shown in FIG. 2, there are two zero points in the phase and gain frequency characteristics which are the largest. The first zero point frequency Fz1 is determined by the output smoothing capacitor C3 and the load resistance R3 as shown by the following equation.
[0040]
Fz1 = 1 / 2π * R3 * C3 (7)
The second zero frequency is very important. The output circuit of the output transistor P4 is connected by a gold wire having a thickness of 25 μm to 30 μm in the integrated power supply circuit, and has a resistance of several tens of milliohms to one hundred and several tens of milliohms when the length is 1 mm to 3 mm. . Both ends of the gold wire are in contact with the aluminum pad and the lead wire and have contact resistance and parasitic resistance of several tens of milliohms. It has a total resistance Rog = 100 mΩ to 200 mΩ. Further, the equivalent series resistance ESR of the smoothing output capacitor C3 is also significantly related. The second zero point frequency Fz2 is determined by the following equation.
[0041]
Fz2 = 1 / 2π * (Rog + ESR) * C3 (8)
Here, ESR is an equivalent resistance of the output smoothing capacitor C3.
[0042]
[Zero frequency considerations]
C3 is generally widely used from 1000 pF to 10 μF. R3 greatly varies depending on the load current. For example, assuming that the resistance is about 10Ω to 100KΩ, Rog is 200mΩ, and ESR = 20mΩ,
Fz1 = 0.15 Hz. . . 1.5MHz
Fz2 = 72 KHz. . . . 7.2MHz
Fz1 moves greatly depending on the output current during operation. When the load current is large, the frequency shifts to a very high frequency, and when no load is applied, the frequency shifts to a low frequency.
[0043]
Fz2 does not depend on the load current once the value of each part is set, but the equivalent resistance ESR of the output smoothing capacitor greatly changes depending on the type of the capacitor. It is said that a chemical capacitor or an electrolytic capacitor has a resistance of several ohms to several tens of ohms, a tantalum capacitor has a resistance of 1 to several ohms, and a ceramic capacitor has a resistance of several milliohms to several hundred ohms. Therefore, the operation may be unstable depending on the type of the capacitor used. As will be described in detail later, Fz2 is an important factor for stability because the phase delay affects the phase characteristics around 180 degrees.
[0044]
[Consideration of specific examples of stability and pole frequency]
It is considered that the stability of the stabilized power supply circuit is stable if the pole frequencies are separated from each other. For example, it is said that no problem occurs if the distance is about 10 times. Let us consider a specific example of the extreme pole frequency.
[0045]
The pole frequency Fp1 of the first stage is Ro1 = 300 KΩ. . . 150 KΩ, Co1 = 0.1-0.2 pF, Fp1 = from several hundred kilohertz to several megahertz. Since the frequency is high, the stability is relatively unlikely to be a problem, and since Co1 is small, the amount of additional capacity for performing phase compensation can be reduced, which is the best place to apply phase compensation. A stable error amplifier can be configured by adding a series circuit of a capacitor and a resistor between the gate and the drain of P3 in FIG. However, it is generally known that in a conventional circuit, when this phase compensation is large, the PSRR characteristic is greatly sacrificed in a high frequency range.
[0046]
The pole frequency Fp2 of the second stage is Ro2 = 50 KΩ. . . 100KΩ, Co2 = 150pF. . . . 250 pF, Fp2 = several kilohertz to several tens of kilohertz. Co2 is the sum of the gate capacitance of the output transistor and the additional capacitance C2. The output current varies depending on the output current standard, that is, the output transistor size. However, in a circuit with a large output transistor, a large capacitance enters Co2 from the beginning. During operation, it is almost fixed, but there is a problem in the positional relationship with Fp3 described below.
[0047]
The pole Fp3 of the third stage is the pole frequency of the final stage, and Ro3 greatly varies depending on the load current. When no load is applied, Ro3 becomes equal to the output voltage dividing resistor, and when the output voltage dividing resistance is large, the voltage drops to several hundred hertz, and the phase rotates from a low frequency. Come out. For this purpose, the output voltage dividing resistance is lowered to allow idling current to flow, thereby avoiding this. However, this is one of the reasons why the circuit current cannot be extremely reduced.
[0048]
The pole frequency Fp3 rises to about 150 KHz when a large load current flows. At this time, if the gain is close to the pole frequency FP2 of the second stage and the gain is large, the operation becomes unstable, so that it is necessary to shift Fp2. Since it is impossible to increase Fp2 with the circuit configuration as it is, conventionally, measures to decrease Fp2 by increasing C2 are generally used. However, in this method, since a capacitor of several picofarads to several hundred picofarads is added to the gate of the output FET P4, the power supply ripple noise is released from the PD node to the output voltage terminal Vout, and the ripple noise removal is sacrificed. Is inevitable. Further, in response to a pulse-like change, in order to quickly charge and discharge the added capacitor, it is necessary to supply a sufficient operating current to the transistor P3 for driving the output transistor P4.
[0049]
As described above, in the conventional circuit configuration, it is necessary to supply a sufficient operating current and an idling current in order to obtain a good ripple noise elimination rate, for example, a characteristic of -80 dB or more at 10 KHz and a good stability. Inferred from theoretical considerations.
[0050]
[Simulation characteristics of conventional circuit]
FIGS. 5 and 6 are graphs showing gain-frequency characteristics, phase-frequency, and PSRR characteristics obtained by simulation in the conventional circuit when the operating current is increased and when the operating current is reduced. Characteristic curves 51, 52 and 53 show gain-frequency characteristics of output voltage Vout, curves 54, 55 and 56 show phase-frequency characteristics, and characteristic curves 61, 62 and 63 show PSRR characteristics. The characteristic curves 51, 54 and 61 show the case where the operating current is 100 μA or more, and the characteristic curves 52, 55 and 62 show the case where the operating current is 2 μA or less. The phase margin is an index for measuring the stability of the circuit, and is defined as a phase difference from 180 degrees when the gain is 1 or 0 dB. It is considered that if the phase is separated from the lag phase of 180 degrees by 40 degrees or more at the frequency of the gain 1, the oscillation is stable and no oscillation occurs. The gain margin is also an index for measuring the stability of the circuit, and is defined by the gain attenuation ratio when the phase of the output signal is delayed by 180 degrees. It is said that if the gain is attenuated by 12 dB or more at the frequency when the phase is delayed by 180 degrees, it is stable and does not oscillate. Hereinafter, the phase margin will be studied.
[0051]
In FIG. 5, the characteristic curve 54 has a sufficient margin with a phase margin of about 60 degrees near a frequency of 15 kHz crossing 0 dB. A characteristic curve 51 indicates that a good PSRR-90 dB is obtained in the PSRR characteristic when the operating current is sufficiently large.
[0052]
However, when the characteristic curve 52 is 0 dB, the characteristic curve 55 has already passed 200 degrees, and at a frequency around 20 KHz where the characteristic curve 55 crosses 180 degrees, the characteristic curve 52 still has a sufficient gain of 40 dB. This indicates that the oscillation occurs at a frequency in the vicinity. That is, in the conventional circuit, when the operating current is reduced, the phase rotation starts from a low frequency, the gain does not decrease, and stable operation cannot be performed.
[0053]
The characteristic curves 53, 56, and 62 are characteristics of a circuit in which when the operating current is reduced to 2 μA or less, C3 is increased to 100 μF to improve the phase characteristics and increase the stability. Since C3 is increased, the third pole frequency Fp3 is significantly reduced, and the gain is reduced by about 40 dB. The second zero point frequency Fz2 is set between 1 KHz and 10 KHz for a large C3, and the phase lag is suppressed to greatly improve the stability. When the gain of the characteristic curve 53 is 0 dB, the characteristic curve 56 has a phase margin of about 50 degrees. By adjusting the poles and the zero point in this way, even with the conventional circuit method, it is possible to greatly reduce the operating current and secure stability to create a stabilized power supply circuit, but a large capacitance value is required for C3. Therefore, there is a problem that it cannot be adopted for a small device, and as a result, the PSRR is greatly reduced. The characteristic curve 62 in FIG. 6 indicates that the PSRR characteristic corresponding to the characteristic curves 53 and 56 is deteriorated by about 30 dB or more at around 10 KHz as compared with 61.
[0054]
A characteristic curve 63 shows the PSRR characteristic when the operating current is set to 2 μA or less in the circuit of the conventional example in FIG. 2 for comparison. This indicates that the gain is insufficient due to the two-stage amplification configuration, and good characteristics are not obtained.
[0055]
From the above considerations, in the conventional circuit system, a good ripple rejection rate could not be achieved unless a very stable reference voltage source was used and the operating current of the error amplifier was not sufficiently increased.
[0056]
Numerous proposals have been made for ripple removal in response to the expansion of the market for mobile phones and wireless LANs. It is roughly divided into the following.
[0057]
(1) Method by optimizing pole zero frequency and increasing gain
US Pat. No. 5,631,593, US Pat.
USP 5,889,393
(3) Method of adaptively controlling pole zero frequency under load condition
USP 6,246,221;
(4) A method of removing with a ripple filter.
[0058]
JP-A-8-272461, US Pat. No. 5,130,579, US Pat. No. 4,327,319.
(5) How to cancel with reactor transformer
USP 5,686,464, JP 2001-339937
(6) Method of operating reference voltage source with own stabilized voltage
JP-A-5-35344, JP-A-2002-182758, JP-A-2002-182758
Classification (1), which has been proposed most frequently in recent years, has excellent ripple elimination characteristics, but the number of elements increases due to the addition of a current amplifier. The problem remains that cannot be done.
[0059]
Classification (2) has a problem in that an unstable state always appears at the moment of switching from the original power supply to the stabilized output stabilized by itself at the time of startup, and the time from the start of operation until the output is stabilized becomes longer. It is. In applications such as mobile phones in recent years, since the power supply operates intermittently in order to save power, it takes time to start up. Further, since an accurate level shift circuit is required between the error amplifier and the output transistor, the operating current also increases there, and low current consumption cannot be realized.
[0060]
In the classification (3), as in the classification (1), the design theory of the error amplifier is applied as it is, so that the operating current cannot be reduced, and the load current has a characteristic that includes a very large amount of noise with a drastic change. When the feedback is performed, the problem that the ripple removing characteristic is hindered is included.
[0061]
Classification (4) is that the ripple component includes a frequency band from a few Hz to a high frequency region. In particular, a large time constant is indispensable for removing a low frequency ripple by a filter, and it is necessary to integrate the ripple component on a semiconductor substrate. Is not feasible without significant cost increases.
[0062]
Classification (5) does not pose a problem because large reactor transformers cannot be integrated.
[0063]
Although the classification (6) is similar to the classification (2), the circuit configuration may be simplified because its own stabilized output voltage is supplied only to the reference voltage source. Although a high-precision circuit is not required for the reference voltage source, a large PSRR improvement effect can be obtained, but there are many disadvantages. The biggest disadvantage is that it does not start when the power is turned on. The second problem is an unstable operation due to positive feedback. Many additional circuit elements are required to solve these problems. Hereinafter, this classification (6) will be described in detail.
[0064]
[Problems of conventional startup control circuit]
FIG. 9 shows a conventional reference power source switching type stabilized power source circuit diagram. In FIG. 9, reference numeral 100 denotes an error amplifier, an example of the circuit is shown in FIG. 17, in which 10 is a first-stage differential amplifier circuit, and 20 is a second-stage phase inversion circuit. P1 and P2 indicate P-FETs, and N1 to N4 indicate N-FETs, respectively. C1 and R4 realize the phase compensation by the capacitance and the resistance. 9, 30 is an output circuit, FIG. 18 is an example of the circuit, 40 is an error detection voltage dividing circuit, FIG. 19 is an example of the circuit, 50 is a reference voltage circuit, FIG. A control circuit 81 is a switching P-FET switch.
[0065]
Although there are various methods of realizing the start-up control circuit 80, a typical circuit example is shown in FIG. 20, where N201 to N206 indicate N-FETs and P201 to P209 indicate P-FETs. In FIG. 20, reference numeral 51 denotes a reference voltage source / bias current source, 11 denotes a comparator circuit with hysteresis, and 21 denotes a buffer circuit. The basic operation is to apply the output voltage Vout of the stabilized power supply to the input terminal IN. When the output voltage Vout is lower than the voltage of the reference voltage source 51, the output Q is at a low level and the transistor P2 of the changeover switch 81 in FIG. Vdd is supplied to the reference voltage generation circuit 50 of FIG. 9 to activate the reference voltage. When the output voltage Vout in FIG. 9 rises and becomes higher than the voltage of the reference voltage source 51 in FIG. 20, the transistor P1 and the transistor P2 of the changeover switch 81 in FIG. 9 are turned off to supply the stabilized output voltage Vout. For example, even if the power supply voltage characteristic of the reference voltage generating circuit 50 in FIG. 9 is somewhat poor, the stability of the reference voltage can be easily obtained at about −10 μV (−100 dB) by the stabilized voltage input.
[0066]
That is, although the power supply voltage characteristics of the reference voltage circuits shown in FIGS. 7B and 7C are not as good as those shown in FIG. 7A, it is desirable because they can be manufactured in the same process as a standard digital circuit. If the processing dimension is smaller than the submicron, it is predicted that the control of the threshold value Vth of the depletion FET becomes difficult as in the circuit of FIG. Therefore, it is highly desirable to realize a stabilized power supply with low current consumption and high precision PSRR using the reference voltage circuits of (b) and (c).
[0067]
FIGS. 8A, 8B, and 8C show the transient response characteristic curves of the reference voltage circuit in FIGS. 7A, 7B, and 7C when the power supply slowly rises at 20 mS. Characteristic curves 81, 82, and 83 are shown corresponding to the reference voltage circuits of FIGS. 7A, 7B, and 7C, respectively. The characteristic curve 81 responds without delay, while the characteristic curves 82 and 83 indicate that the response responds with a great delay. This is related to a problem at the time of startup described later, and in the worst case, a state in which no output is output from the reference voltage circuit appears.
[0068]
FIGS. 10A, 10B and 10C show transient response operation waveforms of the conventional reference power source switching type stabilized power source circuit of FIG. In the figure, the horizontal axis represents the time axis, the power supply voltage Vdd represents a step waveform with a rise time of 5 μS, 101, 102, and 103 represent the waveform of the output voltage Vout, and 104 represents the waveform of the reference voltage VR.
[0069]
A waveform 101 in FIG. 10A is a response waveform when the power supply voltage Vdd is as high as 6 V, and indicates that the output voltage Vout oscillates and starts. This is presumably because the ringing vibration when the changeover switch is switched does not immediately converge. A waveform 102 in FIG. 10B shows a waveform when the phase compensation capacitance C1 is increased three times to 9 pF in order to secure stability in the error amplifier circuit in FIG. 2, and the ringing time is shorter than the waveform 101. Has become. In other words, FIG. 9 shows that in the conventional configuration example, a large phase compensation capacitance is indispensable to suppress the vibration. This is because the PSRR characteristic has a high frequency range as described in the consideration of the stability described above. Means large deterioration.
[0070]
A waveform 103 in FIG. 10C is a response characteristic when the power supply voltage Vdd is as low as 2.2 V, and shows that the output voltage Vout 103 starts with a large delay and the reference voltage VR104 also rises with a large delay. ing. This is presumed to be due to the long start-up time of the reference voltage circuit as seen in the transient response waveform of the reference voltage generation circuit in FIG. 8, but when this phenomenon becomes significant, the reference voltage VR does not start and the output A fatal problem occurs as a power supply that does not start the voltage Vout.
[0071]
As described above, in the conventional switching start-up control circuit, the start-up becomes unstable regardless of the type of the reference voltage circuit, and it is very difficult to operate stably in a desired power supply voltage range. Was. That is, stable operation is possible if the operation is performed in a very narrow range of the power supply voltage Vdd, but stable operation is difficult in a wide voltage range of a power source such as a battery. A number of additional circuit elements would be required to solve this and were not economical. For these reasons, it is a reality that very few products have been put into practical use while the conventional power supply switching method of the reference voltage can be expected to have an effect.
[0072]
The present invention proposes a method for realizing the method of the above classification (6) by solving the above-mentioned problem.
[0073]
[Problems to be solved by the invention]
An object of the present invention is to provide a standard manufacturing process, a low current consumption, a very high output voltage ripple rejection ratio without using high-precision circuit elements, and excellent PSRR characteristics with excellent stability. Power supply circuit.
[0074]
[Means for Solving the Problems]
The stabilized DC power supply circuit according to the first aspect of the present invention is
Means for generating a reference voltage and a bias current;
Voltage current output means for generating a voltage output,
Output detection means for detecting an error or variation of the output voltage;
Error amplification means for amplifying an error voltage with respect to the reference voltage,
In response to the voltage of the voltage / current output unit and the reference voltage, the control unit has an activation control unit that controls an output of the voltage / current output unit or an output of the error amplification unit,
The activation control unit has a predetermined intrinsic threshold determined by the size of a component element, and has a function of performing voltage conversion and holding in accordance with the output voltage of the voltage / current output unit, and It has a terminal for driving the output in a constant current manner and a terminal for driving and controlling the output of the error amplifier, and has a feature of controlling the drive until the voltage output reaches the intrinsic threshold.
[0075]
Further, the stabilized DC power supply circuit according to the second aspect of the present invention,
Means for generating a reference voltage and a bias current;
Voltage current output means for generating a voltage output,
Output detection means for detecting an error or variation of the output voltage;
Error amplification means for amplifying an error voltage with respect to the reference voltage,
In response to the voltage of the voltage / current output unit and the reference voltage, the control unit has an activation control unit that controls an output of the voltage / current output unit or an output of the error amplification unit,
The activation control unit has a predetermined intrinsic threshold determined by the size of a component element, and has a function of performing voltage conversion and holding in accordance with the output voltage of the voltage / current output unit, and A terminal for driving the output in a constant current manner and a terminal for driving and controlling the output of the error amplifier, and controlling the drive until the voltage output reaches the intrinsic threshold;
Having overcurrent protection means for outputting an overcurrent detection signal at the time of output overcurrent,
The terminal for driving the output of the reference voltage of the activation control means in a constant current manner is activated by the overcurrent detection signal, and the terminal for driving the output of the error amplifier is deactivated. .
[0076]
According to a third aspect of the present invention, in the DC stabilized power supply circuit according to the first or second aspect,
It is characterized in that the generation of the reference voltage and the generation of the bias current are configured as separate and independent means.
[0077]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0078]
[First Embodiment]
FIG. 11 shows a configuration diagram of a startup control stabilized power supply circuit of the present invention. 11 shows an error amplifier 100, FIG. 17 shows an example of the circuit, 30 shows an output circuit, FIG. 18 shows an example of the circuit, 40 shows an example of an error detecting voltage dividing circuit, FIG. 19 shows an example of the circuit, and 50 shows a reference voltage. FIG. 7 shows an example of a generator circuit. These components are the same as those used in the conventional example shown in FIG. In the figure, reference numeral 90 denotes a start control circuit of the present invention, and there is no switch 81 in the conventional example of FIG. The output voltage Vout is connected to the IN terminal of the startup control circuit 90. FIG. 12 shows a circuit example of the activation control circuit 90. In FIG. 12, P121, P122, and P123 represent P-FETs, and N121, N122, and N123 represent N-FETs. Reference numeral 120 denotes a voltage conversion holding circuit, in which a stabilized output voltage Vout is applied to an input terminal IN, and when the output exceeds an inversion threshold set by a transistor size ratio, the output is converted to a power supply voltage Vdd and held. I do. Since the inversion threshold value of the startup control circuit 90 of the present invention is determined by the size ratio and conductance of P122 and N122 when the input rises and at the falling edge, it is not necessary to prepare a separate threshold unlike the conventional example. The reference voltage circuit 51 and the bias circuit 51 in FIG. 20 in the conventional startup control circuit 80 are unnecessary. In addition, since P121 and P122 form a latch circuit, in a region where the difference between the voltage at the IN terminal and the power supply voltage is smaller than the sum of the threshold values of the P-FET and the N-FET, the current becomes constant after latching. Does not flow, so that current consumption does not increase. The conventional startup control circuit of FIG. 20 always requires an operating current, and is added to the entire operating current.
[0079]
In FIG. 12, reference numeral 121 denotes a VR drive circuit that drives the output reference voltage VR of the constant current drive reference voltage generation circuit 50 in a constant current manner. A constant current operation is added by the constant current source I121 to reduce the voltage dependency. In the figure, reference numeral 122 denotes a PD drive switch which controls the output of the error amplifier 100 at the time of startup and drives the output voltage to rise quickly. In other words, the output impedance of the error amplifier 100 is reduced at the time of startup, which assists the voltage / current output to respond quickly.
[0080]
The means for realizing the constant current source I121 in FIG. 12 may be a general high resistance, a current mirror transistor controlled by a constant current, or a large channel length in which the gate-source potential difference is controlled to be substantially constant. A transistor that performs a constant current operation using a transistor may be used.
[0081]
FIGS. 13A, 13B, 13C, and 13D show operation characteristics obtained by simulation of the operation of the startup control circuit of FIG. 12 when Vdd = 4V. Waveforms 134, 133, 132, and 131 indicate the input voltage of the IN terminal, the operating current IDD of the circuit, the output voltage of the node Q, and the output voltage of the node QX, respectively. When the rise of the voltage 134 at the input terminal IN is about 1.5 V, the Q output voltage 132 rises rapidly, the QX output voltage 131 is inverted, and when the IN input voltage is at a high level, the IDD operation is performed as shown by a waveform 133. The current is almost zero. Further, a desirable property of the start-up control circuit is that the Q output voltage 132 does not invert in a rectangular waveform like the QX output voltage 131 but changes via an intermediate level corresponding to the level of the IN input voltage. Because, in FIG. 12, the Q output voltage 132 is connected to the VR drive circuit 121 that drives the reference voltage circuit, so that when the level of the IN input voltage, that is, the output voltage Vout of the stabilized power supply is low, the drive is performed strongly, and When the voltage Vout starts and becomes higher than a certain level, the operation of weak driving is a desirable property for stable startup. This is realized by the Q output voltage 132 outputting an intermediate level voltage proportional to the output voltage Vout.
[0082]
In FIG. 13, the Q output voltage 132 and the QX output voltage 131 are inverted again at the fall of 1.4 V of the input voltage 134. Since the falling reversal threshold is determined by the size ratio as described above, it is possible to provide hysteresis. When the IN input terminal voltage 134 becomes a high level, the VR drive circuit 121 and the PD drive switch 122 stop the drive operation and enter a high impedance state. In other words, when the IN input terminal voltage 134 becomes high level, the operating current is not consumed, the output terminals of the VR drive circuit 121 and the PD drive switch 122 become high impedance, and no action is performed. An activation control circuit is realized.
[0083]
As shown in FIG. 12, the startup control circuit 90 of the present invention has a circuit element number that is only seven elements, which is less than half that of the conventional startup control circuit of FIG. We are saving. Therefore, there is a great effect in reducing the circuit area.
[0084]
FIGS. 14A and 14B show operation waveforms of the stabilized power supply circuit example FIG. 11 of the present invention. The horizontal axis is the time axis, and the power supply voltage Vdd is not shown, but is applied in a step waveform with a rise of 5 μS. Waveforms 141 and 142 indicate the output voltage Vout, and 143 and 144 indicate the output reference voltage of the reference voltage generation circuit 50. Waveforms 141 and 143 and 142 and 144 show waveforms when the power supply voltage Vdd is 6 V, which is larger than the output reference voltage, and when the power supply voltage is 2.2 V, which is almost the same as the output reference voltage. The phase compensation capacitance of the error amplifier 100 is 3 pF, and does not need to be tripled as in the conventional example. When the power supply voltage is 6 V, the output reference voltage 141 has neither overshoot nor undershoot, and has a rising time of about 5 μS at the maximum, showing a practically excellent rising waveform. Even when the power supply voltage Vdd is 2.2 V, as can be seen from the curve 142 of the voltage drop due to the output current, the problem at the time of startup has been solved without ringing or startup delay.
[0085]
According to the embodiment of the present invention, the drive of the reference voltage output terminal VR of the reference voltage generation circuit 50 of FIG. It is possible to launch. In the VR drive circuit 121 of FIG. 12, if the input voltage at which the forcible drive control of the reference voltage VR is stopped, that is, the inversion threshold of the start control circuit is set higher than the voltage at which the output voltage of the reference voltage circuit 50 in FIG. Since the startup does not fail, the startup can be guaranteed 100%. The voltage at which the output of the reference voltage circuit 50 stabilizes is, in the circuit example of FIG. 7 described above, (a) is the threshold voltage of the N-FET, and (b) and (c) are the threshold voltages of the N-FET and the P-FET. Since it is known that the sum is substantially equal to the sum, the inversion threshold value of the activation control circuit 90 can be set in advance. Further, since the start-up control circuit 90 of the present invention does not include the conventional changeover switch 81, even when the power supply voltage is high, the power supply input of the reference voltage circuit 50 does not greatly change, and ringing occurs in the output of the reference voltage generation circuit. It does not occur.
[0086]
The constant current here does not need to be an ideal constant current as described above, but may be any drive circuit in which the dependency of the power supply voltage Vdd is reduced. Regardless of the magnitude of the power supply voltage Vdd, it is desirable that the motor has a strong driving force at the start of startup and that the driving force decreases as the voltage approaches the target voltage. This cannot be achieved with a single transistor whose gate is controlled by high and low. Because, when the power supply voltage is large, the single transistor suddenly raises the reference voltage and rapidly raises the reference voltage, causing overshoot.When the power supply voltage is low, only a small current flows, and the activation of the reference voltage is delayed or It will not start.
[0087]
FIG. 15 is obtained by a simulation showing the PSRR characteristic of the present invention and the PSRR characteristic of the conventional example, and shows the attenuation on the vertical axis and the frequency on the horizontal axis. 11, reference numeral 151 denotes the PSRR characteristic of the embodiment of the present invention. In FIG. 11, reference numeral 152 denotes a case where the VDD input of the reference voltage generation circuit 50 is connected to the power supply line voltage Vdd instead of the stabilization voltage Vout in FIG. 7 shows PSRR characteristics of a conventional example connected to a line. The curve 152 shows a PSRR of about -53 dB, but the curve 151 reaches a maximum of -112 dB. In the embodiment of the present invention, the improvement is 59 dB.
[0088]
In the above equation (2), the ripple component ΔVref caused by the reference voltage circuit is only one of the three elements, but it can be seen from the characteristic example of FIG. 15 that it occupies a large weight. .
[0089]
[Second embodiment]
FIG. 16 shows a circuit diagram of a second embodiment of the present invention. In FIG. 16, reference numeral 100 denotes an error amplifier, an example of which is shown in FIG. An output circuit 30 is shown in FIG. Reference numeral 40 denotes an error detection voltage dividing circuit, an example of which is shown in FIG. A start control circuit 90 according to the present invention does not include the switching P-FET switch 81 in the conventional example shown in FIG. Reference numeral 50 denotes a reference voltage generation circuit, which is connected to the start control circuit 90. Reference numeral 60 denotes a bias current generation circuit, which is provided separately from the reference voltage generation circuit and is not connected to the start control circuit 90. In the second embodiment, the operation of the activation control circuit 90 is the same as that of the first embodiment except that the bias current generation circuit 60 is separated.
[0090]
[Third embodiment]
The start control operation of the present invention has one contradiction. That is, when the overcurrent protection function is added, the operation of the startup control of the present invention contradicts the operation of the overcurrent protection. The startup control of the present invention operates to quickly start the output voltage when it has not been started. On the other hand, the overcurrent protection operates so as to reduce the output voltage when the output current exceeds a certain level, thereby limiting the output current. Therefore, a circuit function for eliminating the inconsistency is required.
[0091]
FIG. 21 shows a configuration diagram of the third embodiment of the present invention. FIG. 21 shows a stabilized power supply circuit to which an overcurrent detection protection circuit 70 is added, and shows an error amplifier 100, an output circuit 30, an output voltage dividing circuit 40, and a reference voltage generation circuit 50. Same as 1. FIG. 23 is a circuit example of the overcurrent detection protection circuit 70. In the figure, reference numeral 231 denotes a current detection circuit, and 232 denotes a current detection holding circuit. The same signal as that of the P-FET gate of the output circuit 30 of FIG. 21 is supplied to the terminal PD, and P233 and P236 form a current mirror with the P-FET P3 of the output circuit 30, and are therefore substantially proportional to the FET size. Electric current flows. The current flows to R231 and R234, and the gate voltage of the N-FET rises, and N232 and N233, which are N-FETs, respectively, detect a certain amount of current or more and turn on, and then P234 and P235 turn on. The state shifts to the ON state, and the PD terminal is pulled toward the power supply voltage Vdd to limit the output current Iout. At the same time, the current detection and holding circuit 232 fixes and holds the current to a small value. This state is maintained until the output current Iout becomes equal to or less than the holding current to release the overcurrent state or the power supply voltage Vdd is reset, thereby preventing the output circuit 30 from being thermally damaged. At that time, the overcurrent detection output terminal DO outputs a predetermined positive potential.
[0092]
21 is a start control circuit of the present invention, and FIG. 22 shows an example of the circuit. In FIG. 22, an N-FET N124 and an overcurrent detection signal terminal KI are added as compared with the circuit example of FIG. 12 of the first embodiment. The overcurrent detection signal is a signal for performing special control at the time of overcurrent, and a DO terminal output from the overcurrent detection circuit 70 is connected to the overcurrent detection signal terminal KI. N124 is an N-FET, which receives the overcurrent detection signal, prevents the latch 120 from returning to the state during the output overcurrent state, inhibits the starting operation, and inhibits the PD drive circuit 122 from operating. Since the latch circuit configuration is used, it is easy to hold that state. If N124 has a lower impedance than N122, the state equivalent to the on state of N122 can be held, and the control signal of N122 changes to the full power supply voltage. It does not need to be a signal.
[0093]
FIG. 24 is a waveform diagram showing the operation of the start-up control circuit during the overcurrent operation obtained by simulation. The horizontal axis is the time axis. In the circuit example of FIG. 21, the resistance R3 connected to the output terminal Vout is gradually decreased, and after an overcurrent state occurs, the resistance R3 is increased again to increase the output current. The operation to decrease the value is obtained by simulation. In FIG. 24 (b), the characteristic curve 243 of the output current Iout gradually increases, and after detecting the overcurrent state, the holding current is held, and after a certain period of time, the load current is gradually reduced to reduce the overcurrent. It has returned from the state. A waveform 241 is an output voltage, a waveform 242 is a reference voltage, a waveform 244 is an output voltage of the error amplifier, a waveform 245 is a detection signal output of the overcurrent protection circuit 70, a waveform 246 is an output voltage waveform of the Q node of the startup control circuit, and a waveform 247. Indicates the output voltage of the QX node of the voltage conversion circuit of the activation control circuit.
[0094]
When the output current waveform 243 gradually increases and suddenly changes to a low holding current, an overcurrent is detected, and the voltage value of the output voltage waveform 241 in FIG. 24F also decreases to prevent the generation of Joule heat. The output circuit 30 is prevented from being destroyed. At this time, the voltage of the voltage waveform 247 of the QX node in FIG. 22 also changes to a low level, the VR drive circuit 121 of the activation control circuit is activated at a slightly lower level, a low reference voltage is generated, and an overcurrent occurs. It is activated so that it can be started quickly when released. Generating a reference voltage lower than the normal operation is a very important operation function so that the output does not overshoot when the overcurrent state is released, and the VR drive circuit 121 in the start control circuit FIG. Can be easily realized by setting the output impedance of the signal to a certain value or more.
[0095]
The waveform 246 of the QX node in FIG. 24E remains at a low level due to the plus voltage of the overcurrent detection signal waveform 245 in FIG. 24D, and the PD drive circuit 122 of the start control circuit in FIG. Therefore, the 244-PD signal is controlled by the overcurrent protection circuit 70 and holds the output circuit 30 near the off state. That is, the startup control circuit in FIG. 22 realizes a complicated function with the minimum additional element N124, and a very great effect is obtained. An equivalent function can be realized by a logic circuit. However, it is presumed that more elements are required as compared with the circuit in FIG. 22 when the signal levels are not uniform and the number of logic states is estimated.
[0096]
Therefore, the startup control circuit used in the present invention completely resolves serious inconsistencies in operation with only one additional element, and is very effective.
[0097]
【The invention's effect】
As described above, the present invention solves the problem of the conventional switching type starting circuit with a small number of elements, and remarkably improves the PSRR characteristic. Not only the stability at startup, but also the number of circuit elements is greatly reduced. In the case of a simple constant current source, for example, a high resistance element, and above all, when the power supply voltage Vdd is low, the current consumption of the startup control circuit can be reduced to almost zero. Especially effective. Further, since a device manufactured by a special manufacturing method is not used for the reference voltage circuit, it can be realized in a standard digital integrated circuit manufacturing process. The present invention does not specify the type of the reference voltage circuit, but can be applied to any reference voltage circuit.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a conventional stabilized power supply circuit.
FIG. 2 is a circuit diagram showing an example of a conventional stabilized power supply circuit.
FIG. 3 is a diagram showing an example of an output voltage-power supply voltage characteristic of a conventional stabilized power supply circuit.
FIG. 4 is an enlarged view of the scale of FIG.
FIG. 5 is a diagram showing gain-frequency characteristics and phase-frequency characteristics of an output of a conventional stabilized power supply circuit.
FIG. 6 shows PSRR characteristics of a conventional stabilized power supply circuit.
FIGS. 7A to 7C are circuit diagrams of a reference voltage source.
FIG. 8 is a diagram showing a transient response characteristic of a reference voltage circuit.
FIG. 9 is a circuit schematic diagram of a conventional switchable stabilized power supply.
FIG. 10 is a diagram showing a transient response characteristic of a conventional switched-type stabilized power supply.
FIG. 11 is an overall block diagram of Embodiment 1 of the present invention.
FIG. 12 is a diagram showing a circuit example of a start-up control circuit of the present invention.
FIG. 13 is a diagram showing an operation characteristic curve of the startup control circuit of the present invention.
FIG. 14 is a diagram showing an operation characteristic curve of the stabilized power supply circuit of the present invention.
FIG. 15 is a diagram showing PSRR characteristic curves of the present invention and a conventional example.
FIG. 16 is an overall block diagram of Embodiment 2 of the present invention.
FIG. 17 is a diagram illustrating an example of an error amplifier circuit.
FIG. 18 is a diagram illustrating a circuit example of a voltage / current output circuit.
FIG. 19 is a diagram illustrating a circuit example of an error detection voltage dividing circuit.
FIG. 20 is a diagram illustrating an example of a conventional startup control circuit.
FIG. 21 is an overall block diagram of a third embodiment of the present invention.
FIG. 22 is a diagram showing a circuit example of an overcurrent protection start control circuit according to the present invention.
FIG. 23 is a diagram illustrating a circuit example of an overcurrent detection protection circuit.
FIG. 24 is a diagram showing an operation characteristic curve of the overcurrent protection start control circuit of the present invention.
[Explanation of symbols]
1, 2 Voltage supply terminals
3 Output terminal
10 Differential amplifier circuit
20 phase inversion amplifier
30 output circuit
40 output voltage divider
50 Reference voltage generation circuit
60 Bias current generation circuit
70 Overcurrent protection circuit
80 Conventional startup control circuit
81 Changeover switch circuit
90, 91 Start-up control circuit of the present invention
100 error amplifier

Claims (3)

Means for generating a reference voltage and a bias current;
Voltage current output means for generating a voltage output,
Output detection means for detecting an error or variation of the output voltage;
Error amplification means for amplifying an error voltage with respect to the reference voltage,
In response to the voltage of the voltage / current output unit and the reference voltage, the control unit has an activation control unit that controls an output of the voltage / current output unit or an output of the error amplification unit,
The activation control unit has a predetermined intrinsic threshold determined by the size of a component element, and has a function of performing voltage conversion and holding in accordance with the output voltage of the voltage / current output unit, and A DC stabilized power supply having a terminal for driving an output in a constant current manner and a terminal for driving and controlling the output of the error amplifier, and performing drive control until the voltage output reaches the intrinsic threshold. circuit. Means for generating a reference voltage and a bias current;
Voltage current output means for generating a voltage output,
Output detection means for detecting an error or variation of the output voltage;
Error amplification means for amplifying an error voltage with respect to the reference voltage,
In response to the voltage of the voltage / current output unit and the reference voltage, the control unit has an activation control unit that controls an output of the voltage / current output unit or an output of the error amplification unit,
The activation control unit has a predetermined intrinsic threshold determined by the size of a component element, and has a function of performing voltage conversion and holding in accordance with the output voltage of the voltage / current output unit, and A terminal for driving the output in a constant current manner and a terminal for driving and controlling the output of the error amplifier, and controlling the drive until the voltage output reaches the intrinsic threshold;
Having overcurrent protection means for outputting an overcurrent detection signal at the time of output overcurrent,
According to the overcurrent detection signal, a terminal for driving the output of the reference voltage of the activation control means in a constant current manner is activated, and a terminal for driving the output of the error amplifier is deactivated. , DC stabilized power supply circuit. 3. The stabilized DC power supply circuit according to claim 1, wherein the generation of the reference voltage and the generation of the bias current are configured as separate and independent means.

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