JP2004310220A - Data processor, nonvolatile semiconductor storage device, and image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor and image processor capable of enhancing security by preventing the leak of data, and a nonvolatile semiconductor storage device capbale of reducing the processing load on a side using a memory. <P>SOLUTION: A CPU 12 executes, when a cluster with invalid data is present in reference to status information stored in a main memory 13, zero clear of the cluster concerned. The zero clear is realized by forming bit-inverted data of zero clear object data of a flash memory 20 by the CPU 12 and writing the formed data in the storage area of the zero clear object data. The CPU 12 also erase, when a block all clusters of which are zero-cleared is present in reference to the status information, all data in the block concerned. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor storage device such as a flash memory, a data processing device including the nonvolatile semiconductor storage device, and an image processing device.
[0002]
[Prior art]
As a memory provided in an image processing device (data processing device) such as a facsimile or an MFP, there is a flash memory (non-volatile semiconductor storage device) that can hold data even when the power is turned off. In a flash memory, for example, erasing is performed by setting all bits in an erasing unit area to “1”, and writing is performed by electrically changing the erased bits from “1” to “0” (for example, And Patent Document 1).
[0003]
In the case of a flash memory, since an erasing unit area is relatively large, for example, 64 kbytes, a plurality of data are often stored together in one erasing unit area (block). For example, by dividing one erasing unit area into a plurality of data unit areas (clusters) and storing data in each data unit area, the storage capacity can be used efficiently.
[0004]
[Patent Document 1]
JP-A-2000-90678
[0005]
[Problems to be solved by the invention]
As described above, since data is erased for each erasing unit area, data erasing cannot be performed until all data (all data unit areas) stored in the erasing unit area becomes unnecessary. Therefore, data erasure cannot be performed as long as valid data remains in the erasure unit area, and other unnecessary data remains stored.
[0006]
Also, prior to data erasure, by performing pre-write processing of clearing (clearing all bits) in the erasure unit area to “0” (zero clear), the characteristics (potentials) when the erasure unit area is erased collectively may be uniformed. is there. However, also in this case, the prewrite process cannot be performed until all data in the erasing unit area can be erased, and unnecessary data remains in the flash memory.
[0007]
If the unnecessary data remains in the flash memory, the unnecessary data may be illegally read from the flash memory, which poses a problem in security.
[0008]
The present invention has been made in view of such circumstances, and it is possible to prevent data leakage and enhance security by writing to an unwritten bit portion in a bit string of unnecessary data. It is an object to provide a simple data processing device and an image processing device.
[0009]
Further, the present invention provides a non-volatile semiconductor memory device capable of reducing the processing load on the side using the memory by writing the unwritten bit portion of the write target address on the memory side. That is another purpose.
[0010]
[Means for Solving the Problems]
A data processing device according to the present invention includes a nonvolatile semiconductor storage device, divides a storage area of the nonvolatile semiconductor storage device into a plurality of blocks, writes a plurality of data in one block, and stores unnecessary data in block units. The data processing device for erasing data in (1) is characterized by comprising write control means for writing data to an unwritten bit portion in a bit string of unnecessary data.
[0011]
The data processing device according to the present invention includes a creating unit that creates inverted data obtained by bit-inverting unnecessary data, and the writing control unit uses the inverted data created by the creating unit to generate the inverted data. Characterized in that it is configured to write to an unwritten bit portion in a bit string of the data.
[0012]
The data processing device according to the present invention is characterized by including a storage unit that stores identification information of data written in an unwritten bit portion by the write control unit.
[0013]
The data processing device according to the present invention is characterized in that, when all data in a block becomes unnecessary, the data of the block is erased.
[0014]
A non-volatile semiconductor storage device according to the present invention receives a write instruction, a write destination address, and write data by a receiving unit, and transfers the write data received by the receiving unit to the write destination address received by the receiving unit. In the nonvolatile semiconductor memory device for writing, the receiving means is configured to receive a write instruction to a non-written bit part and a write target address, and the receiving means writes the data to the unwritten bit part. A write control unit for writing an unwritten bit portion in a bit string of data written to the write target address received by the receiving unit when the write instruction is received.
[0015]
An image processing apparatus according to the present invention includes a nonvolatile semiconductor storage device that stores image data to be processed, divides a storage area of the nonvolatile semiconductor storage device into a plurality of blocks, and writes a plurality of image data in one block. An image processing apparatus for erasing unnecessary image data in block units is characterized in that the image processing apparatus further comprises a write control means for writing an unwritten bit portion in a bit string of the unnecessary image data.
[0016]
In the present invention, writing is performed by the write control means on the unwritten bit portion in the bit string of the data that is no longer needed. For example, inverted data obtained by bit-inverting unnecessary data is created by creating means, and the inverted data created by the creating means is used by the writing control means to write unwritten data in the bit string of the unnecessary data. Write to the bit portion. For example, when the erase state is “1”, writing is performed from “1” to “0”. By writing to the unwritten bit portion in the bit string of the unnecessary data, the unnecessary data becomes different from the original data. In addition, by setting all the bits of the bit string of the unnecessary data to the writing state, the data is cleared (cleared to zero). In the flash memory, only writing from "1" to "0" is performed, and writing from "0" to "1" is not executed (erased to "1" collectively in block units), so data is unnecessary. By writing data obtained by bit-inverting the data into the cluster that has become, the cluster can be cleared to zero. By writing to unnecessary data and changing or zero-clearing the data content, data security is enhanced. Further, since the unwritten bit portion is written using the bit-inverted data, it is possible to prevent the flash memory from being destroyed by writing "0" to "0".
[0017]
In the present invention, the write control means stores the identification information such as the address of the data written in the unwritten bit portion in the storage unit. Since the identification information of the data written to the unwritten bit portion is stored in the storage unit, it is easy to grasp the completion / incomplete of the writing of the unwritten bit portion for each unnecessary data. It becomes possible to do. Therefore, it becomes easy to execute the writing process of the unwritten bit portion independently of other processes, or to execute it between other processes.
[0018]
In the present invention, data erasure in block units is performed when all data in a block becomes unnecessary. For example, when the storage area of the nonvolatile semiconductor memory device is divided into a plurality of blocks and the blocks are further divided into a plurality of clusters, when data of all clusters in the block becomes unnecessary, the data in the block is erased. I do. The life of the flash memory depends on the number of erases, and when the data in all clusters is no longer needed, the data is erased, minimizing the number of erases and extending the life of the flash memory. is there.
[0019]
In the present invention, an instruction to write to an unwritten bit portion and a write target address are received by the receiving means of the nonvolatile semiconductor memory device, and the unwritten bit portion in the bit string of the write target address received by the receiving means is received. Then, writing is performed by the writing control means. For example, when “1” is in the erased state, the “1” portion (unwritten bit portion) existing in the bit string in the write target address is written to “0” (written state). A data processing device including such a nonvolatile semiconductor memory device provides a nonvolatile semiconductor memory device by giving an address of unnecessary data (address to be written) and a write instruction to an unwritten bit portion. The side can automatically execute writing to the unwritten bit portion in the specified address. The data processor only needs to give a write instruction to the unwritten bit portion and a write target address, and it is possible to reduce the load of memory management.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be specifically described with reference to the drawings showing the embodiments.
(First Embodiment)
FIG. 1 is a block diagram showing an example of a data processing device according to the present invention. The data processing device includes a CPU (Central Processing Unit) 12, a main memory 14 such as a DRAM (Dynamic Random Access Memory), a PROM (Programmable Read Only Memory) 16, and a flash memory (non-volatile semiconductor storage device) 20. And each is connected to a common bus.
[0021]
The flash memory 20 includes a memory main body 24 such as a memory array, and a memory control unit 22 including an address decoder and a voltage control circuit. The storage area of the flash memory 20 (memory main body 24) is divided into a plurality of blocks, which are units of erasing. In the example of FIG. 1, the block is divided into n blocks (n is an integer of 3 or more) (block 1, block 2,..., Block n). Each block is divided into a plurality of clusters, and each cluster stores, for example, data in units of 8 bits.
[0022]
In this description, it is assumed that “1” is erased from the flash memory 20 and writing is performed from “1” to “0”. The erasing process from “0” to “1” is performed in block units, and the rewriting (erasing) from “0” to “1” in data units (cluster units) is performed in the flash memory 20 (memory control unit). 22) will not be accepted and will not be executed.
[0023]
The CPU 12 operates as means (write control means) for writing an unwritten bit portion in the bit string of unnecessary data. Further, the CPU 12 operates as a means (creating means) for creating inverted data obtained by bit-inverting unnecessary data, and using the created inverted data, an unwritten bit in the bit string of the unnecessary data. Write to the part.
[0024]
In this description, the CPU 12 writes inverted data of the unnecessary data into the cluster where the unnecessary data is stored. As described above, since the flash memory 20 (memory control unit 22) does not accept rewriting (erasing) from “0” to “1”, inverted data of unnecessary data is replaced with the unnecessary data. By writing to the stored cluster, only the "1" portion becomes "0", and the data of the cluster is cleared to zero (all bits = "0").
[0025]
The CPU 12 operates as each unit described above, for example, by reading and executing the zero clear control program stored in the PROM 16.
[0026]
The main memory (storage unit) 14 stores status information that functions as identification information of data written in the unwritten bit portion by the CPU 12. In the present description, the status information functions as information for identifying the cluster in which the inverted data has been written (cleared to zero) by the CPU 12.
[0027]
The status information stores the status of each cluster. For example, when the CPU 12 writes data to a predetermined cluster of the flash memory 20, the CPU 12 updates the status of the predetermined cluster in the status information to “valid data”. Similarly, the CPU 12 updates the state of the cluster to “invalid data” when data is no longer needed, updates it to “zero cleared” when zero-cleared, and “erased” when erased. Update to
[0028]
The CPU 12 refers to the status information and erases data in block units when all data (all clusters) in the block is unnecessary or cleared to zero. In this description, in order to perform the prewrite process, the CPU 12 clears unnecessary data to zero, and performs erasing when all data in the block is cleared to zero.
[0029]
The CPU 12 reads and executes a data management program stored in the PROM 16, for example, to execute various processes related to data storage of the flash memory 20, such as the above-described data erasing, writing, zero clearing, and status information updating. I do.
[0030]
Next, data erasing using the data processing device according to the present invention will be described. FIG. 2 is a flowchart illustrating an example of the execution procedure of block erasure. The CPU 12 performs processes such as erasing, data writing, and zero clearing on the flash memory 20, and changes status information according to a change in the state of each cluster (erased, valid data, invalid data, or zero cleared) due to the performed process. Update.
[0031]
The CPU 12 refers to the status information, and if there is a cluster in which the data has become invalid (S10: YES), executes the zero clear of the cluster in which the data has become invalid (S12). For example, a cluster whose status information state is “invalid data” is set as a zero clear target cluster.
[0032]
FIG. 3 is a flowchart illustrating an example of the execution procedure of the zero clear. The CPU 12 reads the invalid data of the cluster to be cleared to zero from the flash memory 20 and saves (stores) it in the main memory 14 (S30). The CPU 12 sets (sets) the leading address of the invalid data saved in the main memory 14 in the variable rAddr stored in the main memory 14 (S32). Further, the CPU 12 sets (sets) the head address of the cluster to be zero-cleared in the flash memory 20 in the variable wAddr stored in the main memory 14 (S34).
[0033]
The CPU 12 reads and stores the unit data stored at the address of the main memory 14 indicated by rAddr in the variable SD stored in the main memory 14 (S36). Further, the CPU 12 reads the data stored in the SD, performs bit inversion, and stores the data obtained by bit-inverting the SD in a variable WD stored in the main memory 14 (S38).
[0034]
The CPU 12 executes a WD (data stored in the WD) write command for the address of the flash memory 20 indicated by wAddr (S40). The flash memory 20 (memory control unit 22) that has received the write command and the WD from the CPU 12 writes the WD to the address indicated by wAddr. Since WD is data obtained by inverting data (same data as SD) written in the write destination of the flash memory 20, "0" is written in the "1" portion and "1" is written in the "0" portion. However, writing of “1” to the “0” portion is not accepted by the flash memory 20 (memory control unit 22), and the “0” portion remains “0”. Therefore, "0" is written only in the "1" portion, and all bits of the write destination data are cleared to "0" (cleared to zero).
[0035]
The CPU 12 sets the next address in rAddr and wAddr, for example, by adding 1 to rAddr and wAddr (S42). If wAddr exceeds the final address of the zero-clear target cluster (S44: YES), the process ends because zero-clear of the zero-clear target cluster has been completed. If wAddr has not exceeded (S44: NO), the same process is performed. (S36, S38, S40, S42).
[0036]
When confirming completion of the zero clear (S14 in FIG. 2: YES), the CPU 12 updates the status information (S16). For example, the CPU 12 updates the status of the cluster for which the zero clear has been completed in the status information stored in the main memory 14 to “zero cleared”.
[0037]
In addition, referring to the status information, if there is a block in which all the clusters are “zero cleared” (S18: YES), the CPU 12 executes erasure of all data in the block (hereinafter, block erasure) (S20). ). Block erasure can be performed in the same manner as in the past. If there is no block in which all clusters have been “zero cleared” (S18: NO), the above-described zero clear processing is performed (S10 to S16).
[0038]
When confirming the completion of the block erasure (S22: YES), the CPU 12 updates the status information (S24). For example, the CPU 12 updates the status of each cluster in which the block erasure has been executed in the status information stored in the main memory 14 to “erased”. Thereafter, the processing shown in FIGS. 2 and 3 is repeated.
[0039]
FIGS. 4 and 5 are diagrams showing examples of changes in the state (erased, valid data, invalid data, and zero-cleared) of each cluster in the block. 4 and 5, a block A having four clusters (clusters A1, A2, A3, and A4) is taken as an example. In FIG. 4A, all clusters in block A have been erased (all bits = "1"). When the CPU 12 writes data in the clusters A1 and A2, as shown in FIG. 4B, the clusters A1 and A2 become valid data, and the CPU 12 sets the status of the clusters A1 and A2 in the status information to "valid data". To ".
[0040]
Thereafter, when the processing of the CPU 12 using the data of the cluster A1 is completed and the data of the cluster A1 becomes unnecessary, as shown in FIG. 4C, the cluster A1 becomes invalid data and the CPU 12 The status of the cluster A1 in the information is updated to “invalid data”. When there is a cluster in which data has become invalid, zero clear processing (and updating of status information) is performed as described above (FIGS. 2 and 3), and as shown in FIG. 4D, cluster A1 is cleared to zero. (All bits = "0").
[0041]
Thereafter, as shown in FIG. 5A, the CPU 12 writes data in the clusters A3 and A4 and clears the cluster A2 to zero. In the state of FIG. 5A, when the processing of the CPU 12 using the data of the clusters A3 and A4 ends and the data of the clusters A3 and A4 become unnecessary, as shown in FIG. , Clusters A3 and A4 become invalid data, and the CPU 12 updates the status of the clusters A3 and A4 in the status information to “invalid data”.
[0042]
When there is a cluster in which data has become invalid, zero clear processing (and updating of status information) is performed as described above (FIGS. 2 and 3), and clusters A3 and A4 as shown in FIG. Is cleared to zero (all bits = "0"). This means that all clusters in the block A have been cleared to zero. If there is a block in which all clusters have been cleared to zero, block erasure (and updating of status information) is performed as described above (FIGS. 2 and 3), and as shown in FIG. Are erased, and all clusters are erased (all bits = "1"). FIG. 5D shows the same state as FIG. 4A.
[0043]
(Second embodiment)
FIG. 6 is a block diagram showing an example of a data processing device provided with the nonvolatile semiconductor memory device according to the present invention. The data processing device includes a CPU 12, a main memory 14, a PROM 16, and a flash memory (non-volatile semiconductor storage device) 20, similarly to the first embodiment (FIG. 1), each of which is connected to a common bus. It is connected. The flash memory 20 includes a memory main body 24 such as a memory array, and a memory control unit 22 including an address decoder and a voltage control circuit.
[0044]
In the present description, when the memory control unit 22 of the flash memory 20 receives a write instruction to write an unwritten bit portion and a write target address from the CPU 12, the memory control unit 22 stores the unwritten data in the bit string of the received write target address. It operates as a means for writing to the bit portion (write control means (zero clear control section)). For example, when the CPU 12 writes a command including a size specification for zero-clearing to the head address of the cluster to be zero-cleared in the flash memory 20, the memory control unit 22 specifies the cluster in which the command is written as a reference address. Writing is performed on the unwritten bit portion of the bit string within the size (zero clear size). In this description, the memory control unit 22 clears (zeros) each cluster within the size (address range) specified by the command to “0”. Zero clearing of each cluster within the designated size can be executed by the memory control unit 22 in the same manner as in the first embodiment. Variables and the like necessary for execution of the processing are stored in a memory (not shown) in the memory control unit 22.
[0045]
A data management program is stored in the PROM 16 as in the first embodiment. The block erasing procedure is the same as in the first embodiment (FIG. 2).
[0046]
FIG. 7 is a flowchart illustrating an example of the execution procedure of the zero clear. The CPU 12 writes a command including the designation of the size to be cleared to zero at the start address of the cluster to be cleared to zero in the flash memory 20 (S50). The memory control unit 22 of the flash memory 20 converts the bit “1” of each bit string within the specified size range into the bit “0” from the address where the command is written (S52).
[0047]
The CPU 12 checks the zero clear state of the flash memory 20 (S54), and updates the status information when the zero clear is completed (S56: YES). The CPU 12 only needs to give the flash memory 20 a command including an address range to be cleared to zero, and the processing load on the CPU 12 is reduced.
[0048]
In each of the above-described embodiments, unnecessary data is cleared to zero (all bits = “0”). However, “0” may be written in an arbitrary “1” portion of a bit string of unnecessary data. It is possible. For example, it is possible to write "0" in any one of the "1" portions or the random portion of the bit string of unnecessary data.
[0049]
The present invention can be applied to any data processing device including a nonvolatile semiconductor memory device. For example, the present invention can be applied to an image processing apparatus such as an MFP (Multi Function Peripheral). FIG. 8 is a block diagram illustrating an example of an image processing apparatus including a nonvolatile semiconductor storage device (flash memory) 20. An MFP (image processing apparatus) 10 includes a scanner unit 60 that reads image data of a document, a printer unit 50 that prints image data, and a control unit 30 that performs image processing control including control of the scanner unit 60 and the printer unit 50. Is provided.
[0050]
The scanner unit 60 includes an image reading unit 64 having a charge coupled device (CCD) or the like, a scanner control unit 62 that performs reading control including scanning of a document, and the like. The printer unit includes an LSU (Laser Scanning Unit) 54, a printer control unit 52 that performs print control including feeding of recording paper, and the like.
[0051]
The control unit 30 includes a laser control IC 36 for controlling the LSU 54, an image memory (flash memory: nonvolatile semiconductor storage device) 20 for storing image data received from the image reading unit 64, an image processing IC 32 for processing image data, and an NIC ( A network interface card (38), a hard disk controller 40, and the CPU 12 are connected to a common bus. A hard disk 42 is connected to the hard disk controller 40, and the main memory 14, the PROM 16, the image memory 20, a non-volatile memory 34 for storing various settings, an operation unit 44, an LCD (Liquid Crystal Display) 46, and a scanner are connected to the CPU 12. The control unit 62 and the printer control unit 52 are connected, and an external device such as a computer 70 is connected to the NIC 38.
[0052]
The MFP 10 stores the image data read by the image reading unit 64 in the image memory 20 and outputs the image data from the printer unit 50 under the control of the CPU 12, or stores the image data received from the computer 70 or an external facsimile device in the image memory 20. The image data can be stored and output from the printer unit 50, or the image data read by the image reading unit 64 can be stored in the image memory 20 and transmitted from the NIC 38 to the computer 70 or an external facsimile machine.
[0053]
Writing, clearing, and erasing of image data in the image memory (flash memory) 20 can be controlled by the CPU 12 in the same manner as in the above-described embodiments. Further, data writing, zero clearing, and erasing in the nonvolatile memory 34 in which various settings are stored can be performed by the CPU 12 in the same manner as in the above-described embodiments.
[0054]
【The invention's effect】
According to the present invention, by writing to the unwritten bit portion in the bit string of the unnecessary data, the unnecessary data becomes different from the original data. Further, by setting all the bits of the bit string of the unnecessary data to the write state, the unnecessary data is cleared (zero-cleared). By writing to the unwritten bit portion of the unnecessary data, it is possible to prevent the leakage of the unerased data and enhance the security.
[0055]
According to the present invention, "0" is set to "0" in order to write the unwritten bit portion in the bit string of the unnecessary data by using the data obtained by bit-inverting the unnecessary data. It is possible to prevent the nonvolatile semiconductor memory device from being destroyed by writing. In addition, by erasing data when all data in the block becomes unnecessary, the number of erasures can be minimized and the life of the nonvolatile semiconductor memory device can be extended.
[0056]
According to the present invention, the non-volatile semiconductor memory device receives a write instruction for a non-written bit portion and a write target address, and writes the non-written bit portion in the bit string of the received write target address. Is performed, the side using the nonvolatile semiconductor memory device only needs to give a write instruction and a write target address, and it is possible to reduce the load of memory management.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a data processing device according to the present invention.
FIG. 2 is a flowchart illustrating an example of an execution procedure of block erasure;
FIG. 3 is a flowchart illustrating an example of an execution procedure of zero clear.
FIG. 4 is a diagram illustrating an example of a change in the state of each cluster in a block.
FIG. 5 is a diagram illustrating an example of a change in the state of each cluster in a block.
FIG. 6 is a block diagram illustrating an example of a data processing device including a nonvolatile semiconductor memory device according to the present invention.
FIG. 7 is a flowchart illustrating an example of an execution procedure of zero clear.
FIG. 8 is a block diagram illustrating an example of an image processing apparatus according to the present invention.
[Explanation of symbols]
10 MFP (image processing device)
12 CPU
14 Main memory
16 PROM
20 Flash memory (non-volatile semiconductor storage device)
22 Memory control unit
24 Memory body
30 Control section
50 Printer section
60 Scanner unit

Claims (6)

In a data processing device comprising a nonvolatile semiconductor memory device, dividing a storage area of the nonvolatile semiconductor memory device into a plurality of blocks, writing a plurality of data in one block, and erasing unnecessary data in block units,
A data processing apparatus, comprising: a write control unit that writes data to an unwritten bit portion in a bit string of unnecessary data. Providing a means for creating inverted data obtained by bit-inverting unnecessary data,
The writing control means is configured to write the unwritten bit portion in the bit string of the unnecessary data using the inverted data created by the creating means. Item 2. The data processing device according to Item 1. 3. The data processing device according to claim 1, further comprising: a storage unit configured to store identification information of data written in an unwritten bit portion by the write control unit. 4. The data processing apparatus according to claim 1, wherein the data in the block is erased when all the data in the block becomes unnecessary. In a nonvolatile semiconductor memory device, a write instruction, a write destination address, and write data are received by a receiving unit, and the write data received by the receiving unit is written into a write destination address received by the receiving unit.
The receiving means is configured to receive a write instruction to a non-written bit portion and a write target address,
When the receiving unit receives an instruction to write to the unwritten bit portion, writing is performed to write to the unwritten bit portion in the bit string of the data written at the write target address received by the receiving unit. A nonvolatile semiconductor memory device comprising a control unit. A nonvolatile semiconductor storage device for storing image data to be processed; a storage area of the nonvolatile semiconductor storage device is divided into a plurality of blocks; a plurality of image data are written in one block; In an image processing device that erases in units,
An image processing apparatus comprising: a writing control unit that writes data to an unwritten bit portion in a bit string of unnecessary image data.

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