JP2004303987A - Wafer map automatic discrimination control method, semiconductor inspection apparatus, semiconductor manufacturing apparatus, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wafer map automatic discrimination control method and a semiconductor inspection apparatus for automatically and properly detecting the tendency of a wafer map, and to provide a semiconductor manufacturing apparatus and a semiconductor device. <P>SOLUTION: A flowchart indicating the wafer map automatic discrimination control method includes a step S1 of acquiring positional information for discriminating a defective part of a semiconductor wafer in response to an inspection mode of a defect inspection apparatus or the like; a map processing step of dividing the surface of the semiconductor wafer into areas on information processing by a map processing process, and overlapping the result on the fault location information obtained by the defect inspection apparatus as shown in a step S2; an arithmetic processing step in a step 5 of discriminating whether or not the density or the number of defective parts exceeds a preset reference value on the basis of the positional information in the step S1 for each area in the step S2, and displaying the result in a way capable of identifying the inside of the reference value and the other parts; and a defective area information acquisition step in the step S5 of carrying out identification purpose display control for areas discriminated in excess of the reference value, and areas adjacent to the discriminated areas respectively as areas with defective tendency. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to semiconductor device manufacturing, and in particular, a wafer map automatic determination control method, a semiconductor inspection device, a semiconductor manufacturing device, and a semiconductor device that determine and recognize an abnormality such as a defect in a semiconductor wafer, a pattern defect, or an adhesion of a foreign substance as a wafer map tendency. Equipment related.
[0002]
[Prior art]
2. Description of the Related Art A semiconductor wafer (hereinafter, also referred to as a wafer) is formed by repeatedly forming a pattern of an integrated circuit necessary for manufacturing an LSI by, for example, reduction projection exposure. That is, the reduction projection exposure apparatus on which a predetermined reticle is set repeatedly exposes the pattern while moving the projection area on the wafer one after another. As a result, a predetermined number of integrated circuit chip areas are obtained in the wafer. A plurality of patterns to be exposed are aligned in the scribe line area. In the meantime, a chip product is completed through various processing steps such as a film forming step, an etching step, and a cleaning step.
[0003]
With the increase in the functions of LSIs, chip products are constantly required to be integrated on a large scale and to reduce design rules. Then, it is necessary to secure as many chip products as possible from a single semiconductor wafer according to the design rule at that time, such as logic products and memory products. In addition, the mass production must be performed with uniform performance and high yield.
[0004]
The number of defects in the wafer increases or decreases due to the search for optimization conditions and process control in the LSI manufacturing process. Inspection of foreign matter adhering to a wafer due to pattern defects or particles generated due to a defect in an exposure pattern is generally achieved by a comparative inspection. That is, an image of the same pattern area in an adjacent integrated circuit chip area is fetched and compared and inspected. As a result, for example, the coordinate position of the abnormal location is plotted and displayed on a wafer map. An operator or the like actually looks at the wafer map, and determines a concentrated portion of an abnormal portion, a scattered degree, and other deviations and tendencies. This will be reflected in future improvements in process control and manufacturing lines, changes in inspection recipes, and the like.
[0005]
[Problems to be solved by the invention]
However, in the conventional wafer map, the skill of an operator or the like who makes a determination is affected, and variation occurs among the determination persons. As a result, there is a possibility that appropriate measures for semiconductor manufacturing may not be sufficiently performed.
The present invention has been made in view of the above circumstances, and provides a wafer map automatic determination control method, a semiconductor inspection device, a semiconductor manufacturing device, and a semiconductor device that automatically detect an appropriate wafer map tendency. Is what you do.
[0006]
[Means for Solving the Problems]
A wafer map automatic determination control method according to the present invention includes: a first information obtaining step of obtaining position information for specifying an abnormal portion of a semiconductor wafer; and a map processing step of dividing a surface of the semiconductor wafer into an information processing area. And an arithmetic processing step of determining whether the density or the number of abnormal points based on the position information in each of the sections exceeds a preset reference value, and a first section of the sections that exceeds the reference value A second information acquisition step of storing a second area adjacent to the first area, and a display step of displaying at least the first area and the second area in a recognizable manner. .
[0007]
According to the wafer map automatic determination control method according to the present invention, the map of the semiconductor wafer is divided into predetermined areas by the map processing step separately from the first information acquisition step. In the arithmetic processing step, a determination determined according to the density or the number of abnormal portions in each area is automatically made. In addition, regions in the same tendency are automatically determined by the second information acquisition step.
[0008]
In the above-described wafer map automatic determination control method according to the present invention, the following features are given as preferred embodiments.
The map processing step is characterized in that the areas correspond to each other such that a mesh-shaped map sheet of a predetermined area unit is put on the surface of the semiconductor wafer.
The size of the area can be changed.
The reference value can be changed in setting.
The second information acquiring step is characterized in that an area existing on the upper, lower, left and right sides of the first area is a second area.
The number or total number of either the first area or the second area in the second information acquisition step is related to the evaluation of the tendency of the wafer map.
[0009]
A semiconductor inspection apparatus according to the present invention uses a wafer map automatic determination control method having any one of the features described above. It becomes easy to determine the tendency of the map at the abnormal inspection location.
[0010]
A semiconductor inspection apparatus according to the present invention includes an inspection mechanism that acquires position information that specifies an abnormal portion of a semiconductor wafer, and divides the surface of the semiconductor wafer into information processing areas, and applies the position information to each of the areas. An arithmetic and control unit for determining whether or not the density or the number of abnormal points based on the reference value exceeds a preset reference value; and a first section exceeding the reference value and a second section adjacent to the first section among the sections. It is characterized by including a storage unit for storing information of each area, and a display unit for displaying at least the first area and the second area in a recognizable manner.
[0011]
According to the semiconductor inspection apparatus of the present invention, the map of the semiconductor wafer is divided into predetermined areas separately from the inspection mechanism, and is processed by the arithmetic and control unit. That is, the determination determined according to the density or the number of abnormal portions in each area is automatically made, and the information (the first area and the second area) is stored in the storage unit together with the areas having the same tendency. Thereby, the tendency of the wafer map can be easily confirmed on the display unit.
[0012]
In the above-described semiconductor inspection apparatus according to the present invention, the display unit can display an abnormal portion based on position information obtained by the inspection mechanism. It is also useful to display the map of the actual abnormal location with reference.
[0013]
The semiconductor inspection device according to the present invention, further comprising: a determination control unit that relates the number or the total number of any of the first area and the second area in the storage unit to an evaluation of a wafer map tendency. The wafer map tendency is automatically determined and displayed.
[0014]
A semiconductor manufacturing apparatus according to the present invention uses any one of the above-described wafer map automatic determination control methods.
A semiconductor device according to the present invention uses any one of the wafer map automatic determination control methods described above.
Further, a semiconductor device according to the present invention uses any one of the semiconductor inspection devices described above.
As described above, an easy-to-handle and highly reliable semiconductor manufacturing apparatus can be provided, which contributes to mass production of a highly reliable semiconductor device.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a flowchart illustrating a wafer map automatic determination control method according to an embodiment of the present invention. FIG. 2 is a plan view showing a wafer map adopting the wafer map automatic determination control method according to the present invention. Such a wafer map automatic determination control method is used during the manufacture of a semiconductor device including a process of repeatedly exposing a predetermined mask pattern so that a plurality of integrated circuit chip regions are formed on a semiconductor wafer separated by scribe line regions. Can be
[0016]
In FIG. 1, as shown in a process S1, position information for specifying an abnormal portion of a semiconductor wafer is acquired according to an inspection mode of a defect inspection device or the like. For example, a predetermined pattern in the same region is compared and inspected between two adjacent chip regions. Thereby, the position information of the abnormal part in the wafer surface is obtained. On the other hand, as shown in processing S2, the surface of the semiconductor wafer is divided into information processing areas by the map processing step. For example, the above areas are made to correspond so that a mesh-shaped map sheet of a predetermined area unit (1 mm square) is placed on the surface of the semiconductor wafer (see FIG. 2). Thereby, the information is superimposed on the information of the abnormal part obtained by the defect inspection apparatus. In one area, a reference value relating to the density or the number of allowable abnormal points is set in advance. The size and reference value of the mesh-like area (section) can be arbitrarily set and changed.
[0017]
Next, an arithmetic processing step is performed as in processing S3. The arithmetic processing step determines whether or not the density or the number of abnormal locations based on the position information in the process S1 exceeds a preset reference value in each of the sections in the process S2. The first discrimination display control, such as color coding, is performed on the area determined not to exceed the reference value (process S5). On the other hand, as shown in the process S4, in the abnormal area information acquiring step, the first abnormal area determined to exceed the reference value is held as data, and further vertically and horizontally adjacent to the first abnormal area by information processing. Data is held for each of the sections as a second abnormal section having an abnormal tendency. For the first abnormal area and the second abnormal area, display control for the second and third discrimination such as color coding is performed (step S5).
[0018]
That is, in the process S5, it is preferable that the area having no abnormality, the first abnormal area, and the second abnormal area adjacent to the first abnormal area are displayed in different colors for each mesh section (see FIG. 2). Further, the plot display of the actual abnormal part may be displayed in a superimposed manner.
[0019]
According to the wafer map automatic determination control method of the above-described embodiment, the map of the semiconductor wafer is divided into predetermined areas by the map processing step, separately from the position information of the abnormal part obtained by the defect inspection device or the like. In the arithmetic processing step, a determination determined according to the density or the number of abnormal portions in each area is automatically made. In addition, the areas within the same tendency are automatically determined by the abnormal area information obtaining step. As a result, there is no variation in determination among operators, and the determination becomes more appropriate. A semiconductor manufacturing apparatus incorporating such a wafer map automatic determination control method is easy to handle, has improved reliability, and contributes to mass production of highly reliable semiconductor devices.
[0020]
FIG. 3 is a block diagram showing a main configuration of a semiconductor inspection apparatus according to one embodiment of the present invention. The semiconductor wafer 10 includes those in the process of manufacturing a semiconductor process, and a predetermined pattern of a chip region is repeatedly arranged with a scribe line (not shown) interposed therebetween. The stage 11 has a semiconductor wafer 10 mounted horizontally and is movable in the X and Y directions. Thereby, the inspection location is moved on the semiconductor wafer 10.
[0021]
An inspection mechanism INS for acquiring position information for specifying an abnormal portion of the semiconductor wafer is provided. The inspection mechanism INS includes a control unit 12, an image data acquisition mechanism 13, an image data processing unit 14, a memory unit 15, an arithmetic processing unit 16, and an output control unit 17. The image data acquisition mechanism 13 acquires an image of the inspection target area on the wafer 10 by, for example, a camera. The image data processed by the image data processing unit 14 is stored in the memory unit 16. The arithmetic processing unit 16 compares image data to be compared and inspected in the image data, detects different data, and acquires position information as defect data. The output control unit 17 controls at least the output of the inspection result regarding the defect data.
[0022]
The arithmetic and control unit 20 divides the surface of the semiconductor wafer 10 into information processing areas, and in each of the areas, the density or the number of abnormal spots based on the position information in the inspection mechanism INS is set to a predetermined reference value. Is determined. A memory 21 is provided for storing information of a first section exceeding a reference value among the above sections, and upper, lower, left and right second sections adjacent to the first section. The information of the first area and the second area is transmitted to the display unit 21 via the output control unit 17 and displayed so as to be recognizable.
[0023]
FIG. 4 is a block diagram showing a main configuration of a semiconductor inspection apparatus according to another embodiment of the present invention. A determination control unit 22 is added as compared with FIG. Other configurations are the same as those in FIG. 3 and are denoted by the same reference numerals. The display unit 21 can also display an abnormal location based on the position information from the inspection mechanism INS. Further, there is provided a determination control unit 22 for relating the number or total number of either the first area or the second area in the memory unit 21 to the evaluation of the tendency of the wafer map. This is convenient when the display unit 21 automatically displays the tendency of the wafer map.
[0024]
As described above, according to the present invention, a map of a semiconductor wafer is provided for each predetermined area by a map processing step, separately from the first information acquisition step in which position information of an abnormal part is obtained from a normal defect inspection. Divided. In the arithmetic processing step, a determination determined according to the density or the number of abnormal portions in each area is automatically made. In addition, areas that are in the same tendency are automatically determined. If such a wafer map automatic determination control method is incorporated in an appropriate semiconductor manufacturing apparatus, it is easy to handle and an improvement in processing efficiency can be expected. As a result, it is possible to provide a wafer map automatic determination control method, a semiconductor inspection apparatus, a semiconductor manufacturing apparatus, and a semiconductor device that automatically detect an appropriate wafer map tendency.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating a wafer map automatic determination control method according to an embodiment.
FIG. 2 is a plan view showing a wafer map according to the present invention.
FIG. 3 is a block diagram illustrating a configuration of a main part of the semiconductor inspection device according to the embodiment;
FIG. 4 is a block diagram of a configuration of a main part of a semiconductor inspection device according to another embodiment.
[Explanation of symbols]
S1 to S5: each processing step, INS: inspection mechanism, 10: semiconductor wafer, 11: stage, 12: control unit, 13: image data acquisition mechanism, 14: image data processing unit, 15, 21: memory unit, 16 ... Arithmetic processing unit, 17 ... output control unit, 20 ... arithmetic control mechanism, 21 ... display unit, 22 ... determination control unit.

Claims (12)

A first information acquisition step of acquiring position information specifying an abnormal part of the semiconductor wafer;
A map processing step of dividing the surface of the semiconductor wafer into information processing areas;
An arithmetic processing step of determining whether the density or the number of abnormal locations based on the position information in each of the sections exceeds a preset reference value,
A first section exceeding the reference value among the sections, a second information acquisition step of storing a second section adjacent to the first section,
A display step of displaying at least the first area and the second area so as to be recognizable;
And a wafer map automatic determination control method. 2. The wafer map automatic determination control method according to claim 1, wherein in the map processing step, the areas are made to correspond so that a mesh-shaped map sheet of a predetermined area unit is put on the surface of the semiconductor wafer. 3. The method according to claim 1, wherein the size of the area is changeable. 4. The method according to claim 1, wherein the reference value is changeable. 5. The method according to any one of claims 1 to 4, wherein the second information acquiring step sets an area existing on the upper, lower, left, and right sides of the first area as the second area. The wafer according to any one of claims 1 to 5, wherein the number or total number of any of the first area and the second area in the second information acquisition step is related to an evaluation of a wafer map tendency. Map automatic judgment control method. An inspection mechanism for acquiring position information for identifying an abnormal part of the semiconductor wafer;
An arithmetic and control unit that divides the surface of the semiconductor wafer into information processing areas and determines whether the density or the number of abnormal locations based on the position information in each of the areas exceeds a preset reference value. When,
A storage section that stores information of a first section exceeding the reference value among the sections, and a second section adjacent to the first section;
A display unit for displaying at least the first area and the second area in a recognizable manner. 8. The semiconductor inspection apparatus according to claim 7, wherein the display unit can also display an abnormal part based on the position information by the inspection mechanism. A determination control unit that relates the number or the total number of any one of the first area and the second area in the storage unit to an evaluation of a wafer map tendency; and automatically determining and displaying the wafer map tendency on the display unit. 9. The semiconductor inspection apparatus according to claim 7, wherein: A semiconductor manufacturing apparatus using the wafer map automatic determination control method according to claim 1. A semiconductor device formed by using the wafer map automatic determination control method according to claim 1. A semiconductor device formed using the semiconductor inspection device according to claim 7.

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