JP2004303081A - Instruction prefetching circuit and microcontroller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an instruction prefetching circuit with which processing capability can be enhanced, using a simplified circuit configuration. <P>SOLUTION: When a conditional branch instruction is detected, an instruction prefetching control part 24, based on its branching frequency, decides whether prefetching the instruction is halted, in accordance with the control flag set on a prefetching control register 25 in advance. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an instruction prefetch circuit and a microcontroller.
In recent years, the operation speed of a microcontroller has been relatively higher than that of peripheral circuits such as a memory, as the operating frequency of a CPU has been increased. Therefore, there is a configuration in which a processing speed of the CPU is improved by mounting an instruction prefetch circuit that reads the instruction from a memory in advance and holds the instruction before executing the instruction by the CPU. There is a demand for improved microcontroller memory access efficiency.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as one of devices having an instruction prefetching function, there is a configuration in which prefetching of an instruction is stopped when an instruction read by a processor such as a CPU is a conditional branch instruction (for example, Patent Documents 1 and 2). 2).
[0003]
That is, in this configuration, when the branch instruction is detected regardless of the type of the conditional branch instruction, the prefetching of the instruction is stopped until the branch destination address of the instruction is determined, so that when a branch occurs, It is prevented that the prefetched instruction is not used and is wasted. As a result, it is possible to minimize memory access for instruction prefetching.
[0004]
[Patent Document 1]
JP-A-5-27972
[Patent Document 2]
JP 2001-312404 A
[0005]
[Problems to be solved by the invention]
However, if the prefetch is always stopped when a conditional branch instruction is detected, as in the above-described related art, there is a problem that the prefetch efficiency is reduced when the branch instruction does not cause a branch. That is, there is a problem in that the processing capability of the CPU is reduced because necessary instructions are not read in advance when a branch does not occur because the condition is satisfied or not satisfied in the conditional branch instruction.
[0006]
As a means for solving this problem, there is a configuration in which both instruction addresses when a conditional branch instruction is detected and when a branch does not occur are calculated and prefetched (for example, see Patent Document 2). In this configuration, it is necessary to pre-read many instructions, and as a result, the processing capacity of the CPU is reduced.
[0007]
Further, as another means, there is a configuration in which information on the frequency of occurrence of a past branch is stored in advance, and when a conditional branch instruction is detected, whether or not to branch is predicted and a branch destination instruction is prefetched. However, the configuration having such a branch prediction function has a disadvantage that the circuit scale is increased because the circuit is complicated.
[0008]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an instruction prefetch circuit and a microcontroller capable of improving processing performance with a simple circuit configuration.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, according to the first and tenth aspects of the present invention, in the instruction prefetching circuit, the prefetch control unit stops prefetching when the branch instruction detected by the instruction decoding unit is an absolute branch instruction. Let it. When the branch instruction detected by the instruction decoding unit is a conditional branch instruction, the prefetch control unit determines whether to stop prefetch based on a control flag set in the prefetch control register. In such a configuration, prefetching can be stopped when a conditional branch instruction having a high branch occurrence frequency is detected, and conversely, prefetching can be continued when a conditional branch instruction having a low branch occurrence frequency is detected. . As a result, it is possible to improve the processing capability while efficiently prefetching instructions by effectively using the bus bandwidth of the external bus.
[0010]
According to the second aspect of the present invention, since the prefetch control register is provided for each type of the conditional branch instruction, more accurate prefetch control is possible.
According to the third aspect of the present invention, it is determined whether or not the address of an instruction to be prefetched is within a predetermined address range, and a control flag set in the prefetch control register based on the judgment result. And an address range comparison unit that can be switched. As a result, the control flag can be appropriately switched at the time of executing the program, so that more accurate read-ahead control can be performed.
[0011]
According to the fourth aspect of the present invention, the address range comparing section is provided with an address range setting register for storing a first address and a second address designating the address range.
[0012]
According to the fifth aspect of the present invention, the address range is set for each instruction routine including a prefetch instruction. As a result, even when the branch occurrence frequency of the conditional branch instruction differs for each instruction routine included in the program, highly accurate prefetch control can be performed.
[0013]
According to the invention described in claim 6, when the data pattern read from the memory is a predetermined specific data pattern, a data pattern detection unit that can switch a control flag set in the prefetch control register is provided. Equipped. As a result, the control flag can be appropriately switched at the time of executing the program, so that more accurate read-ahead control can be performed.
[0014]
According to the seventh aspect of the present invention, the data pattern detection unit includes a data holding register that holds the specific data pattern.
According to the invention described in claim 8, when the instruction read from the memory is a predetermined specific instruction code, the control flag set in the prefetch control register can be switched. As a result, the control flag can be appropriately switched at the time of executing the program, so that more accurate read-ahead control can be performed.
[0015]
According to the ninth aspect of the present invention, the first counter counts up when a pre-specified conditional branch instruction is detected, and the second counter counts up when the pre-specified conditional branch instruction branches. A counter, and an assist circuit for calculating a branch occurrence frequency of the conditional branch instruction based on count values of the first and second counters. Thus, the value of the control flag set in the prefetch control register can be determined.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
[0017]
FIG. 1 is a schematic block diagram illustrating a microcontroller including the instruction prefetch circuit according to the first embodiment.
The microcontroller 11 includes a CPU 12, a command prefetch circuit 13, and an external bus interface (hereinafter, abbreviated as bus I / F) 14, which are formed on the same semiconductor chip 15. A memory 17 is connected to the microcontroller 11 via an external bus 16 connected to a bus I / F 14. The memory 17 stores programs and data executed by the CPU 12.
[0018]
The instruction prefetch circuit 13 includes a prefetch address generation unit 21, a prefetch buffer unit 22, an instruction decoding unit 23, and a prefetch control unit 24. The prefetch control unit 24 includes a prefetch control register 25.
[0019]
The prefetch address generation unit 21 generates an address of an instruction to be executed next by the CPU 12 based on an address output from the CPU 12. Specifically, the addresses loaded at the time of the first instruction fetch after power-on or reset, or the first instruction fetch after a branch is generated by an absolute branch instruction or a conditional branch instruction described later are sequentially counted up and prefetched. Generate the address of the instruction to execute.
[0020]
The address generated by the prefetch address generation unit 21 is output to the external bus 16 via the arithmetic unit 26 and the bus I / F 14. Thus, the instruction prefetching circuit 13 reads out (prefetches) the instruction corresponding to each address from the memory 17.
[0021]
The instruction prefetched from the memory 17 is held in the prefetch buffer unit 22 and decoded by the instruction decoding unit 23. The prefetch buffer unit 22 is configured by, for example, a FIFO (First-In First-Out) memory, sequentially fetches prefetched instructions, and outputs the fetched instructions to the CPU 12 via the arithmetic unit 27. Therefore, the CPU 12 decodes instructions prefetched by the instruction prefetch circuit 13 and sequentially executes the processes.
[0022]
The instruction that is prefetched and held in the prefetch buffer unit 22 is cleared when the CPU 12 executes an instruction that has been branched by an absolute branch instruction or a conditional branch instruction described later.
[0023]
The instruction decoding unit 23 decodes an instruction read ahead from the memory 17 and detects a branch instruction. Specifically, the instruction decoding unit 23 detects an absolute branch instruction and a conditional branch instruction included in the prefetched instruction, and sends the absolute branch instruction detection signal Iab and the conditional branch instruction detection signal Icb to the prefetch control unit 24 as the detection result. Output. In this embodiment, when detecting a conditional branch instruction, the instruction decoding unit 23 outputs a detection result (detection signal) corresponding to each type of the conditional branch instruction to the prefetch control unit 24.
[0024]
FIG. 3 is a block diagram illustrating an example of the instruction decoding unit 23 that detects an absolute branch instruction and one conditional branch instruction.
The instruction decoding unit 23 includes first and second comparators 31 and 32, first and second storage units 33 and 34, and first and second AND circuits 35 and 36. Read data RD from the external bus I / F 14 is input to the first and second comparators 31 and 32. The output signal of the first storage unit 33 is input to the first comparator 31, and the output signal of the second storage unit 34 is input to the second comparator 32.
[0025]
The first and second storage units 33 and 34 are composed of hardwires such as a register rewritable from the CPU 12 or externally, or a mask ROM, and store an absolute branch instruction and a conditional branch instruction, respectively. As shown in FIG. 4, the instruction 37 includes an operation code section (OP code section) 38 and an operand section 39. The first storage unit 33 stores the data of the OP code unit 38 of the absolute branch instruction, and the second storage unit 34 stores the data of the OP code unit 38 of the conditional branch instruction. The first and second storage units 33 and 34 output the stored data of the operation code unit 38, respectively.
[0026]
Accordingly, the first comparator 31 receives the read data RD and the data of the OP code part 38 of the absolute branch instruction, and outputs a signal corresponding to the result of comparing the two. The second comparator 32 receives the read data RD and the data of the OP code part 38 of the conditional branch instruction, and outputs a signal corresponding to the result of comparing the two.
[0027]
The first AND circuit 35 receives the output signal of the first comparator 31 and the instruction fetch signal SF, and outputs an absolute branch instruction detection signal Iab based on both signals. The second AND circuit 36 receives the output signal of the second comparator 32 and the instruction fetch signal SF, and outputs a conditional branch instruction detection signal Icb based on both signals. The instruction fetch signal SF is a signal for determining whether the data (read data RD) input to the external bus I / F 14 is an instruction or data.
[0028]
Therefore, the instruction decoding unit 23 outputs a detection signal Iab of a predetermined level (for example, H level: 1) when the read data RD is an instruction and detects an absolute branch instruction, and outputs a detection signal Iab when detecting a conditional branch instruction. Outputs a detection signal Icb of a predetermined level (for example, H level: 1).
[0029]
The prefetch control unit 24 controls prefetching of the instruction based on the detection result of the instruction decoding unit 23 (determines whether to continue or stop the prefetching). When the data (instruction) held in the prefetch buffer unit 22 is full, the prefetch control unit 24 stops prefetching the instruction based on a full flag FF indicating the state. .
[0030]
More specifically, the prefetch control unit 24 determines whether the instruction decoding unit 23 does not detect a branch instruction (when the detection signals Iab and Icb are at L level), that is, when neither the absolute branch instruction nor the conditional branch instruction is detected. Causes the instruction to look ahead.
[0031]
When the instruction decoding unit 23 detects an absolute branch instruction, the prefetch control unit 24 stops prefetching the instruction. Specifically, the generation of addresses by the prefetch address generation unit 21 is stopped.
[0032]
When a conditional branch instruction is detected by the instruction decoding unit 23, the prefetch control unit 24 determines whether to stop prefetching of an instruction according to a control flag preset in a prefetch control register 25.
[0033]
Here, the prefetch control register 25 will be described. In the present embodiment, the prefetch control register 25 is provided corresponding to each type of conditional branch instruction included in the program in the present embodiment. Therefore, when the conditional branch instruction is detected, the prefetch control unit 24 can individually control the prefetch of the instruction according to the type.
[0034]
For example, when the types of conditional branch instructions executed by the CPU 12 are four types of A to D, the prefetch control unit 24 stores four types of conditional branch instructions A to D, as shown in FIG. Two prefetch control registers 25a to 25d are provided. Therefore, when any one of the conditional branch instructions A to D is detected by the instruction decoding unit 23, the prefetch control unit 24 resets the control flag set in any of the prefetch control registers 25a to 25d corresponding to the condition branch instruction. By referencing, it is determined whether or not to stop the prefetching.
[0035]
The control flag of such a prefetch control register 25 (the prefetch control registers 25a to 25d in FIG. 2) is set at the time of debugging in the program development stage.
This makes it possible to grasp at the time of program debugging which instruction in the program causes the occurrence of a conditional branch instruction to frequently occur, and accordingly optimizes the type of the conditional branch instruction (the conditional branch instructions A to D in FIG. 2) according to the type. This is because a register value (control flag) can be set.
[0036]
Here, the optimal control flag is set by setting the control flag of the prefetch control register 25 corresponding to the conditional branch instruction having a high branch occurrence frequency to a value indicating stop of prefetch, and conversely, setting the control flag to the conditional branch instruction having a low branch occurrence frequency. That is, the control flag of the corresponding prefetch control register 25 is set to a value indicating continuation of prefetch.
[0037]
For example, in FIG. 2, when the conditional branch instruction A is a branch instruction with a low branch occurrence frequency, a control flag of a value “0” indicating continuation of prefetch is set in the prefetch control register 25a. Therefore, when the conditional branch instruction A is detected, the prefetch control unit 24 continues the prefetch.
[0038]
In FIG. 2, when the conditional branch instruction B is a branch instruction having a high branch occurrence frequency, a control flag of a value “1” indicating stop of prefetch is set in the prefetch control register 25b. Therefore, when the conditional branch instruction B is detected, the prefetch control unit 24 stops the prefetch. That is, the generation of the address by the prefetch address generation unit 21 is stopped.
[0039]
FIG. 5 is a block diagram of the prefetch control unit 24 that stops prefetching in response to one conditional branch instruction. FIG. 5 shows a prefetch control unit which stops prefetching when the conditional branch instruction B shown in FIG. 2 is detected.
[0040]
The prefetch control unit 24 includes a prefetch control register 25b, a combination circuit 41, a flip-flop (FF) 42, and an AND circuit 43. Write data from the CPU 12 in FIG. 1 is written in the pre-read control register 25b. The prefetch control register 25b outputs a signal of a level according to the written data. The combinational circuit 41 receives the signal from the prefetch control register 25b, the full flag FF, and the output signal of the FF42, and outputs a signal having a level determined by a combination of these signals and controlling the prefetching of the instruction. I do. The FF 42 receives the signal from the combination circuit 41 and the clock signal CLK. The FF outputs a signal having substantially the same level as the signal output from the combination circuit 41 in response to the clock signal CLK. The signal is output to the combination circuit 41. Therefore, the combination result (the output signal of the FF42) of the data of the prefetch control register 25b and the full flag FF is held by the FF42. The output signal of the FF 42 is input to the AND circuit 43. The AND circuit 43 receives a conditional branch instruction detection signal Icb (a detection signal IB corresponding to the conditional branch instruction B). The AND circuit 43 outputs a prefetch stop signal FS generated based on both signals to the prefetch address generation unit 21 in FIG.
[0041]
Therefore, the prefetch control unit 24 determines that the data held in the prefetch buffer unit 22 is not full, the output of the FF 42 is “1” (the write data from the CPU 12 is “1”), and the conditional branch instruction detection signal IB is “1”. In the case of "1", a prefetch stop is instructed (a prefetch stop signal FS having a level of "1" is output).
[0042]
Next, the operation of the microcontroller 11 equipped with the instruction prefetch circuit 13 as described above will be described. Here, as shown in FIG. 2, the prefetch control unit 24 includes four prefetch control registers 25a to 25d corresponding to four types of conditional branch instructions A to D, respectively, and each register 25a to 25d has “0”. , “1”, “0”, and “1” are set. Note that the value “0” is a control flag indicating that prefetching is to be continued, and the value “1” is a control flag indicating stopping prefetching.
[0043]
The instruction prefetch circuit 13 stops prefetching when the prefetched instruction is an absolute branch instruction. When the prefetched instruction is the conditional branch instruction B or the conditional branch instruction D having a high branch occurrence frequency, the instruction prefetch circuit 13 sets the prefetch control registers 25b and 25d in which the control flag of the value “1” is set, respectively. The prefetching is stopped according to.
[0044]
Therefore, in these cases, it is possible to prevent the instruction prefetched by the instruction prefetching circuit 13 from being wasted without being used. Further, since the bus bandwidth of the external bus 16 is released, it is possible to efficiently perform data access to the memory 17 by the CPU 12 and instruction fetch after branching.
[0045]
When the prefetched instruction is a conditional branch instruction A or a conditional branch instruction C with a low branch occurrence frequency, the instruction prefetch circuit 13 sets the prefetch control registers 25a and 25c each having a control flag of a value “0” set therein. And continues the look-ahead instruction.
[0046]
Therefore, in these cases, an instruction required when a branch does not occur can be stored in the prefetch buffer unit 22 in advance, so that the processing capability of the CPU 12 is not reduced.
[0047]
As described above, the present embodiment has the following advantages.
(1) When a conditional branch instruction is detected, the prefetch control unit 24 determines whether or not to stop prefetching of an instruction in accordance with a control flag preset in a prefetch control register 25 based on the branch occurrence frequency. to decide. Accordingly, when a conditional branch instruction having a high branch occurrence frequency is detected, prefetching can be stopped and the prefetched instruction can be prevented from being wasted. As a result, the processing capability of the CPU 12 can be improved.
[0048]
(2) When a conditional branch instruction having a high branch occurrence frequency is detected, the prefetching is stopped, so that the prefetching of the instruction can be efficiently performed by effectively utilizing the bus bandwidth of the external bus 16.
[0049]
(3) If a conditional branch instruction with a low branch occurrence frequency is detected, prefetching is continued, so that necessary instructions can be stored in the prefetch buffer unit 22 in advance when a branch does not occur. Therefore, the processing performance of the CPU 12 is not reduced.
[0050]
(4) In the present embodiment, it is possible to realize the instruction prefetch circuit 13 that enables highly accurate prefetch control with a very simple configuration in which the prefetch control unit 24 includes the prefetch control register 25. Therefore, a circuit or the like having a branch prediction function is unnecessary, and the circuit scale does not increase.
[0051]
(5) In the present embodiment, since the prefetch control registers 25a to 25d corresponding to the conditional branch instructions A to D included in the program are provided, more precise instruction prefetch control is possible.
[0052]
(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 6 is a block diagram illustrating a microcontroller including the instruction prefetch circuit according to the second embodiment. Note that the present embodiment has a configuration in which an address range comparison unit 51 is newly added to the instruction prefetch circuit 13 of the first embodiment, and other configurations are the same as those in FIG.
[0053]
The address range comparison unit 51 includes an address range setting register 52.
The address range setting register 52 stores a first address and a second address for determining whether or not the address of a prefetched instruction is within an address range designated in advance. In this embodiment, a start address (first address) and an end address (second address) indicating an address range corresponding to each instruction routine of the program are stored.
[0054]
The address range comparison unit 51 compares the address output from the CPU 12 (that is, the address for accessing the memory 17) with the first and second addresses set in the register 52, thereby obtaining a prefetched instruction. Is determined to be within the address range specified in advance.
[0055]
Then, the address range comparison unit 51 outputs a flag switching signal FC for controlling prefetch to the prefetch control unit 24 based on the determination result (whether or not the address is within the range).
[0056]
FIG. 7 is an explanatory diagram showing a specific example of the address range setting register 52.
In the present embodiment, the address range setting register 52 is provided with four types of control flags that enable the control flags of the prefetch control registers 25a to 25d corresponding to the types of conditional branch instructions (conditional branch instructions A to D in the figure) to be individually switched. Including registers.
[0057]
That is, the address range comparison unit 51 includes the address range setting registers 52a to 52d, and performs switching control in accordance with the address ranges set therein.
Here, in each of the address range setting registers 52a to 52d, a start address ADS1, ADS2, ADS3,... Indicating an address range S100, S200, S300,. ADE1, ADE2, ADE3,... Are stored.
[0058]
FIG. 8 is a block diagram of the address range comparison unit 51a corresponding to one address range setting register 52a.
The address range comparator 51a includes a start address register 61, an end address register 62, an internal / external setting register 63, a magnitude comparison circuit 64, and an exclusive OR (EOR) circuit 65. The start address register 61 stores an address indicating the start of the range, and the end address register 62 stores an address indicating the end of the range. The internal / external setting register 63 stores a set value indicating whether the designated area is within the range from the start address to the end address or outside the range. For example, “1” is stored in the inside / outside setting register 63 when the inside is specified, and “0” is stored when outside the range is specified.
[0059]
The magnitude comparison circuit 64 is a comparator for detecting whether or not the input address ADD falls within the range between the start address and the end address, and outputs the detection result. For example, the magnitude comparison circuit 64 outputs a signal of “1” when the address ADD is within the range between the start address and the end address, and outputs a signal of “0” when the address ADD is not within the range. I do.
[0060]
The EOR circuit 65 outputs a flag switching signal FC generated by performing an exclusive OR operation on the output signal of the magnitude comparison circuit 64 and the data of the internal / external setting register 63.
Therefore, the address range comparing unit 51a outputs, for example, the flag switching signal FC of H level (1) when the above conditions are matched, and outputs the flag of L level (0) when at least one condition is not matched. It outputs the switching signal FC.
[0061]
Hereinafter, the operation of the address range setting register 52a will be described as an example.
In the execution of the program by the CPU 12, the address range comparing unit 51 monitors the access address of the CPU 12, and checks which instruction routine is currently in the address range corresponding to the instruction routine.
[0062]
Here, when the access address of the CPU 12 is within the address range S100 indicated by, for example, the start address ADS1 and the end address ADE1, the address range comparison unit 51 generates the flag switching signal FC so as to continue the prefetch. .
[0063]
Next, when the access address of the CPU 12 is an address in the address range S200 indicated by, for example, the start address ADS2 and the end address ADE2, the address range comparison unit 51 generates the flag switching signal FC so as to stop the prefetch.
[0064]
Next, when the access address of the CPU 12 is within the address range S300 indicated by, for example, the start address ADS3 and the end address ADE3, the address range comparison unit 51 generates the flag switching signal FC so as to continue the prefetch.
[0065]
As described above, the address range comparison unit 51 determines which address range the access address of the CPU 12 is in (that is, which instruction routine includes the prefetched instruction) and generates the flag switching signal FC. The flag switching signal FC is input to the combination circuit 41 of the prefetch control unit 24 shown in FIG. Therefore, the prefetch control unit 24 controls the combination of the flag switching signal FC, the full flag FF, and the prefetch control register 25 (25b in FIG. 5), and the signal that controls the prefetch when the conditional branch instruction detection signal IB is “1”. Is output.
[0066]
In other words, the address range comparison unit 51 switches the control of whether or not to continue the instruction prefetch according to the address range within which the access address of the CPU 12 is located. Although the description is omitted here, the same applies to the other address range setting registers 52b to 52d.
[0067]
As described above, in the present embodiment, the control flag set in the prefetch control register 25 (the prefetch control registers 25a to 25d) can be switched according to the address range to which the access address of the CPU 12 belongs when executing the program. With this configuration, appropriate prefetch control can be performed even when the frequency of occurrence of conditional branch instructions (conditional branch instructions A to D) differs in each instruction routine. Therefore, prefetch control with higher accuracy than in the first embodiment can be performed.
[0068]
(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS.
FIG. 9 is a block diagram illustrating a microcontroller including the instruction prefetch circuit according to the third embodiment. Note that the present embodiment has a configuration in which a data pattern detection unit 71 is newly added to the instruction prefetch circuit 13 of the first embodiment instead of the address range comparison unit 51 of the second embodiment. Same as 1.
[0069]
The data pattern detection unit 71 includes a data holding register 72 that holds a specific data pattern read from the memory 17 by the CPU 12.
Then, the data pattern detection unit 71 compares the data pattern accessed by the CPU 12 with the data pattern held in the data holding register 72, and when the respective data match, switches the flag for controlling prefetching. The signal FC1 is output to the prefetch control unit 24. The flag switching signal FC1 is input to the combination circuit 41 of the prefetch control unit 24 shown in FIG. Accordingly, the prefetch control unit 24 controls the combination of the flag switching signal FC1, the full flag FF, and the prefetch control register 25 (25b in FIG. 5), and the signal that controls the prefetch when the conditional branch instruction detection signal IB is “1”. Is output.
[0070]
In the data holding register 72 of the present embodiment, the control flags of the prefetch control registers 25a to 25d corresponding to the types of the conditional branch instructions (the conditional branch instructions A to D in FIG. 2) are individually set in accordance with the data pattern. Four registers that can be switched are provided.
[0071]
FIG. 10 is a block diagram of the data pattern detection unit 71a that detects a conditional branch instruction that matches one data pattern.
The data pattern detection unit 71a includes a plurality of bit determination units 81 and AND circuits 82 and 83. The bit determination unit 81 is a circuit that determines whether a predetermined bit of the data pattern accessed by the CPU 12 in FIG. 9 matches a bit of the specified data. Therefore, the data pattern detection unit 71a includes the number of bit determination units 81 corresponding to the number of bits to be determined.
[0072]
The bit determination unit 81 includes a data pattern register 84, a mask register 85, a bit comparison circuit 86, and an AND circuit 87. The data pattern register 84 and the mask register 85 are 1-bit registers, and the data pattern register 84 forms the data holding register 72 in FIG. The data pattern register 84 stores one bit of the specified data pattern. The bit comparison circuit 86 compares one bit of the data accessed by the CPU 12 with the contents of the data pattern register 84 and outputs the result of the comparison. For example, the bit comparison circuit 86 outputs a signal of “1” when both data match, and outputs a signal of “0” when they do not match.
[0073]
The AND circuit 87 outputs a signal generated by performing an AND operation on the output signal of the bit comparison circuit 86 and the data of the mask register 85. The mask register 85 stores data for masking the comparison result of the data accessed by the CPU 12. Therefore, the AND circuit 87 outputs a signal having substantially the same level as the output signal of the bit comparison circuit 86 when the mask of the mask register 85 is “1”, and outputs the signal at the level of “0” when the mask of the mask register 85 is “0”. Outputs a "1" level signal.
[0074]
Therefore, the bit determination unit 81 determines whether the bit at the corresponding position matches, and masks the determination result based on the contents of the mask register 85.
[0075]
The AND circuit 82 has a plurality of input elements, and the number of inputs corresponds to the number of the bit determination units 81. That is, the AND circuit 82 receives the output signals of the plurality of bit determination units 81 and outputs a signal obtained by performing an OR operation on the signals. Therefore, the AND circuit 82 outputs, for example, an H-level signal when all the comparisons between the data pattern and the specified data in the plurality of bit determination units 81 match, and outputs an L-level signal when at least one does not match. The signal of is output.
[0076]
The output signal of the AND circuit 82 and the data access signal ACC are input to the AND circuit 83, and the AND circuit 83 outputs a flag switching signal FC1a.
Therefore, when the pattern of the data accessed by the CPU 12 in FIG. 9 matches the pattern of the specified data (one bit of the data of the data holding register 72), the data pattern detection unit 71a switches the flag for controlling the prefetch. The signal FC1a is output to the prefetch control unit 24. Similarly to the above, the flag switching signal FC1a is input to the combination circuit 41 of the prefetch control unit 24 shown in FIG. Then, the prefetch control unit 24 controls the combination of the flag switching signal FC1a, the full flag FF, the prefetch control register 25 (25b in FIG. 5), and the prefetch control signal when the conditional branch instruction detection signal IB is “1”. Is output.
[0077]
In the instruction look-ahead circuit 13 including such a data pattern detection unit 71, the control flag set in the look-ahead control register 25 (the look-ahead control registers 25a to 25d) is changed according to the data pattern accessed by the CPU 12 at the time of executing the program. be able to. Therefore, it is possible to perform prefetch control with higher accuracy than in the first embodiment.
[0078]
In the present embodiment, the register setting is switched when a specific data pattern is detected. However, the register setting is switched when a specific data pattern is continuous or a plurality of types of unique data patterns are continuous. It may be.
[0079]
That is, in FIG. 10, a flag register 88 and an AND circuit 89 are further provided. The flag register 88 holds the output signal of the AND circuit 83 and outputs a signal having substantially the same level as the held signal. The AND circuit 89 receives the output signal of the flag register 88 and the output signal of the AND circuit 83, and outputs a flag switching signal FC1b. When both the input signals of the AND circuit 89 indicate "match", that is, when the pattern of the data continuously accessed by the CPU 12 in FIG. 9 matches the pattern of the specified data, a flag for controlling prefetching is set. The switching signal FC1b is output to the prefetch control unit 24. Then, similarly to the above, the prefetch control unit 24 determines whether the combination of the flag switching signal FC1b, the full flag FF, the prefetch control register 25 (25b in FIG. 5) and the conditional branch instruction detection signal IB are “1”. Outputs a signal for controlling prefetching.
[0080]
Further, the data pattern detection unit 71b is configured as shown in FIG. The data pattern detection unit 71b includes a plurality (four in this example) of coincidence detection circuits 91a to 91d and a state machine 92. Each of the coincidence detecting circuits 91a to 91d has the same configuration, and includes a bit judging unit 81 and an AND circuit 82, as shown in one coincidence detecting circuit 91d, similarly to the data pattern detecting unit 71a of FIG. . The designated data (designated data DA to DD: shown at the lower left in the figure) is stored in the data pattern register 84 of each of the coincidence detection circuits 91a to 91d, that is, the data holding register 72 of each of the coincidence detection circuits 91a to 91d. You. Therefore, each of the coincidence detecting circuits 91a to 91d detects whether or not the data pattern accessed by the CPU 12 in FIG. 9 matches the designated data DA to DD, and outputs a signal.
[0081]
The state machine 92 outputs to the prefetch control unit 24 a flag switching signal FC2 for controlling prefetching when data of a plurality of types of unique patterns are continuous based on the output signals of the match detection circuits 91a to 91d. More specifically, every time the CPU 12 accesses data, the state machine 92 transitions to the state shown in FIG. 12 based on the output signals of the respective match detection circuits 91a to 91d, and asserts the flag switching signal FC2.
[0082]
First, the state machine 92 is in an idle state (IDLE) 101 after reset. At this time, the state machine 92 transitions to the first state 102 when the access data of the CPU 12 and the specified data DA match in the first match detection circuit 91a. Next, the state machine 92 makes a transition to the second state 103 when the access data of the CPU 12 and the designated data DB match in the second match detection circuit 91b, and makes a transition to the idle state 101 when they do not match.
[0083]
Similarly, the state machine 92 makes a transition to the third state 104 when the access data of the CPU 12 and the designated data DC match in the third match detection circuit 91c, and makes a transition to the idle state 101 when they do not match. Furthermore, the state machine 92 makes a transition to the fifth state 105 when the access data of the CPU 12 and the specified data DD match in the fourth match detection circuit 91d, and makes a transition to the idle state 101 when they do not match. Then, in the fifth state 105, the state machine 92 asserts the flag switching signal FC2 and makes a transition to the idle state 101.
[0084]
Therefore, the data pattern detection unit 71b determines that the four data successively accessed by the CPU 12 match the designated data DA to DD of the match detection circuits 91a to 91d, respectively, and that the order of the four data is When the state transition order matches, the flag switching signal FC2 is asserted.
[0085]
The flag switching signal FC2 is input to the combinational circuit 41 of the prefetch control unit 24 shown in FIG. Therefore, the prefetch control unit 24 controls the combination of the flag switching signal FC2, the full flag FF, and the prefetch control register 25 (25b in FIG. 5), and the signal that controls the prefetch when the conditional branch instruction detection signal IB is “1”. Is output.
[0086]
(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG.
In this embodiment, at the time of program debugging, the branch occurrence frequency of the conditional branch instruction is calculated, and the control flag of the prefetch control register 25 (prefetch control registers 25a to 25d) in each of the above embodiments is set. 5 is a diagram illustrating an assist circuit.
[0087]
As shown in FIG. 13, the assist circuit 110 includes a conditional branch instruction storage register 111, a comparator 112, a first counter 113, a second counter 114, and a control circuit 115. The assist circuit 110 is formed on a semiconductor chip 15 constituting the microcontroller 11, and is specifically connected to a data bus through which an instruction read from the memory 17 is transferred to the CPU 12 via the bus I / F 14. It is formed.
[0088]
Prior to program debugging, the conditional branch instruction storage register 111 stores in advance any of the conditional branch instructions included in the program (instructions for which the occurrence frequency of the branch is to be grasped).
[0089]
The comparator 112 compares the conditional branch instruction read by the CPU 12 at the time of debugging and the conditional branch instruction stored in advance in the register 111, and outputs a match signal S1 when the two instructions match each other. It outputs to the counter 113 and the control circuit 115. The first counter 113 counts up the count value N1 in response to the coincidence signal S1 from the comparator 112.
[0090]
The control circuit 115 branches to the second counter 114 in response to the branch occurrence signal BEN output from the CPU 12 when the corresponding conditional branch instruction actually causes a branch when the instructions match each other. An occurrence detection signal S2 is output. The second counter 114 counts up the count value N2 in response to the branch occurrence detection signal S2 from the control circuit 115.
[0091]
The assist circuit 110 configured as described above operates the program once, calculates the ratio of the count value N2 to the count value N1, and calculates the branch occurrence frequency of the conditional branch instruction stored in the register 111. Can be.
[0092]
By performing such an operation on all the conditional branch instructions included in the program, the branch occurrence frequency can be calculated for each conditional branch instruction.
[0093]
Therefore, by performing register setting based on the branch occurrence frequency obtained by using such an assist circuit 110, setting of an optimal register value according to each conditional branch instruction (conditional branch instructions A to D in FIG. 2). It can be performed.
[0094]
As described above, the present embodiment has the following advantages.
Each of the above embodiments may be implemented in the following manner.
The instruction prefetch circuit 13 of the first embodiment may be configured to include both the address range comparison unit 51 of the second embodiment and the data pattern detection unit 71 of the third embodiment. In this case, the combinational circuit 41 of the prefetch control unit 24 shown in FIG. 5 receives the signal from the prefetch control register 25b, the full flag FF, the flag switching signals FC and FC1, and the output signal of the FF42, and inputs these signals. And outputs a signal for controlling prefetching of an instruction having a level determined by the combination of. When the output signal of the combinational circuit 41 is “1” and the conditional branch instruction detection signal IB is “1”, the prefetch control unit 24 instructs prefetch stop (the prefetch stop signal FS having the level “1” is output). Output).
[0095]
In each of the embodiments, the instruction prefetch control is performed for each type of conditional branch instruction included in the program. However, the prefetch control is not always necessary, and is performed only for a specific conditional branch instruction among the conditional branch instructions in the program. It may be.
[0096]
In each embodiment, the control flag of the prefetch control register 25 (the prefetch control registers 25a to 25d) may be switched when the CPU 12 reads a specific instruction code. However, in this case, it is necessary to set a specific instruction code in the program in advance.
[0097]
In the third embodiment, a specific data pattern may be detected by a control signal from the CPU 12, for example, instead of including the data holding register 72.
[0098]
The features of each of the above embodiments are summarized as follows.
(Supplementary Note 1) In an instruction prefetching circuit that prefetches an instruction from a memory,
An instruction decoding unit for decoding a prefetched instruction and detecting a branch instruction;
A prefetch control unit that stops prefetching when the branch instruction detected by the instruction decoding unit is an absolute branch instruction,
The look-ahead control unit includes a look-ahead control register in which a control flag for determining whether to stop look-ahead when a branch instruction detected by the instruction decoding unit is a conditional branch instruction is set. An instruction look-ahead circuit characterized in that:
(Supplementary note 2) The instruction prefetching circuit according to supplementary note 1, wherein the prefetch control register is provided for each type of the conditional branch instruction.
(Supplementary note 3) The instruction prefetch circuit according to supplementary note 1 or 2, wherein the control flag is set based on a branch occurrence frequency of the conditional branch instruction.
(Supplementary Note 4) An address range in which it is determined whether or not the address of the instruction to be prefetched is within a predetermined address range, and based on the judgment result, the control flag set in the prefetch control register can be switched. 4. The instruction prefetching circuit according to claim 1, further comprising a comparing unit.
(Supplementary note 5) The address range comparing unit according to Supplementary note 4, wherein the address range comparison unit includes an address range setting register that stores a first address and a second address that specify the address range. Instruction look-ahead circuit.
(Supplementary note 6) The instruction prefetch circuit according to supplementary note 5, wherein the address range setting register is provided for each type of the conditional branch instruction.
(Supplementary note 7) The instruction prefetching circuit according to any one of Supplementary notes 4 to 6, wherein the address range is set for each instruction routine including an instruction to be prefetched.
(Supplementary Note 8) A data pattern detection unit that can switch a control flag set in the prefetch control register when a data pattern read from the memory is a predetermined specific data pattern. 8. The instruction look-ahead circuit according to claim 1, wherein
(Supplementary note 9) The instruction prefetch circuit according to supplementary note 8, wherein the data pattern detection unit includes a data holding register that holds the specific data pattern.
(Supplementary note 10) The instruction prefetch circuit according to supplementary note 9, wherein the data holding register is provided for each type of the conditional branch instruction.
(Supplementary note 11) Any of the supplementary notes 1 to 10, wherein a control flag set in the look-ahead control register can be switched when an instruction read from the memory is a predetermined specific instruction code. An instruction prefetch circuit according to claim 1.
(Supplementary Note 12) A first counter that counts up when a pre-designated conditional branch instruction is detected,
A second counter that counts up when the prespecified conditional branch instruction branches.
12. The instruction prefetch circuit according to claim 1, further comprising an assist circuit for calculating a branch occurrence frequency of the conditional branch instruction based on the count values of the first and second counters.
(Supplementary Note 13) A microcontroller including the instruction prefetch circuit according to any one of Supplementary Notes 1 to 12.
[0099]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide an instruction prefetch circuit and a microcontroller capable of improving the processing capability with a simple circuit configuration.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an instruction prefetch circuit according to a first embodiment.
FIG. 2 is an explanatory diagram showing a prefetch control register.
FIG. 3 is a block diagram illustrating an instruction decoding unit.
FIG. 4 is an explanatory diagram showing the structure of an instruction.
FIG. 5 is a block diagram illustrating a prefetch control unit.
FIG. 6 is a block diagram illustrating an instruction prefetch circuit according to a second embodiment.
FIG. 7 is an explanatory diagram showing an address range setting register.
FIG. 8 is a block diagram illustrating an address range comparison unit.
FIG. 9 is a block diagram illustrating an instruction prefetch circuit according to a third embodiment.
FIG. 10 is a block diagram illustrating a data pattern detection unit.
FIG. 11 is a block diagram illustrating another data pattern detection unit.
FIG. 12 is a state transition diagram of the state machine.
FIG. 13 is a block diagram illustrating a fourth embodiment.
[Explanation of symbols]
Iab Absolute branch instruction detection signal
Icb Conditional branch instruction detection signal
A to D conditional branch instructions
ADD address
ADS1, ADS2, ADS3,... First address as first address
ADE1, ADE2, ADE3,... End address as the second address
S100, S200, S300, ... Address range
N1, N2 count value
11 Microcontroller
13 Instruction look-ahead circuit
17 Memory
23 Instruction decoding unit
24 Read-ahead control unit
25, 25a to 25d Prefetch control register
37 instructions
51, 51a Address range comparison unit
52, 52a to 52d Address range setting register
71, 71a, 71b Data pattern detector
72 Data holding register
110 Assist circuit
113 First counter
114 Second counter

Claims (10)

In an instruction prefetching circuit that prefetches an instruction from a memory,
An instruction decoding unit for decoding a prefetched instruction and detecting a branch instruction;
A prefetch control unit that stops prefetching when the branch instruction detected by the instruction decoding unit is an absolute branch instruction,
The look-ahead control unit includes a look-ahead control register in which a control flag for determining whether to stop look-ahead when a branch instruction detected by the instruction decoding unit is a conditional branch instruction is set. An instruction look-ahead circuit characterized in that: 2. The instruction prefetch circuit according to claim 1, wherein said prefetch control register is provided for each type of said conditional branch instruction. An address range comparison unit that determines whether an address of an instruction to be prefetched is within a predetermined address range and that can switch a control flag set in the prefetch control register based on a result of the determination; 3. The instruction look-ahead circuit according to claim 1, wherein: 4. The instruction look-ahead circuit according to claim 3, wherein the address range comparison unit includes an address range setting register for storing a first address and a second address designating the address range. . 5. The instruction prefetch circuit according to claim 3, wherein the address range is set for each instruction routine including a prefetch instruction. 2. A data pattern detecting unit, which is capable of switching a control flag set in the prefetch control register when a data pattern read from the memory is a predetermined specific data pattern. An instruction prefetch circuit according to any one of claims 1 to 5. 7. The instruction prefetch circuit according to claim 6, wherein the data pattern detection unit includes a data holding register for holding the specific data pattern. The control flag set in the prefetch control register can be switched when an instruction read from the memory is a predetermined specific instruction code. Instruction look-ahead circuit. A first counter that counts up when detecting a pre-specified conditional branch instruction;
A second counter that counts up when the prespecified conditional branch instruction branches.
9. The instruction prefetch according to claim 1, further comprising an assist circuit for calculating a branch occurrence frequency of the conditional branch instruction based on count values of the first and second counters. circuit. A microcontroller comprising the instruction prefetch circuit according to any one of claims 1 to 9.

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