JP2004289139A - Chip type solid electrolytic capacitor - Google Patents
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- JP2004289139A JP2004289139A JP2004057406A JP2004057406A JP2004289139A JP 2004289139 A JP2004289139 A JP 2004289139A JP 2004057406 A JP2004057406 A JP 2004057406A JP 2004057406 A JP2004057406 A JP 2004057406A JP 2004289139 A JP2004289139 A JP 2004289139A
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本発明は、等価直列抵抗（ＥＳＲ）が低く、漏れ電流（ＬＣ値）の初期不良率が低い、特性の良好なチップ状固体電解コンデンサに関する。 The present invention relates to a chip-type solid electrolytic capacitor having a low equivalent series resistance (ESR) and a low initial failure rate of a leakage current (LC value) and excellent characteristics.
従来のチップ状固体電解コンデンサとしては、その構造を斜視図として図３に示すように、弁作用金属または導電性の酸化物からなる焼結体の表面に誘電体酸化皮膜層、半導体層及び導電体層を順次形成した１個の固体電解コンデンサ素子（２）の導電体層の一部と前記焼結体に接続された陽極リード（４ａ）（陽極部）を、各々外部端子となる平板状金属製リードフレーム（１）の一部である一対の対向して配置された先端部（１ａ及び１ｂ）に載置し、それぞれ電気的・機械的に接続した後、リードフレームの外部端子部のみを残して外装樹脂で封口して外装部（５）を形成した後、外装部外のリードフレームを所定部で切断後曲げ加工したものが知られている。 As a conventional chip-shaped solid electrolytic capacitor, as shown in FIG. 3 as a perspective view of the structure, a dielectric oxide film layer, a semiconductor layer and a conductive layer are formed on the surface of a sintered body made of a valve metal or a conductive oxide. A part of the conductor layer of one solid electrolytic capacitor element (2) in which the body layers are sequentially formed and the anode lead (4a) (anode part) connected to the sintered body are formed in a flat plate shape to be an external terminal. After being mounted on a pair of opposed end portions (1a and 1b) which are a part of the metal lead frame (1) and electrically and mechanically connected to each other, only the external terminal portion of the lead frame is provided. After forming an exterior part (5) by sealing with an exterior resin while leaving a lead frame, a lead frame outside the exterior part is cut at a predetermined part and then bent.
一方、近年の電子機器の高周波化に対応して、固体電解コンデンサにおいても高周波性能の良好なものが望まれていた。本発明者等は、既に特開平５−２３４８２９号公報（特許文献１）において、陽極部を有し、弁作用金属よりなる陽極基体の表面に誘電体酸化皮膜層、その上に半導体層、さらにその上に導電体層を順次積層して陰極部を形成した複数の固体電解コンデンサ素子の陰極部の一部が、一対の対向して配置された先端部を有するリードフレームの一方の先端部に並列に隙間なく載置され、また陽極部が他方の先端部に載置されて各々電気的・機械的に接合された後、前記リードフレームの先端部の一部を残して樹脂封口し、樹脂封口外の所定部でリードフレームを切断折り曲げ加工された、良好な高周波性能値を示すチップ状固体電解コンデンサを提案している。 On the other hand, in response to the recent increase in the frequency of electronic devices, a solid electrolytic capacitor having good high-frequency performance has been desired. The present inventors have already disclosed in Japanese Patent Application Laid-Open No. Hei 5-234829 (Patent Document 1) a dielectric oxide film layer on a surface of an anode substrate having an anode portion and made of a valve action metal, a semiconductor layer thereon, A portion of the cathode portion of the plurality of solid electrolytic capacitor elements in which a cathode portion is formed by sequentially laminating conductive layers thereon is provided at one end portion of a lead frame having a pair of opposed end portions. After being placed in parallel with no gap, and the anode part being placed on the other end part and being electrically and mechanically joined together, the resin is sealed while leaving a part of the lead frame end part. A chip-shaped solid electrolytic capacitor having a good high-frequency performance value, in which a lead frame is cut and bent at a predetermined portion outside a seal, has been proposed.
他方、チップ状固体電解コンデンサは、その他電子部品と共に基板に組み込まれた後、電子機器に搭載されて複数年使用されるが、基板に組み込まれた段階でのチップ状固体電解コンデンサの初期故障率はできるだけ低いことが望まれている。 On the other hand, chip-type solid electrolytic capacitors are mounted on electronic devices together with other electronic components, then mounted on electronic devices and used for several years. Is desired to be as low as possible.
前記した高周波性能が良好なチップ状固体電解コンデンサを多数作製した場合、基板への半田実装時に初期故障率（特にＬＣ値）が不良なものが出現することがあった。 When a large number of the chip-shaped solid electrolytic capacitors having good high-frequency performance described above are manufactured, there may be a case where the initial failure rate (especially, the LC value) is poor at the time of solder mounting on the substrate.
本発明者等は、前記課題を解決するために鋭意検討した結果、チップ体積に対する陽極部を除いた焼結体１個の体積比を特定の範囲とした焼結体を使用してチップ状固体電解コンデンサを作製すると、初期故障率が低くしかもＥＳＲ値が小さなチップ状固体電解コンデンサを作製できることを見出し本発明を完成するに至った。 The present inventors have conducted intensive studies in order to solve the above-mentioned problems, and as a result, have found that a chip-shaped solid body using a sintered body having a specific volume ratio of one sintered body excluding the anode part to the chip volume is used. The present inventors have found that when an electrolytic capacitor is manufactured, a chip-shaped solid electrolytic capacitor having a low initial failure rate and a small ESR value can be manufactured, and the present invention has been completed.
すなわち、本発明は、以下のチップ状固体電解コンデンサ及びそのチップ状固体電解コンデンサを使用した電子機器に関する。
１． 弁作用金属もしくは導電性酸化物の焼結体よりなる陽極基体または前記焼結体と金属線の接続物よりなる陽極基体の一端の陽極部を除く表面に、誘電体酸化皮膜層、半導体層及び導電体層を順次積層して陰極部を形成した固体電解コンデンサ素子を、一対の対向して配置されたリードフレームの先端部に、複数個水平に並列して隙間なく、前記陽極部と陰極部とをリードフレームに接触するように載置し接合した後、リードフレームの外部端子部を残して樹脂封口してなるチップ状固体電解コンデンサにおいて、チップ体積に対する陽極部を除いた焼結体１個の体積比が、0.042〜0.110であることを特徴とするチップ状固体電解コンデンサ。
２． 陽極部が陽極基体の末端からなる前記１記載のチップ状固体電解コンデンサ。
３． 陽極部が焼結体に接続された金属線からなる前記１記載のチップ状固体電解コンデンサ。
４． 金属線が、タンタル、ニオブ、アルミニウム、チタン、これら金属を主成分とする合金及びこれら金属または前記合金の一部を酸化及び／または窒化させたものから選択される前記３記載のチップ状固体電解コンデンサ。
５． 弁作用金属もしくは導電性酸化物が、タンタル、アルミニウム、ニオブ、チタン、これら弁作用金属を主成分とする合金または酸化ニオブであるか、または前記弁作用金属、合金及び導電性酸化物から選択される２種以上の混合物である前記１記載のチップ状固体電解コンデンサ。
６． 前記弁作用金属、合金及び導電性化合物が、それらの一部が炭化、燐化、ホウ素化、窒化及び硫化から選ばれる少なくとも１種の処理がされたものである前記４記載のチップ状固体電解コンデンサ。
７． 前記焼結体が、その表面が化学的及び／または電気的にエッチング処理されたものである前記１記載のチップ状固体電解コンデンサ。
８． 陽極基体の陽極部と陽極部を除く残部との境界部が絶縁性樹脂により絶縁されている前記１記載のチップ状固体電解コンデンサ。
９． 前記誘電体酸化皮膜層が、Ｔａ2Ｏ5、Ａｌ2Ｏ3、Ｚｒ2Ｏ3、及びＮｂ2Ｏ5から選ばれる少なくとも１つを主成分とするものである前記１記載のチップ状固体電解コンデンサ。
１０． 半導体層が、有機半導体層及び無機半導体層から選ばれる少なくとも１種である前記１記載のチップ状固体電解コンデンサ。
１１． 有機半導体が、ベンゾピロリン４量体とクロラニルからなる有機半導体、テトラチオテトラセンを主成分とする有機半導体、テトラシアノキノジメタンを主成分とする有機半導体、及び下記一般式（１）または（２）
で示される繰り返し単位を含む高分子にドーパントをドープした導電性高分子を主成分とした有機半導体から選択される少なくとも１種である前記１０記載のチップ状固体電解コンデンサ。
１２． 一般式（１）で示される繰り返し単位を含む導電性高分子が、下記一般式（３）
で示される構造単位を繰り返し単位として含む導電性高分子である前記１１記載のチップ状固体電解コンデンサ。
１３． 導電性高分子が、ポリアニリン、ポリオキシフェニレン、ポリフェニレンサルファイド、ポリチオフェン、ポリフラン、ポリピロール、ポリメチルピロール、及びこれらの置換誘導体から選択される前記１１記載のチップ状固体電解コンデンサ。
１４． 導電性高分子が、ポリ（３，４−エチレンジオキシチオフェン）である前記１３記載のチップ状固体電解コンデンサ。
１５． 無機半導体が、二酸化モリブデン、二酸化タングステン、二酸化鉛、及び二酸化マンガンから選ばれる少なくとも１種の化合物である前記１０記載のチップ状固体電解コンデンサ。
１６． 半導体の電導度が１０-2〜１０3Ｓ／ｃｍの範囲である前記１０記載のチップ状固体電解コンデンサ。
１７． 前記１乃至１６のいずれかに記載のチップ状固体電解コンデンサを使用した電子回路。
１８． 前記１乃至１６のいずれかに記載のチップ状固体電解コンデンサを使用した電子機器。
That is, the present invention relates to the following chip-shaped solid electrolytic capacitors and electronic devices using the chip-shaped solid electrolytic capacitors.
1. A surface excluding an anode portion at one end of an anode substrate made of a sintered body of a valve metal or a conductive oxide or an anode substrate made of a connection of the sintered body and a metal wire, a dielectric oxide film layer, a semiconductor layer, A solid electrolytic capacitor element having a cathode portion formed by sequentially laminating conductor layers, a plurality of the anode portions and the cathode portions are horizontally arranged in parallel at the tip portions of a pair of opposedly disposed lead frames without gaps. Is placed in contact with the lead frame and bonded, and then a sintered body excluding the anode part with respect to the chip volume in a chip-shaped solid electrolytic capacitor which is sealed with a resin except for the external terminals of the lead frame. Wherein the volume ratio of the solid electrolytic capacitor is 0.042 to 0.110.
2. 2. The chip-shaped solid electrolytic capacitor according to the above item 1, wherein the anode portion comprises an end of the anode substrate.
3. 2. The chip-shaped solid electrolytic capacitor as described in 1 above, wherein the anode portion is made of a metal wire connected to the sintered body.
4. 4. The chip-shaped solid electrolytic device according to the
5. The valve metal or conductive oxide is tantalum, aluminum, niobium, titanium, an alloy or niobium oxide containing these valve metal as a main component, or selected from the valve metal, alloy and conductive oxide. 2. The chip-shaped solid electrolytic capacitor according to the above item 1, which is a mixture of two or more of the following.
6. The chip-shaped solid electrolyte according to the above item 4, wherein the valve action metal, alloy and conductive compound have been subjected to at least one kind of treatment selected from carbonization, phosphidation, boration, nitridation and sulfurization. Capacitors.
7. 2. The chip-shaped solid electrolytic capacitor according to the above item 1, wherein the surface of the sintered body is chemically and / or electrically etched.
8. 2. The solid electrolytic capacitor according to claim 1, wherein the boundary between the anode portion of the anode substrate and the remainder excluding the anode portion is insulated by an insulating resin.
9. 2. The chip-shaped solid electrolytic device according to the above item 1, wherein the dielectric oxide film layer contains at least one selected from Ta 2 O 5 , Al 2 O 3 , Zr 2 O 3 , and Nb 2 O 5 as a main component. Capacitors.
10. 2. The chip-shaped solid electrolytic capacitor according to the above item 1, wherein the semiconductor layer is at least one selected from an organic semiconductor layer and an inorganic semiconductor layer.
11. The organic semiconductor is an organic semiconductor composed of benzopyrroline tetramer and chloranil, an organic semiconductor composed mainly of tetrathiotetracene, an organic semiconductor composed mainly of tetracyanoquinodimethane, and the following general formula (1) or (2) )
11. The chip-shaped solid electrolytic capacitor according to the above item 10, wherein the chip-shaped solid electrolytic capacitor is at least one selected from organic semiconductors containing a conductive polymer obtained by doping a polymer containing a repeating unit with a dopant as a main component.
12. The conductive polymer containing the repeating unit represented by the general formula (1) is represented by the following general formula (3)
12. The chip-shaped solid electrolytic capacitor according to the above item 11, which is a conductive polymer containing a structural unit represented by the following as a repeating unit.
13. 12. The chip-shaped solid electrolytic capacitor according to the above 11, wherein the conductive polymer is selected from polyaniline, polyoxyphenylene, polyphenylene sulfide, polythiophene, polyfuran, polypyrrole, polymethylpyrrole, and substituted derivatives thereof.
14． 14. The chip-shaped solid electrolytic capacitor according to the above 13, wherein the conductive polymer is poly (3,4-ethylenedioxythiophene).
15. The chip-shaped solid electrolytic capacitor according to the above item 10, wherein the inorganic semiconductor is at least one compound selected from molybdenum dioxide, tungsten dioxide, lead dioxide, and manganese dioxide.
16. The chip-shaped solid electrolytic capacitor according to the above item 10, wherein the conductivity of the semiconductor is in the range of 10 -2 to 10 3 S / cm.
17. An electronic circuit using the chip-shaped solid electrolytic capacitor according to any one of the above 1 to 16.
18. Electronic equipment using the chip-shaped solid electrolytic capacitor according to any one of 1 to 16.
本発明のチップ状固体電解コンデンサの１形態を図面に基づいて説明する。
図１は本発明のチップ状固体電解コンデンサの１例の斜視図である。本例では、陽極部リード（４ａ）が接続され、弁作用金属または導電性酸化物よりなる陽極基体（４）の表面に誘電体酸化皮膜層、その上に半導体層、さらにその上に導電体層を順次積層して陰極部（３）が形成された３個の固体電解コンデンサ素子（２）の陰極部の一部が、一対の対向して配置されたリードフレーム（１）の一方の先端部（１ａ）に並列に隙間なく載置され、また、陽極部リード（４ａ）が前記他方の先端部（１ｂ）に載置されて、各々電気的・機械的に接合された後、前記リードフレーム（１）の外部端子部を残して樹脂封口し、樹脂封口外の所定部（図示せず）でリードフレームを切断折り曲げ加工した構造を有している。
One embodiment of the chip-shaped solid electrolytic capacitor of the present invention will be described with reference to the drawings.
FIG. 1 is a perspective view of one example of a chip-shaped solid electrolytic capacitor of the present invention. In this example, an anode lead (4a) is connected, a dielectric oxide film layer is formed on the surface of an anode substrate (4) made of a valve metal or a conductive oxide, a semiconductor layer is formed thereon, and a conductor is formed thereon. The cathode portions of the three solid electrolytic capacitor elements (2) in which the cathode portions (3) are formed by sequentially laminating the layers are partially connected to one end of a pair of opposingly arranged lead frames (1). After the anode lead (4a) is placed on the other end (1b) and electrically and mechanically joined to each other, the lead is placed on the lead (4a) without gaps. The frame (1) has a structure in which the resin is sealed except for the external terminal portions, and the lead frame is cut and bent at a predetermined portion (not shown) outside the resin seal.
図２は本発明のチップ状固体電解コンデンサの他の例の斜視図である。本例では、固体電解コンデンサ素子の端部の陽極部（４）が残るように、弁作用金属または導電性酸化物よりなる陽極基体の表面に誘電体酸化皮膜層、半導体層、導電体層を順次積層して陰極部（３）を形成した３個の固体電解コンデンサ素子（２）の陰極部（３）を、一対の対向して配置されたリードフレーム（１）の一方の先端部（１ａ）に並列に隙間なく載置し、陽極部（４）を他方の先端部（１ｂ）に載置して、各々を電気的・機械的に接合した後、リードフレーム（１）の外部端子部を残して樹脂封口して、図１の例と同様に樹脂封口外の所定部でリードフレームを切断折り曲げ加工した構造を有している。 FIG. 2 is a perspective view of another example of the chip-shaped solid electrolytic capacitor of the present invention. In this example, a dielectric oxide film layer, a semiconductor layer, and a conductor layer are formed on the surface of an anode substrate made of a valve metal or a conductive oxide so that the anode part (4) at the end of the solid electrolytic capacitor element remains. The cathode portions (3) of the three solid electrolytic capacitor elements (2), which are successively laminated to form the cathode portion (3), are connected to one end portion (1a) of a pair of lead frames (1) opposed to each other. ) Are placed in parallel with no gap, the anode part (4) is placed on the other tip part (1b), and each is electrically and mechanically joined, and then the external terminal part of the lead frame (1) is mounted. 1 and the lead frame is cut and bent at a predetermined portion outside the resin seal as in the example of FIG.
本発明に使用される弁作用金属または導電性酸化物としては、タンタル、アルミニウム、ニオブ、チタン、これら弁作用金属を主成分（５０質量％以上の成分）とする合金または酸化ニオブであるか、または前記弁作用金属、合金及び導電性酸化物から選択される２種以上の混合物が挙げられる。弁作用金属または前記合金または導電性化合物等の一部を、炭化、燐化、ホウ素化、窒化、硫化から選ばれた少なくとも１種の処理を行ってから使用しても良い。 The valve metal or conductive oxide used in the present invention may be tantalum, aluminum, niobium, titanium, an alloy or niobium oxide containing these valve metal as a main component (50% by mass or more), Alternatively, a mixture of two or more kinds selected from the valve metal, alloy, and conductive oxide may be used. The valve metal or a part of the alloy or the conductive compound may be used after at least one treatment selected from carbonization, phosphidation, boration, nitridation, and sulfurization.
本発明で使用する陽極基体は、前記弁作用金属または導電性酸化物の粉末を成形した後焼結して焼結体としたものであるが、成形圧力と焼結条件（温度・時間）を適宜選択することにより焼結体の表面積を変化させることができる。焼結後に焼結体の表面積をさらに増加させるために、焼結体表面を化学的及び／または電気的にエッチング処理を行っていても良い。 The anode substrate used in the present invention is obtained by molding the powder of the valve metal or the conductive oxide and then sintering it to obtain a sintered body. The molding pressure and the sintering conditions (temperature and time) are varied. The surface area of the sintered body can be changed by appropriately selecting it. In order to further increase the surface area of the sintered body after sintering, the surface of the sintered body may be chemically and / or electrically etched.
本発明では、陽極基体（４）の一部を陽極部として使用する。図２に示したように陽極基体の末端を陽極部として設けておいても良いし、または図１で示したように、陽極基体の一部に金属線（４ａ）を接続して陽極部としておいても良い。金属線の接続は、焼結体作製後に行っても良いし、焼結体作製前の成形時に金属線の一部を埋設させた後に焼結して接続を取ることもできる。金属線の種類として、タンタル、ニオブ、アルミニウム、チタン、これら金属を主成分とする合金及びこれら金属または前記合金の一部を酸化及び／または窒化させたものが挙げられる。 In the present invention, a part of the anode substrate (4) is used as an anode part. The end of the anode base may be provided as an anode part as shown in FIG. 2, or a metal wire (4a) may be connected to a part of the anode base as an anode part as shown in FIG. You can leave it. The connection of the metal wire may be performed after the production of the sintered body, or the connection may be made by sintering after embedding a part of the metal wire during molding before the production of the sintered body. Examples of the type of metal wire include tantalum, niobium, aluminum, titanium, alloys containing these metals as main components, and those obtained by oxidizing and / or nitriding some of these metals or the alloys.
金属線としては、通常１ｍｍ以下の細線を使用する。陽極部とする部分に後記する半導体層が付着してコンデンサがショートすることを防ぐために、陽極部と残部の陽極基体の境界部に絶縁性樹脂を鉢巻状に付着させて絶縁を計ってもよい。 As the metal wire, a thin wire of usually 1 mm or less is used. In order to prevent the semiconductor layer to be described later from adhering to a portion serving as the anode portion and short-circuiting the capacitor, an insulating resin may be adhered in a headband shape to a boundary portion between the anode portion and the remaining anode substrate to measure insulation. .
本発明において、陽極部を除く陽極基体表面に形成させる誘電体酸化皮膜層（陽極部の全部または一部に該誘電体酸化皮膜層があっても良い）としては、Ｔａ2Ｏ5、Ａｌ2Ｏ3、Ｚｒ2Ｏ3、Ｎｂ2Ｏ5等の金属酸化物から選ばれる少なくとも１つを主成分とする誘電体層が挙げられる。該誘電体層は、前記陽極基体を電解液中で化成することによって得ることができる。また本出願人による国際公開公報WO00/75943号に記載されているように、金属酸化物から選ばれる少なくとも１つを主成分とする誘電体層とセラミックコンデンサで使用される誘電体層を混合した誘電体層であってもよい。 In the present invention, the dielectric oxide film layer formed on the surface of the anode substrate excluding the anode portion (the dielectric oxide film layer may be present on all or a part of the anode portion) is Ta 2 O 5 , Al 2 The dielectric layer mainly includes at least one selected from metal oxides such as O 3 , Zr 2 O 3 , and Nb 2 O 5 . The dielectric layer can be obtained by forming the anode substrate in an electrolytic solution. Further, as described in International Publication WO00 / 75943 by the present applicant, a dielectric layer containing at least one selected from metal oxides as a main component and a dielectric layer used in a ceramic capacitor are mixed. It may be a dielectric layer.
一方、本発明の誘電体層上に形成される半導体層の代表例として、有機半導体及び無機半導体から選ばれる少なくとも１種の化合物が挙げられる。有機半導体の具体例としては、ベンゾピロリン４量体とクロラニルからなる有機半導体、テトラチオテトラセンを主成分とする有機半導体、テトラシアノキノジメタンを主成分とする有機半導体、下記一般式（１）または（２）で表される繰り返し単位を含む高分子にドーパントをドープした電導性高分子を主成分とした有機半導体が挙げられる。 On the other hand, a typical example of the semiconductor layer formed on the dielectric layer of the present invention includes at least one compound selected from an organic semiconductor and an inorganic semiconductor. Specific examples of the organic semiconductor include an organic semiconductor composed of benzopyrroline tetramer and chloranil, an organic semiconductor composed mainly of tetrathiotetracene, an organic semiconductor composed mainly of tetracyanoquinodimethane, and the following general formula (1) Alternatively, an organic semiconductor mainly composed of a conductive polymer obtained by doping a dopant into a polymer containing a repeating unit represented by (2) can be used.
式（１）及び（２）において、Ｒ1〜Ｒ4は水素原子、炭素数１〜６のアルキル基または炭素数１〜６のアルコキシ基を表し、これらは互いに同一であっても相違してもよく、Ｘは酸素、イオウまたは窒素原子を表し、Ｒ5はＸが窒素原子のときのみ存在して水素原子または炭素数１〜６のアルキル基を表し、Ｒ1とＲ2及びＲ3とＲ4は、互いに結合して環状になっていてもよい。 In the formulas (1) and (2), R 1 to R 4 represent a hydrogen atom, an alkyl group having 1 to 6 carbon atoms or an alkoxy group having 1 to 6 carbon atoms. X represents an oxygen, sulfur or nitrogen atom; R 5 is present only when X is a nitrogen atom, and represents a hydrogen atom or an alkyl group having 1 to 6 carbon atoms, and R 1 and R 2 and R 3 R 4 may be bonded to each other to form a ring.
さらに、本発明においては、前記一般式（１）で表される繰り返し単位を含む電導性高分子としては、好ましくは下記一般式（３）で示される構造単位を繰り返し単位として含む電導性高分子が挙げられる。 Furthermore, in the present invention, the conductive polymer containing a repeating unit represented by the general formula (1) is preferably a conductive polymer containing a structural unit represented by the following general formula (3) as a repeating unit. Is mentioned.
式中、Ｒ6及びＲ7は、各々独立して水素原子、炭素数１〜６の直鎖状もしくは分岐状の飽和もしくは不飽和のアルキル基、または該アルキル基が互いに任意の位置で結合して、２つの酸素元素を含む少なくとも１つ以上の５〜７員環の飽和炭化水素の環状構造を形成する置換基を表わす。また、前記環状構造には置換されていてもよいビニレン結合を有するもの、置換されていてもよいフェニレン構造のものが含まれる。 In the formula, R 6 and R 7 are each independently a hydrogen atom, a linear or branched saturated or unsaturated alkyl group having 1 to 6 carbon atoms, or the alkyl groups are bonded to each other at an arbitrary position. Represents a substituent that forms a cyclic structure of at least one or more 5- to 7-membered saturated hydrocarbon containing two oxygen elements. The cyclic structure includes those having a vinylene bond which may be substituted and those having a phenylene structure which may be substituted.
このような化学構造を含む電導性高分子は、荷電されており、ドーパントがドープされる。ドーパントには公知のドーパントが制限なく使用できる。
式（１）乃至（３）で示される繰り返し単位を含む高分子としては、例えば、ポリアニリン、ポリオキシフェニレン、ポリフェニレンサルファイド、ポリチオフェン、ポリフラン、ポリピロール、ポリメチルピロール、及びこれらの置換誘導体や共重合体などが挙げられる。中でもポリピロール、ポリチオフェン及びこれらの置換誘導体（例えばポリ（３，４−エチレンジオキシチオフェン）等）が好ましい。
The conductive polymer having such a chemical structure is charged and doped with a dopant. Known dopants can be used without limitation as the dopant.
Examples of the polymer containing the repeating units represented by the formulas (1) to (3) include polyaniline, polyoxyphenylene, polyphenylene sulfide, polythiophene, polyfuran, polypyrrole, polymethylpyrrole, and substituted derivatives and copolymers thereof. And the like. Among them, polypyrrole, polythiophene and substituted derivatives thereof (for example, poly (3,4-ethylenedioxythiophene) and the like) are preferable.
無機半導体の具体例として、二酸化モリブデン、二酸化タングステン、二酸化鉛、二酸化マンガン等から選ばれる少なくとも１種の化合物が挙げられる。
上記有機半導体及び無機半導体として、電導度１０-2〜１０3Ｓ／ｃｍの範囲のものを使用すると、作製したコンデンサのＥＳＲ値が小さくなり好ましい。
Specific examples of the inorganic semiconductor include at least one compound selected from molybdenum dioxide, tungsten dioxide, lead dioxide, manganese dioxide, and the like.
It is preferable to use an organic semiconductor and an inorganic semiconductor having a conductivity in the range of 10 −2 to 10 3 S / cm, because the ESR value of the manufactured capacitor is reduced.
本発明では、前述した方法等で形成された半導体層の上に導電体層が設けられる。導電体層としては、例えば、導電ペーストの固化、メッキ、金属蒸着、耐熱性の導電樹脂フイルムの付着等により形成することができる。導電ペーストとしては、銀ペースト、銅ペースト、アルミペースト、カーボンペースト、ニッケルペースト等が好ましいが、これらは１種を用いても２種以上を用いてもよい。２種以上を用いる場合、混合してもよく、または別々の層として重ねてもよい。導電ペーストを適用した後、空気中に放置するか、または加熱して固化せしめる。メッキとしては、ニッケルメッキ、銅メッキ、銀メッキ、アルミメッキ等が挙げられる。また蒸着金属としては、アルミニウム、ニッケル、銅、銀等が挙げられる。 In the present invention, a conductor layer is provided on a semiconductor layer formed by the above-described method or the like. The conductor layer can be formed by, for example, solidifying a conductive paste, plating, metal deposition, attaching a heat-resistant conductive resin film, or the like. As the conductive paste, a silver paste, a copper paste, an aluminum paste, a carbon paste, a nickel paste, or the like is preferable, but one or more of these may be used. When two or more kinds are used, they may be mixed or may be stacked as separate layers. After applying the conductive paste, it is left in the air or heated to be solidified. Examples of the plating include nickel plating, copper plating, silver plating, and aluminum plating. Examples of the metal to be deposited include aluminum, nickel, copper, and silver.
具体的には、例えば半導体層が形成された陽極基体の上にカーボンペースト、銀ペーストを順次積層し導電体層が形成される。
このようにして陽極基体に導電体層まで積層して陰極部を形成した固体電解コンデンサ素子が作製される。
Specifically, for example, a conductive layer is formed by sequentially laminating a carbon paste and a silver paste on an anode substrate having a semiconductor layer formed thereon.
In this way, a solid electrolytic capacitor element in which the cathode portion is formed by laminating the conductor layer on the anode substrate is produced.
本発明のチップ状固体電解コンデンサは、前記固体電解コンデンサ素子を複数個用意し、各々の固体電解コンデンサ素子の陰極部の一部を、別途用意した一対の対向して配置されたリードフレームの一方の先端部に並列に隙間なく載置し、さらに陽極基体の陽極部を前記リードフレームの他方の先端部に載置し、例えば前者は導電ペーストの固化で、後者はスポット溶接で各々電気的・機械的に接合した後、前記リードフレームの外部端子となる部分を残して樹脂封口し、樹脂封口外の所定部でリードフレームを切断折り曲げ加工して作製される。具体的には、図１に示されたように、例えば３個の固体電解コンデンサ素子が、一対の対向して配置されたリードフレームの先端部に並列に隙間なく載置され封口して１つの角型、通常は直方体形状チップ状固体電解コンデンサが作製される。このような固体電解コンデンサの作製に際しては、切断されたリードフレームの納め場所として側面及び／または底面の一部に切り欠け部を設けたり、陽極と陰極を区別するために、例えば上面に切り欠け部を設けたり、あるいは樹脂封口時に作製したチップ状固体電解コンデンサが金型から離脱しやすいように、上面及び／または下面をテーパを切るように角度をつける細工をしておいても良い。 The chip-shaped solid electrolytic capacitor of the present invention is provided with a plurality of the solid electrolytic capacitor elements, a part of a cathode portion of each solid electrolytic capacitor element, one of a pair of separately prepared lead frames arranged facing each other. And the anode of the anode substrate is placed on the other end of the lead frame. For example, the former is a solidification of a conductive paste, and the latter is a spot welding by electric welding. After the mechanical joining, the lead frame is sealed with a resin except for the portion to be an external terminal, and the lead frame is cut and bent at a predetermined portion outside the resin seal. Specifically, as shown in FIG. 1, for example, three solid electrolytic capacitor elements are placed without gaps in parallel at the tip portions of a pair of opposedly arranged lead frames, and one A rectangular, usually rectangular solid chip-shaped solid electrolytic capacitor is produced. When manufacturing such a solid electrolytic capacitor, a cutout portion is provided on a part of a side surface and / or a bottom surface as a place for accommodating the cut lead frame, or a cutout is formed on a top surface, for example, to distinguish an anode from a cathode. A part may be provided, or the upper surface and / or the lower surface may be tapered so that the chip-shaped solid electrolytic capacitor produced at the time of sealing the resin is easily detached from the mold.
前記リードフレームは、前述したように切断加工されて最終的にはチップ状固体電解コンデンサの外部端子となるが、形状は、箔または平板状であり、材質は鉄、銅、アルミニウムまたはこれら金属を主成分とする合金が使用される。該リードフレームの一部または全部に半田、錫、チタン等のメッキが施されていても良い。リードフレームとメッキとの間に、ニッケル等の下地メッキがあっても良い。リードフレームは、２辺のフレームが互いに隙間を保って対向するように配置され、隙間があることによって各固体電解コンデンサ素子の陽極部と陰極部とが絶縁される。 The lead frame is cut as described above and finally becomes an external terminal of the chip-shaped solid electrolytic capacitor, but the shape is a foil or a flat plate, and the material is iron, copper, aluminum, or any of these metals. An alloy as a main component is used. A part or all of the lead frame may be plated with solder, tin, titanium, or the like. There may be a base plating of nickel or the like between the lead frame and the plating. The lead frame is arranged so that two frames face each other with a gap therebetween, and the gap insulates the anode and cathode of each solid electrolytic capacitor element.
本発明のチップ状固体電解コンデンサにおいて、コンデンサのチップ体積に対する陽極部を除いた焼結体１個の体積比を0.042〜0.110、好ましくは0.050〜0.100、より好ましくは0.070〜0.092にしておくと、ＥＳＲとＬＣ値の初期不良率が低くて良好なチップ状固体電解コンデンサが作製できる。前記体積比が0.042より小さいと、ＬＣ値の初期不良率が大きくなり、前記体積比が0.110より大きいと、ＥＳＲ（１００ｋＨｚ）が不良になる。従来の固体電解コンデンサでは、経験的に封口内のコンデンサ素子が小さくなると初期不良率が小さくなる傾向にあるが、本願の固体電解コンデンサ素子を複数個並列に隙間なく載置したチップ状固体電解コンデンサにおいては逆になる。これは、コンデンサ素子が封口した樹脂から受ける応力が素子の配置された状態により異なるためと考えられる。一方、ＥＳＲは、陽極基体の中心と導電体層との距離の関数なので、封口内のコンデンサ素子の大きさに比例する。これらのことから、前記体積比を指標としてコンデンサ素子の大きさを調整すると、上記両特性の良好なコンデンサを得ることができる。 In the chip-shaped solid electrolytic capacitor of the present invention, the volume ratio of one sintered body excluding the anode portion to the chip volume of the capacitor is 0.042 to 0.110, preferably 0.050 to 0.100, more preferably 0.070 to 0.092, A good chip-shaped solid electrolytic capacitor having a low initial failure rate of ESR and LC value can be manufactured. If the volume ratio is smaller than 0.042, the initial failure rate of the LC value increases, and if the volume ratio is larger than 0.110, the ESR (100 kHz) becomes poor. In a conventional solid electrolytic capacitor, the initial failure rate tends to decrease when the capacitor element inside the seal is reduced empirically, but a chip-shaped solid electrolytic capacitor in which a plurality of solid electrolytic capacitor elements of the present application are mounted in parallel without gaps. Is reversed in. This is presumably because the stress applied to the capacitor element from the sealed resin differs depending on the state in which the elements are arranged. On the other hand, since the ESR is a function of the distance between the center of the anode substrate and the conductive layer, it is proportional to the size of the capacitor element inside the seal. From these facts, when the size of the capacitor element is adjusted using the volume ratio as an index, a capacitor having both of the above characteristics can be obtained.
本発明のチップ状固体電解コンデンサの封口に使用される樹脂の種類としては、エポキシ樹脂、フェノール樹脂、アルキッド樹脂等チップ状固体電解コンデンサの封止に使用される公知の樹脂が採用できる。また、樹脂封口するための製造機としてトランスファーマシンが好んで使用される。
本発明は、一般に使用されるチップサイズ、特に長さ、幅、及び高さが、7.3×4.3×1.0ｍｍ、7.3×4.3×1.8ｍｍ、7.3×4.3×2.8ｍｍ、7.3×4.3×3.8ｍｍ、6.0×3.2×1.0ｍｍ、6.0×3.2×1.8ｍｍ、6.0×3.2×2.8ｍｍ、及び6.0×3.2×3.8ｍｍのチップサイズのコンデンサに好ましく適用できる。
As the type of resin used for sealing the chip-shaped solid electrolytic capacitor of the present invention, a known resin used for sealing chip-shaped solid electrolytic capacitors, such as an epoxy resin, a phenol resin, and an alkyd resin, can be adopted. A transfer machine is preferably used as a manufacturing machine for sealing the resin.
The present invention relates to commonly used chip sizes, especially length, width, and height of 7.3 × 4.3 × 1.0 mm, 7.3 × 4.3 × 1.8 mm, 7.3 × 4.3 × 2.8 mm, 7.3 × 4.3 × 3.8 mm, It can be preferably applied to capacitors having a chip size of 6.0 × 3.2 × 1.0 mm, 6.0 × 3.2 × 1.8 mm, 6.0 × 3.2 × 2.8 mm, and 6.0 × 3.2 × 3.8 mm.
また本発明のチップ状固体電解コンデンサは、例えば、電圧安定化回路や、ノイズ除去回路等の高容量のコンデンサを用いる回路に好ましく用いることができる。これらの回路は、パソコン、サーバー、カメラ、ゲーム機、ＤＶＤ、ＡＶ機器、携帯電話等の各種デジタル機器や、各種電源等の電子機器に利用可能である。本発明で製造されたチップ状固体電解コンデンサは、初期不良率が小さいことから、これらを用いることにより、初期不良率の低い電子回路及び電子機器を得ることができる。 Further, the chip-shaped solid electrolytic capacitor of the present invention can be preferably used for a circuit using a high-capacity capacitor such as a voltage stabilizing circuit and a noise removing circuit. These circuits can be used in various digital devices such as a personal computer, a server, a camera, a game machine, a DVD, an AV device, and a mobile phone, and electronic devices such as various power supplies. Since the chip-shaped solid electrolytic capacitor manufactured by the present invention has a small initial failure rate, by using these, an electronic circuit and an electronic device having a low initial failure rate can be obtained.
以下、本発明の具体例についてさらに詳細に説明するが、以下の例により本発明は限定されるものではない。
下記の例について作製したチップ状固体電解コンデンサの半田実装条件は、２６０℃ピーク（１５０℃で４０秒放置その後昇温して２３０℃以上が３０秒、）の温度パターンを取るように設定したリフロー炉を３回通過させる条件とした。実装後のＬＣ測定は、４Ｖで３０秒値とした。なお各測定数は、ｎ＝３２０点とし、ＬＣ値が、0.1ＣＶ以下のものを合格とした。
Hereinafter, specific examples of the present invention will be described in more detail, but the present invention is not limited to the following examples.
The solder mounting conditions of the chip-shaped solid electrolytic capacitor prepared for the following example were set to a temperature pattern of 260 ° C. peak (left at 150 ° C. for 40 seconds and then heated to 230 ° C. or more for 30 seconds). The conditions for passing through the furnace three times were set. The LC measurement after mounting was performed at 4 V for 30 seconds. The number of each measurement was n = 320, and those having an LC value of 0.1 CV or less were accepted.
実施例１〜３及び比較例１〜２：
ＣＶ（容量と化成電圧の積）５万／ｇのタンタル粉を使用して、表１に示すように大きさ4.0 ×Ｗ×1.8 ｍｍの焼結体を作製した（タンタル質量と寸法Ｗｍｍについては、表１に記載。焼結温度1420℃、焼結時間２０分、焼結体密度6.4ｇ／ｃｍ3、Ｔａリード線0.24ｍｍφ、焼結体の４ｍｍ寸法の長手方向と平行にＴａリード線の一部が埋設されていて焼結体から突き出たリード線部が陽極部となる。）。陽極となる焼結体を0.1％燐酸水溶液中にリード線の一部を除いて浸漬し、陰極のＴａ板電極との間に１８Ｖを印加し、８０℃で３時間化成してＴａ2Ｏ5からなる誘電体酸化皮膜層を形成した。この焼結体のリード線を除いて、２０％酢酸鉛水溶液と３５％過硫酸アンモニウム水溶液の１：１混合液に浸漬し４０℃で１時間放置した後引き上げ水洗後乾燥することを２５回繰り返して、誘電体酸化皮膜層上に二酸化鉛と硫酸鉛との混合物（二酸化鉛が９６％）からなる半導体層を形成した。さらに半導体層上にカーボンペースト、銀ペーストを順次積層し陰極部を形成し固体電解コンデンサ素子を作製した。
別途用意した、表面に錫メッキした厚さ１００μｍの銅合金リードフレーム（幅3.4ｍｍの一対の先端部が３２個存在し、陰極部が載置される先端部は、図１の段差相当部分が0.9ｍｍあり、載置部の長さは4.3ｍｍある。両先端部には同一平面に投影して１ｍｍの隙間がある。）の一対の先端部に、前記した固体電解コンデンサ素子を３個並列に水平に隙間なく接続した（固体電解コンデンサ素子の陰極側、即ち焼結体の4.0×Ｗの面を、段差が存在する先端部に載置し、固体電解コンデンサ素子の陽極側は、他方の先端部に載置し、前者は、銀ペーストの固化で、後者は、スポット溶接で電気的・機械的に接続した。１枚のリードフレームに固体電解コンデンサ素子は、各一対の先端部に３個、全部で９６個接続された。）。ついで、リードフレームの両先端部の一部と固体電解コンデンサ素子を封口するためにエポキシ樹脂でトランスファー成形し、大きさ7.3×4.3×2.8ｍｍのチップ状固体電解コンデンサを作製した（封口後封口外の両先端部の封口端面から各々3.4ｍｍのところを切断し、残りのフレームを除去した後、チップ状固体電解コンデンサに接続された外側に残った先端部をコンデンサの外周に沿って折り曲げ加工し、外部端子とした。１リードフレームから３２個のチップ状固体電解コンデンサが作製された。）。
Examples 1-3 and Comparative Examples 1-2:
Using tantalum powder having a CV (product of capacity and formation voltage) of 50,000 / g, a sintered body having a size of 4.0 × W × 1.8 mm was produced as shown in Table 1 (for the tantalum mass and the dimension Wmm, It is described in Table 1. The sintering temperature is 1420 ° C., the sintering time is 20 minutes, the sintered body density is 6.4 g / cm 3 , the Ta lead wire is 0.24 mmφ, and the Ta lead wire is parallel to the longitudinal direction of the sintered body having a dimension of 4 mm. The lead wire part which is partially buried and protrudes from the sintered body becomes the anode part.) The sintered body serving as the anode was immersed in a 0.1% phosphoric acid aqueous solution except for a part of the lead wire, 18 V was applied between the electrode and the Ta plate electrode of the cathode, and formed at 80 ° C. for 3 hours to form Ta 2 O 5. Was formed. Except for the lead wire of this sintered body, immersion in a 1: 1 mixed solution of a 20% aqueous lead acetate solution and a 35% aqueous ammonium persulfate solution, standing at 40 ° C. for 1 hour, pulling up, washing with water, and drying were repeated 25 times. A semiconductor layer made of a mixture of lead dioxide and lead sulfate (96% lead dioxide) was formed on the dielectric oxide film layer. Further, a carbon paste and a silver paste were sequentially laminated on the semiconductor layer to form a cathode portion, thereby producing a solid electrolytic capacitor element.
A separately prepared, tin-plated, copper-plated lead frame with a thickness of 100 μm (32 pairs of 3.4 mm wide tips, and the tip on which the cathode is placed has a portion corresponding to the step in FIG. 1). 0.9 mm, the length of the mounting portion is 4.3 mm, and there is a gap of 1 mm when projected on the same plane at both ends.) (The cathode side of the solid electrolytic capacitor element, that is, the 4.0 × W surface of the sintered body is placed on the tip where the step exists, and the anode side of the solid electrolytic capacitor element is connected to the other side. The solid electrolytic capacitor element was connected to one lead frame, and the solid electrolytic capacitor element was connected to each pair of distal ends by three points. And 96 in total.) Next, transfer molding was performed with epoxy resin to seal a part of both ends of the lead frame and the solid electrolytic capacitor element, thereby producing a chip-shaped solid electrolytic capacitor having a size of 7.3 × 4.3 × 2.8 mm. After cutting 3.4 mm from the sealing end face of both ends of each tip, removing the remaining frame, bend the outer tip connected to the chip-shaped solid electrolytic capacitor along the outer periphery of the capacitor. And 32 external solid electrolytic capacitors from one lead frame.)
実施例４〜６及び比較例３：
実施例１で焼結体のＣＶ値を８万／ｇとし、寸法を4.0×Ｗ×1.0ｍｍとし、焼結体の焼結を1340℃３０分で焼結体密度を5.6ｇ／ｃｍ3とし、半導体層をポリピロール（焼結体を５％ピロールアルコール溶液と、0.1％アンソラキノンスルフォン酸及び１０％過硫酸アンモニウムの混合水溶液に交互に浸漬し、４０℃で反応させることを５５回繰り返して形成）とし、リードフレームの段差を0.5ｍｍとし、チップ形状を7.3×4.3×1.8ｍｍとし、封口後の切断位置を2.9ｍｍとした以外は、実施例１と同様にしてチップ状固体電解コンデンサを作製した。
Examples 4 to 6 and Comparative Example 3:
In Example 1, the CV value of the sintered body was 80,000 / g, the dimensions were 4.0 × W × 1.0 mm, the sintered body was sintered at 1340 ° C. for 30 minutes, and the sintered body density was 5.6 g / cm 3. The semiconductor layer is formed by repeatedly immersing the semiconductor layer in polypyrrole (a sintered body is alternately immersed in a 5% pyrrole alcohol solution and a mixed aqueous solution of 0.1% anthoraquinone sulfonic acid and 10% ammonium persulfate, and reacted at 40 ° C. 55 times) ), A chip-shaped solid electrolytic capacitor was produced in the same manner as in Example 1 except that the step of the lead frame was 0.5 mm, the chip shape was 7.3 × 4.3 × 1.8 mm, and the cutting position after sealing was 2.9 mm. did.
実施例７〜９及び比較例４：
実施例１で、焼結体寸法を4.0×Ｗ×2.5ｍｍとし、半導体層をポリ−エチレンジオキシチオフェン（焼結体をエチレンジオキシチオフェンとアンソラキノンスルフォン酸水溶液＜各微量溶解＞に浸漬し、１７０時間電解重合して形成）とし、リードフレームの段差を1.3ｍｍとし、チップ形状を7.3×4.3×3.5ｍｍとし、封口後の切断位置を3.8ｍｍとした以外は、実施例１と同様にしてチップ状固体電解コンデンサを作製した。
Examples 7 to 9 and Comparative Example 4:
In Example 1, the size of the sintered body was 4.0 × W × 2.5 mm, and the semiconductor layer was immersed in poly-ethylenedioxythiophene (the sintered body was immersed in an aqueous solution of ethylenedioxythiophene and anthoraquinonesulfonic acid (each trace amount dissolved). And formed by electrolytic polymerization for 170 hours), the steps of the lead frame were set to 1.3 mm, the chip shape was set to 7.3 × 4.3 × 3.5 mm, and the cutting position after sealing was set to 3.8 mm, the same as Example 1. Thus, a chip-shaped solid electrolytic capacitor was manufactured.
以上作製した各チップ状固体電解コンデンサの寸法Ｗ、チップ体積に対する陽極部を除いた焼結体１個の体積比、容量、コンデンサ内使用全焼結体質量当たりの容量、ＥＳＲ（１００ｋＨｚ）、基板実装後のＬＣの良品率（0.1 ＣＶ以下を合格とした。このときの電圧値を４Ｖとした）を表１に示した。なお、容量、ＥＳＲはｎ＝３２０個の平均値である。 The dimensions W of each chip-shaped solid electrolytic capacitor produced above, the volume ratio of one sintered body excluding the anode portion to the chip volume, the capacity, the capacity per mass of all the sintered bodies used in the capacitor, ESR (100 kHz), board mounting Table 1 shows the non-defective product ratio of the LC afterwards (pass of 0.1 CV or less; voltage at this time was 4 V). The capacity and ESR are average values of n = 320 pieces.
実施例１〜３と比較例１〜２、実施例４〜６と比較例３、実施例７〜９と比較例４を比べることにより、チップ体積に対する陽極部を除いた焼結体１個の体積比が、0.042〜0.110であれば、体積比以外ほぼ同様なコンデンサに比べＥＳＲが良好で、しかも故障率が小さいチップ状固体電解コンデンサが作製できることが分かる。 By comparing Examples 1-3 with Comparative Examples 1-2, Examples 4-6 with Comparative Example 3, and Examples 7-9 with Comparative Example 4, one sintered body excluding the anode part with respect to the chip volume was obtained. It can be seen that when the volume ratio is 0.042 to 0.110, a chip-shaped solid electrolytic capacitor having a good ESR and a small failure rate can be manufactured as compared with almost the same capacitor except for the volume ratio.
本発明は、チップ体積に対する陽極部を除いた焼結体１個の体積比が、0.042〜0.110であるチップ状固体電解コンデンサを提供したものであり、本発明によれば、ＥＳＲが良好で、初期不良率が小さいチップ状固体電解コンデンサを得ることができる。 The present invention provides a chip-shaped solid electrolytic capacitor in which the volume ratio of one sintered body excluding the anode part to the chip volume is 0.042 to 0.110, and according to the present invention, the ESR is good. A chip-shaped solid electrolytic capacitor having a small initial failure rate can be obtained.
１ リードフレーム
１ａ，１ｂ リードフレーム先端部
２ 固体電解コンデンサ素子
３ 陰極部
４ 陽極部
４ａ 陽極リード
５ 外装部
DESCRIPTION OF SYMBOLS 1
Claims (18)
で示される繰り返し単位を含む高分子にドーパントをドープした導電性高分子を主成分とした有機半導体から選択される少なくとも１種である請求項１０記載のチップ状固体電解コンデンサ。 The organic semiconductor is an organic semiconductor composed of benzopyrroline tetramer and chloranil, an organic semiconductor composed mainly of tetrathiotetracene, an organic semiconductor composed mainly of tetracyanoquinodimethane, and the following general formula (1) or (2) )
The chip-shaped solid electrolytic capacitor according to claim 10, wherein the capacitor is at least one selected from organic semiconductors containing a conductive polymer obtained by doping a polymer containing a repeating unit represented by the following formula with a dopant as a main component.
で示される構造単位を繰り返し単位として含む導電性高分子である請求項１１記載のチップ状固体電解コンデンサ。 The conductive polymer containing the repeating unit represented by the general formula (1) is represented by the following general formula (3)
The solid electrolytic capacitor according to claim 11, which is a conductive polymer containing a structural unit represented by the following as a repeating unit.
An electronic device using the solid electrolytic capacitor chip according to any one of claims 1 to 16.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310809A (en) * | 2005-03-29 | 2006-11-09 | Sanyo Electric Co Ltd | Solid electrolytic capacitor |
| JP2007103575A (en) * | 2005-10-03 | 2007-04-19 | Rohm Co Ltd | Solid electrolytic capacitor |
| US7568778B2 (en) | 2005-03-30 | 2009-08-04 | Brother Kogyo Kabushiki Kaisha | Image Forming Apparatus |
| US7837194B2 (en) | 2005-03-30 | 2010-11-23 | Brother Kogyo Kabushiki Kaisha | Feeding apparatus and image forming system |
| CN112243529A (en) * | 2018-06-11 | 2021-01-19 | 株式会社村田制作所 | Capacitor array, composite electronic component, method for manufacturing capacitor array, and method for manufacturing composite electronic component |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310809A (en) * | 2005-03-29 | 2006-11-09 | Sanyo Electric Co Ltd | Solid electrolytic capacitor |
| US7568778B2 (en) | 2005-03-30 | 2009-08-04 | Brother Kogyo Kabushiki Kaisha | Image Forming Apparatus |
| US7837194B2 (en) | 2005-03-30 | 2010-11-23 | Brother Kogyo Kabushiki Kaisha | Feeding apparatus and image forming system |
| JP2007103575A (en) * | 2005-10-03 | 2007-04-19 | Rohm Co Ltd | Solid electrolytic capacitor |
| CN112243529A (en) * | 2018-06-11 | 2021-01-19 | 株式会社村田制作所 | Capacitor array, composite electronic component, method for manufacturing capacitor array, and method for manufacturing composite electronic component |
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