JP2004282179A - Image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus capable of selecting an optimum processing path when a fast response is required. <P>SOLUTION: The image processing apparatus wherein an input module 12, an output module 13, processing modules 14, 15 and memories 16, 17 are connected by a packet switch 11 having a plurality of ports and independent paths for data transfer between optional ports, is provided with path control means 18, 19 for deciding the processing path depending on data information from the input module 12 and a data transfer capability required for each path in the processing apparatus, and applies selection control to the data transfer path depending on a data transfer delay time by each processing path and a type of data to be transferred. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image processing apparatus that processes data from at least one input unit and forms an image, such as a copier, a printing machine, a printer, a facsimile, and a multifunction peripheral thereof.
[0002]
[Prior art]
FIG. 5 shows a very simplified configuration of a conventional bus technology-based image processing apparatus. An input module 1 such as a scanner that captures an image, an output module 2 such as a plotter that outputs an image, and a plurality of processing modules 3 that perform various types of image processing from input to output are connected via a common bus 4. Connected to one main memory 5.
[0003]
[Problems to be solved by the invention]
Since each processing module 3 performs data transfer via the common bus 4, if one module 3 uses the main memory 5, the other modules 3 cannot access the main memory 5 during that time, and must wait. become. In order to be able to perform processing until the bus 4 becomes empty, a certain amount of buffer memory may be prepared also on the module 3 side, but the capacity of the buffer memory increases with an increase in speed. In addition, since all processing is performed by the common bus 4, an extremely high-speed data transfer processing capability is required.
Therefore, an object of the present invention is to solve the above-mentioned problems and to provide an image processing apparatus capable of selecting an optimum processing path when a fast response is required.
[0004]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, there is provided a packet switch in which an input module, an output module, a processing module and a memory have a plurality of ports and an independent path for data transfer between any ports. The image processing apparatus is connected by (1), and determines a processing path based on data information from an input module and a data transfer capability required for each path in the apparatus, and also includes a data transfer delay time for each processing path and data to be transferred. The most main feature is an image processing apparatus provided with a path control means for selecting and controlling a data transfer path according to the type.
According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the minimum required data transfer capability for each data type between the input module and the output module and the data transfer delay time for each path are stored in the memory. The main feature is an image processing device for storing.
According to a third aspect of the present invention, in the image processing apparatus of the second aspect, the main feature is that the data transfer delay time information of each path stored in the memory uses a value measured at power-on. .
According to a fourth aspect of the present invention, in the image processing apparatus of the second aspect, the minimum required data transfer capability for each data type between the input module and the output module stored in the memory is changed in the configuration of the apparatus. The main feature is an image processing device that is updated every time.
According to a fifth aspect of the present invention, in the image processing apparatus according to any one of the first to fourth aspects, the memory stores route information, data transfer capability, and delay time when a route is changed. The device is the main feature.
[0005]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram of an image processing apparatus according to a first embodiment of the present invention. In the present invention, a packet switch 11 as shown in FIG. 1 is used in place of a bus as an architecture of an image device, and each port of the packet switch 11 has an input module 12, an output module 13, various processing modules 14, 15 and a memory 16, 17 are connected to form a device.
In the packet switch 11 used here, an independent path for data transfer is prepared between arbitrary ports. At this time, it is needless to say that routes that need not be used may be omitted. For this reason, simultaneous data transfer on different routes is possible. Reference numeral 18 denotes a route control determining unit, and 19 denotes a route control unit.
For example, in FIG. 1, assuming that the packet switch 11 and each module are a bidirectional link, while transferring data from the input module 12 to the memory 16, simultaneously transferring data from the memory 16 to the processing module A (processing module 14), Similarly, data can be simultaneously transferred to the output module 13 via the memory 17 and the processing module B (processing module 15) in a pipeline manner.
Since each path performs data transfer independently, the bus format inevitably causes a delay for idle waiting and the buffer memory required for it becomes unnecessary, real-time processing becomes possible, and processing speed is greatly improved. it can. In addition, each path itself can be sufficiently realized with a lower transfer capability than the common bus, and is easily realized electrically. Further, by changing the connection state of the path in the packet switch 11 according to the processing content, various processes can be easily realized. The route control judging unit 18 and the route control unit 19 control the connection state of the route in each switch.
FIG. 2 is an example of a configuration diagram of the packet switch 11. The description will be made using a 4-port switch. Each port has an input port and an output port, and a packet entered from port 1 is sent to any of the remaining ports 2, 3, and 4 via the switch 20 based on information on the transfer destination in the packet. Assuming that port 3 is selected, the packet is input to the selector 21 of port 3.
Although packets from ports 2 and 4 can also be input to this selector 21, each processing path is uniquely determined if the processing content is determined. Therefore, only packets from port 1 are output to port 3 from port 3. The selector 21 may be set as described above. At this time, a path from port 3 to port 4, port 2 to port 1, and port 4 to port 2 can be set simultaneously. Up to four routes can be set at the same time, greatly improving the overall data transfer speed.
If the changeover switch 20 is not used to select any one output port, but a plurality of output ports are selected at the same time, the same data can be sent to a plurality of modules at the same time. The path control unit 19 controls the changeover switch 20.
[0006]
FIG. 3 is a configuration diagram of an image processing apparatus according to the second embodiment of the present invention. In the second embodiment, a plurality of packet switches 11 are prepared and extended to a packet switch network in which arbitrary packet switches are connected by independent paths. In this case, unnecessary routes may be omitted. Reference numeral 22 indicates a processing module C.
It is not feasible to develop a huge switch with dozens of ports that directly connect all modules, because the number of internal paths becomes astronomical. A relatively small and very flexible device can be configured by using the data transfer.
If a processing module that handles the same data is connected to a packet switch as close as possible, data transfer to a distant module will not occur so much, and the number of paths at the switch network level can be further reduced.
In FIG. 3, there are four processing modules B, and two ports are connected to each of them. For a module requiring a long processing time, a plurality of identical function modules are prepared in this way to distribute the load, and the ports are also connected. By increasing the transfer capacity, the processing can be adjusted so that the processing is completed in the same time as other processing. Therefore, the overall processing capacity can be increased.
As described above, various routes can be selected, but at this time, how to select a connection route becomes important. In general, the optimal data transfer capability is required based on data information from the input unit, data transfer capability required for each path in the device, data transfer capability held in each route in the device, and processing capability of each processing module. The connection route is determined by the route control determination unit 18 and the route control unit 19 is controlled based on the result to secure an optimal route. However, the delay time in the packet switch 11 in the connection route is large. Therefore, the transfer time is delayed as the number of packet switches increases. Therefore, in the present invention, the path selection is performed including the data delay time for each path including the delay in the packet switch 11 as a factor of the data path selection.
[0007]
FIG. 4 is a diagram showing a specific example of packet switching in the image processing apparatus of the present invention. The case where the delay time must be taken into account will be described. FIG. 4 shows a total of two command lines for input / output commands for transferring data between the input module 12 such as a scanner and the output module 13 such as a laser printer. Shows the case where lines are allocated.
FIG. 4A shows a normal example in which a high-speed path is assigned to data transfer. However, depending on the type of output device such as a laser printer, there is a case where data transfer timing is performed by exchanging command lines. In such a case, if the delay of the command line is large, the start of data transfer may not be in time.
Therefore, when the allowable response delay of the command line is small, a path having a high response speed (a path that does not include a packet switch as much as possible in the middle) is selected as shown in FIG. At this time, if the transfer capability of the data line is insufficient, a route to be transmitted to the output device via a memory buffer or the like is selected in the middle as shown in FIG. 4 (3) to supplement the transfer capability.
The delay time including the packet switch for each route and the allowable response speed are stored in a storage device such as a memory in advance, and the control device or a program can search for an optimal route based on the value. .
Further, a timer circuit or the like may be provided, delay measurement may be performed when the power is turned on, and the measured value may be stored in the storage device. This is to constantly update information when the route is changed due to a change in the device configuration or the like.
When there is a change in the image processing configuration such as a change in the connected input device or output device, information is received from the changed input device or output device and reflected in the storage device. The information may be obtained from a storage area stored in each device, or may be provided by a program or the like.
In addition, when the initial connection path or the connection path changes, the path information (what kind of path is connected), the data transfer capacity of the path, the delay time, and the data transfer capacity required for input / output And the like may be stored in a memory, and may be used as information for determining whether a route change is necessary or for selecting a route (for example, selecting a route in a similar situation).
[0008]
【The invention's effect】
As described above, according to the first to fourth aspects of the present invention, by selecting a path in consideration of a delay time, it is possible to provide an optimal processing path for an image processing apparatus that requires a fast response.
According to the fifth aspect, by collecting the information on the route selection, the route selection utilizing the past information can be performed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an image processing apparatus according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram of a packet switch 11;
FIG. 3 is a configuration diagram of an image processing apparatus according to a second embodiment of the present invention.
FIG. 4 is a diagram illustrating a specific example of packet switching in the image processing apparatus of the present invention.
FIG. 5 is a configuration diagram of a conventional bus technology-based image processing apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 Packet switch 12 Input module 13 Output module 14, 15 Processing module 16, 17 Memory 18 Route control judgment part 19 Route control part (route control means)

Claims (5)

An image processing apparatus in which an input module, an output module, a processing module, and a memory are connected by a packet switch having a plurality of ports and having an independent path for data transfer between any ports, and the data from the input module. A path control means for judging a processing path based on information and a data transfer capability required for each path in the apparatus, and selecting and controlling a data transfer path according to a data transfer delay time for each processing path and a type of data to be transferred; An image processing apparatus characterized in that: 2. The image processing apparatus according to claim 1, wherein a minimum required data transfer capability between the input module and the output module for each data type and a data transfer delay time for each path are stored in a memory. Processing equipment. 3. The image processing apparatus according to claim 2, wherein the data transfer delay time information of each path stored in the memory uses a value measured at power-on. 3. The image processing apparatus according to claim 2, wherein the minimum required data transfer capability for each data type between the input module and the output module stored in the memory is updated every time the configuration of the apparatus is changed. Characteristic image processing device. 5. The image processing apparatus according to claim 1, wherein the memory stores path information, data transfer capability, and delay time when the path is changed.

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