JP2004280992A - Associative memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an associative memory which allows a correct retrieval result to be always obtained regardless of the performance of word linking and has low power consumption and a high retrieval throughput. <P>SOLUTION: In the associative memory, each one word circuit is provided with; a CAM word which stores a one-word portion of data and retrieves coincidence between stored data and retrieval data to output the retrieval result; a first means which outputs a signal obtained by operating the logic between the retrieval result outputted from the CAM word of the one word circuit and a coincidence flag outputted from a corresponding one word circuit of a CAM block in the preceding stage; a register which latches the signal outputted from the first means as a coincidence flag; a second means which outputs the coincidence flag outputted from the register to a corresponding one work circuit of a CAM block in the succeeding stage; and a third means which outputs the coincidence flag outputted from the register to a priority encoder. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an associative memory having a word linking function of linking a plurality of words to form entry data and expanding the bit width of entry data to be searched to a bit width corresponding to the number of words.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a semiconductor memory having a function of simultaneously performing a match search between data stored in a plurality of words and search data and outputting an address of a word in which data matching the search data is stored, or data related thereto As an apparatus, an associative memory (Content Addressable Memory: hereinafter, referred to as CAM) for performing data search according to contents is well known.
[0003]
FIG. 14 is a block diagram of an example of a conventional CAM. The CAM 70 shown in FIG. 7 includes N words W_1, W_2,..., W_n composed of m-bit CAM cells arranged in the horizontal direction in the figure, a comparison register 72 for storing m-bit search data, and an m-bit , MFR_1, MFR_2,..., MFR_n, and a priority encoder 78.
[0004]
The CAM 70 includes, in addition to the above circuits, a decoder for writing / reading data to / from each of the words W_1, W_2,..., W_n, similarly to a normal semiconductor memory device, and an m-bit data bit line. Although circuits such as a driver and a sense amplifier are provided, they are omitted here to avoid complexity of the drawing.
[0005]
In the CAM 70, data is stored in each of the words W_1, W_2,..., W_n before the search.
[0006]
At the time of search, m bits of search data are stored in the comparison register 72, and m bits of mask data are stored in the mask register 74. Each bit of the m-bit search data is masked by a corresponding bit of the m-bit mask data, and the m-bit search data after the mask processing is searched by the search bit line driver 76 for the corresponding m-bit search data. Driven on bit line.
[0007]
In each of the words W_1, W_2,..., W_n, the coincidence search between the stored m-bit data and the m-bit search data driven on the m-bit search bit line is performed simultaneously (in parallel). The search results are stored as match flags in the corresponding match flag registers MFR_1, MFR_2,..., MFR_n via the match lines ML_1, ML_2,.
[0008]
The match flag stored in the match flag register is input to the priority encoder 78 via the match flag output lines MF_1, MF_2,..., MF_n, and is given the highest priority among words in which a match is detected according to a predetermined priority. The address of the word of the order (highest priority match address: HMA) is output.
[0009]
For example, as a result of the search, '0', '1', '1', '0', ..., '1', '0' are stored as match flags in the match flag registers MFR_1, MFR_2, ..., MFR_n, respectively. The following describes the case. Here, the match flag “1” means that there is a match, and “0” means that there is no match. In addition, it is assumed that the word has the highest priority in W_1, and the priority decreases sequentially toward W_n.
[0010]
In this case, since a match is detected in words W_2, W_3,..., W_n−1, the address of word W_2 is output as HMA. Also, by clearing the match flag stored in the match flag register MFR_2 to '0', the address corresponding to the next highest word W_3 can be output as HMA. In the same manner, the addresses of the words for which a match is detected can be sequentially output.
[0011]
In the CAM 70 having the above-described basic configuration, the word is fixed to a specific bit width in design, and in the above example, the width is fixed to m bits. . That is, a search for data having a bit width smaller than m bits can be performed by setting mask data in the mask register 74 and specifying a bit position to be searched. Can not be searched.
[0012]
As one means for solving such a problem of the conventional CAM 70, Patent Document 1 discloses that the bit width of the CAM is extended to two words or more words by concatenating words to be searched. Technology has been proposed.
[0013]
FIG. 15 is a configuration circuit diagram of a bit width extension circuit proposed in the CAM of Patent Document 1. The bit width expansion circuit 80 shown in FIG. 7 includes latches LT_1, LT_2,..., LT_n for holding a match flag in each of the words W_1, W_2,. .., W_n are provided with AND gates AD_2, AD_3,..., AD_n which take the logical product of their own search results and the match flags of the preceding words W_1, W_2,. ing.
[0014]
In the CAM of Patent Document 1 including the bit width extension circuit 80, before performing a search, outputs MF_1 and MF_2 of latches LT_1, LT_2,..., LT_n of all the words W_1, W_2,. ., MF_n are all initialized to “1”, that is, the state of coincidence. Thereby, one of the inputs of the AND gates AD_2, AD_3,..., AD_n of the words W_2, W_3,.
[0015]
For example, in a case where search is performed using search data having a bit width of two words by performing word concatenation, first, the first search is performed using the search data of the first one word of the search data of two words. Done.
[0016]
As a result, the search result of the word W_1 is stored in the latch LT_1. , W_n are latched LT_1, LT2,..., LT_n−1 of the preceding words W_1, W_2,..., W_n−1 by AND gates AD_2, AD_2,. , MF_2,..., MF_n−1, and the operation result is stored as a match flag in the corresponding latches LT_2, LT_3,.
[0017]
In the case of the first search, as described above, the outputs MF_1, MF_2,..., MF_n of the latches LT_1, LT_2,..., LT_n are “1”. The search results of W_2, W_3,..., W_n are output as they are and stored in the corresponding latches LT_2, LT_3,.
[0018]
Subsequently, a second search is performed using the second one-word search data of the two-word search data.
[0019]
In the case of the second search, one of the inputs of the AND gates AD_2, AD_3,..., AD_n is a match flag of the first search result, so that the AND gates AD_2, AD_3,. ,..., W_n−1 and the second search result of the words W_2, W_3,. That is, an AND search for two words is performed.
[0020]
As described above, in the CAM of Patent Document 1, when k words are concatenated and a search is performed using search data having a bit width of k words, k words are searched for using the corresponding search data of 1 word. The final search result can be obtained by performing the AND search twice.
[0021]
By the way, in the CAM of Patent Document 1, it is possible to search data extending over two or more words by providing the above-described bit extension function. However, there is a problem that an erroneous search result may be output depending on search data. There was a point.
[0022]
FIG. 16 is a conceptual diagram of an example of a data structure that may output an incorrect search result in the CAM of Patent Document 1. FIG. 1 shows a data structure in which four data items having attributes I, II, III, and IV form a set, respectively. The data of each of the attributes I, II, III, and IV has the same bit length as the bit length of one word, and is stored in separate words.
[0023]
Data of the attributes I, II, III, and IV of each entry shown in FIG. 16 is registered in each word of the CAM as shown in FIG. 17, and as search data for four words corresponding to one entry, for example, "ABCD" As described above, first, the search is performed using the search data 'A' in the first search, and the search data 'B', 'C', ' By performing a search with D ', a correct search result can be obtained. In this case, entry 2 matches.
[0024]
On the other hand, when a search is performed using, for example, “BDAB” as search data, the attributes III and IV of the entry 1 and the attributes I and II of the entry 2 despite the fact that a match should be detected only in the entry 4 A match is also detected in the data “BDAB” that straddles.
[0025]
Further, as an example of a method of using a CAM in which such data is registered, for example, a search may be performed only for data registered in attributes I and II. In this case, when a search is performed using, for example, “AB” as search data, a match is erroneously detected even in the data “AB” of the attributes II and III of the entry 1 although a match should be detected only in the entry 2. Is done.
[0026]
Further, the CAM of Patent Document 1 is based on the extension of the bit width between adjacent words. Therefore, in order to perform a search with bit expansion between data registered in non-adjacent words, for example, to perform a search on non-adjacent data of attribute I and attribute III, first, After performing a search with the search data of the attribute I, a dummy search is performed with the search data in which all the bits are masked, and the search results of the attribute II of all entries are matched, and thereafter, the search is performed with the search data of the attribute III Need to do.
[0027]
However, there is a problem that such a redundant dummy search significantly reduces the CAM search throughput.
[0028]
Further, in the CAM, since the search operation is performed simultaneously for all the words, there is a problem that the current consumption is essentially large. However, when performing the sequential search using the entry data as shown in FIG. In the case of searching, the CAM of Patent Document 1 always searches all words, that is, data of all attributes, even though the remaining attributes II, III, and IV do not originally need to perform the search operation. Therefore, there is a problem that unnecessary current is consumed.
[0029]
Further, in the CAM of Patent Document 1, in order to obtain a correct search result, it is necessary to initialize all the latches LT_1, LT_2,..., LT_n before the search. There is also a problem that the throughput is reduced.
[0030]
[Patent Document 1]
JP-B-63-5839
[0031]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a content addressable memory that solves the above-described problems of the related art, can always obtain correct search results even when word concatenation is performed, and has low power consumption and high search throughput. It is in.
[0032]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides an associative memory having a word connection function,
A CAM array having a plurality of CAM blocks, and a priority encoder that outputs an address of a word in which a match is detected according to a predetermined priority order;
Each of the CAM blocks includes a plurality of one-word circuits,
Each of the one-word circuits stores data of one word, performs a match search between the stored data and search data, and outputs a search result, and a CAM word of the one-word circuit. Means for outputting a signal obtained by taking the logic of the search result output from the CAM block and a match flag output from the corresponding one-word circuit of the preceding CAM block, and a signal output from the first means as a match flag A second means for outputting a match flag output from this register to a corresponding one-word circuit of a CAM block at a subsequent stage, and a match flag output from the register to the priority encoder And a third means.
[0033]
Further, according to the present invention, the first means outputs the search result output from the CAM word of the one-word circuit as it is, or outputs the search result output from the CAM word of the one-word circuit and the CAM block of the preceding stage. Means for controlling whether to output a signal obtained by taking a logic with a match flag output from a corresponding one-word circuit,
The register includes means for controlling whether to latch a signal output from the first means,
The second means includes means for controlling whether or not to output a match flag output from the register to a corresponding one-word circuit of the subsequent CAM block.
The third means provides an associative memory, characterized by comprising means for controlling whether or not to output a match flag output from the register to the priority encoder.
[0034]
Here, it is preferable that the CAM words are in a matching state in an initial state.
[0035]
Further, when the entry data is formed by connecting a plurality of words, before the search, the data of each one word constituting the entry data is registered in the one-word circuit of the corresponding CAM block, and at the time of the search, A match search between each one-word data forming the entry data and the corresponding one-word data of the search data is performed in the CAM block corresponding to each one-word data forming the entry data. It is preferable to perform only one step.
[0036]
In addition, it is preferable to search for entry data in which all data of one word constituting the entry data and data of one word of the search data corresponding thereto match.
[0037]
In addition, it is preferable to perform a search for entry data in which a part of one word of the entry data and a part of one word of the search data corresponding thereto match.
[0038]
When sequentially searching one word of data registered in one word circuit of each of the preceding and succeeding CAM blocks that are not adjacent to each other, a CAM located between the preceding and succeeding CAM blocks where no match search is performed. In one word circuit of the block, it is preferable that a match flag output from a corresponding one-word circuit of the preceding CAM block is transmitted to a corresponding one-word circuit of the following CAM block.
[0039]
Prior to the search, the entry data included in the plurality of independent tables is registered in the one-word circuit of the corresponding CAM block, and at the time of the search, the entry data corresponding to the table to be searched is registered in the CAM block. Preferably, only a match search is performed.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an associative memory of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
[0041]
FIG. 1 is a schematic configuration diagram of an embodiment of an associative memory according to the present invention. An associative memory (hereinafter, referred to as a CAM) 10 shown in FIG. 1 can be set to form one entry by one word or by connecting two or four words (up to a maximum of four words can be connected). , A CAM array 12, and a priority encoder 14.
[0042]
In the CAM 10, the CAM array 12 includes four CAM blocks CB_0, CB_1, CB_2, and CB_3 each having N (N = 1, 2, 3,...) Words. That is, the entire CAM array 12 has 4N words. Therefore, in the CAM 10, the total number of entries when one entry is composed of one word, two words, and four words is 4N, 2N, and N, respectively.
[0043]
It should be noted that the CAM array 12 only needs to include CAM blocks of at least the maximum number of connected words. In the case of the present embodiment, four or more CAM blocks may be provided.
[0044]
The address of each word in the CAM array 12 is specified by 4n, 4n + 1, 4n + 2, 4n + 3 (n = 0, 1, 2,...). In the present embodiment, the CAM block CB_0 includes N words specified by the address 4n (0, 4, 8,...), And similarly, the CAM blocks CB_1, CB_2, and CB_3 each have the address 4n + 1 (1, 5, 9). ,...), 4n + 2 (2, 6, 10,...), And 4n + 3 (3, 7, 11,...).
[0045]
Each CAM block includes one word circuit 16 for N words and a block driver 18. The details of the one-word circuit 16 will be described later.
[0046]
The block driver 18 outputs a signal KEYD [m−1: 0], a signal SLE [3: 0], a signal ACIEN [3: 0], a signal MFLT [3: 0], a signal MFOE [3: 0], and a signal ACOEN [ 3: 0], all one-word circuits 16 included in the corresponding CAM blocks are driven. The block driver 18 includes a search bit line driver 20 and four buffers 22.
[0047]
The signals SLE [0], ACIEN [0], MFLT [0], MFOE [0] and ACOEN [0] are input to the search bit line driver 20 and the four buffers 22 of the block driver 18 of the CAM block CB_0. Have been. Similarly, the search bit line driver 20 and the four buffers 22 of the block driver 18 of the CAM blocks CB_3, CB_2, and CB_1 respectively have corresponding signals SLE [3: 1], ACIEN [3: 1], and MFLT [3 : 1], MFOE [3: 1] and ACOEN [3: 1].
[0048]
Also, a signal KEYD [m-1: 0], which is search data, is commonly input to the search bit line driver 20 of the block driver 18 of each CAM block.
[0049]
The search bit line driver 20 of each CAM block outputs the search bit line pair SL [of each of the CAM blocks CB_3, CB_2, CB_1, and CB_0 according to the state of the corresponding bit of the search bit line enable signal SLE [3: 0]. m-1: 0] and SLN [m-1: 0]. The m pairs of search bit lines driven by the search bit line driver 20 are connected to m-bit CAM cells constituting a CAM word of a one-word circuit described later. The corresponding bits of the signals ACIEN [3: 0], MFLT [3: 0], MFOE [3: 0] and ACOEN [3: 0] driven by the four buffers 22 are respectively associated with the corresponding CAMs. It is commonly connected to all the one-word circuits 16 included in the blocks CB_3, CB_2, CB_1, and CB_0.
[0050]
In the CAM 10, the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] are driven only in the CAM block to be searched specified by the signal SLE [3: 0], and a match search is performed. Is Accordingly, when one entry is formed by connecting a plurality of words, the drive of the search bit line pair SL [m-1: 0] and SLN [m-1: 0] of the CAM block not to be searched is suppressed. The power consumption can be reduced accordingly.
[0051]
Finally, the priority encoder 14 sequentially encodes the addresses of the words for which a match is detected according to a predetermined priority order, and outputs the encoded words as the highest priority match address HMA. The priority encoder 14 receives the match flag outputs MFO of all the words, and outputs them sequentially from the address of the word with the highest priority. When a plurality of words are linked to form one entry, an address of a word representing the entry is output.
[0052]
Although omitted to avoid complication of the drawing, the CAM 10 naturally includes circuits such as a decoder, a data bit line driver, and a sense amplifier.
[0053]
Next, the one-word circuit 16 will be described.
[0054]
FIG. 2 is a schematic configuration diagram of one embodiment of a one-word circuit. The one-word circuit 16 shown in FIG. 1 includes a CAM word 24 and a word logic 26.
[0055]
The CAM word 24 stores one word of data, performs a match search between the stored data and the search data, and outputs a search result. The CAM word 24 includes an m-bit CAM cell 28, a match sense circuit 30.
[0056]
FIG. 3 is a configuration circuit diagram of one embodiment of the CAM cell. A CAM cell 28 shown in FIG. 1 is a CAM cell of a mismatch detection type, and has a storage circuit 32 for storing 1-bit data, a 1-bit data stored in the storage circuit 32, and a corresponding search bit line. A comparison circuit 34 is provided for comparing search data driven on the pair SL and SLN with each other and outputting the detection result on a match line ML.
[0057]
The storage circuit 32 has an SRAM configuration, and includes two inverters 36 and 38 whose one output is input to the other input, a data bit line pair BL and BLN, and inputs of the two inverters 36 and 38, respectively. There are provided two N-type MOS transistors (hereinafter, referred to as NMOS) 40 and 42 whose gates are commonly connected to the word line WL. Since the configuration of the SRAM is conventionally known, its description is omitted here.
[0058]
As the storage circuit 32, any conventionally known memory cells can be used as long as they store 1-bit data. In addition, any conventionally known circuit can be used as a circuit for writing / reading data in the storage circuit 32.
[0059]
The comparison circuit 34 includes four NMOSs 44, 46, 48, and 50. The NMOSs 44 and 46 are connected in series between the match line ML and the ground, and their gates are connected to the data D and the search bit line SLN of the storage circuit 32, respectively. The NMOSs 48 and 50 are also connected in series between the match line ML and the ground, and their gates are connected to the inverted data DN and the search bit line SL of the storage circuit 32, respectively.
[0060]
FIG. 4 is a configuration circuit diagram of an embodiment of the coincidence sense circuit. The match sense circuit 30 shown in the figure is connected in parallel between two inverters 52 and 54 connected in series between the match line ML and the match sense output line MT, and between the power supply and the match line ML. Two P-type MOS transistors (hereinafter, referred to as PMOS) 56 and 58 are provided. The gates of the PMOSs 56 and 58 are connected to the signal MLPCN and the output of the inverter 52, respectively.
[0061]
In the one-word circuit 16, both the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] are discharged in advance to "00" before the search. Further, the signal MLPCN is set to “L (= 0: low level)”, and the match line ML is precharged via the PMOS 56 of the match sense circuit 30.
[0062]
At this time, both the NMOSs 46 and 50 of the comparison circuit 34 of the CAM cell 28 are off, and the connection between the match line ML and the ground is non-conductive. Further, the output of the inverter 52 becomes “L”, the PMOS 58 is turned on, and the match line ML is precharged through both the PMOSs 56 and 58. Further, the output of the inverter 54, that is, the signal (match sense output) output on the match sense output line MT is in the 'H' (= 1: high level) state.
[0063]
At the time of the search, the signal MLPCN is set to “H”, and the PMOS 56 is turned off. Further, the search bit line pair SL, SLN is driven to one of '10', '01', '00' according to the search data (data 1, data 0, don't care).
[0064]
When the search bit line pair SL, SLN is driven to '10' or '01', in each CAM cell 28, if the search data and the stored data are the same, one of the NMOSs 44, 46 , And one of the NMOSs 48 and 50 is in the off state, and the match line ML is held at the “H” state as it is precharged. Therefore, the match line ML is kept at “H” only when all the matches are detected in all the CAM cells 28.
[0065]
On the other hand, if the stored data and the search data are different even in one CAM cell 28, both of the NMOSs 44 and 46 or both of the NMOSs 48 and 50 are turned on, and the match line ML is discharged and L '.
[0066]
When the search bit line pair SL, SLN is driven to '00', the NMOSs 46, 50 are turned off in the CAM cell 28, so that the match line ML is precharged regardless of the stored data. The state is maintained as “H”.
[0067]
The search result output on the match line ML is amplified and output by the match sense circuit 30. That is, when the match line ML is in the “H” state while being precharged, the match sense output MT is held in the “H” state as described above. On the other hand, when the match line ML is discharged and becomes "L", the output of the inverter 52 becomes "H", the PMOS 58 is turned off, and the match sense output MT becomes "L".
[0068]
The configuration of the CAM cell 28 is not limited at all, and any conventionally known one can be used regardless of whether it is a mismatch detection type or a match detection type. In the CAM 10, the use of a mismatch detection type CAM cell causes the match sense output to be "H", which is a match state in the initial state. Therefore, as described later, between the CAM blocks in the preceding and subsequent stages that are not adjacent to each other, When performing a partial search, a search result of a preceding CAM block in a CAM block that is not searched and located between them can be transmitted to a subsequent CAM block.
[0069]
Subsequently, in the one-word circuit 24, the word logic 26 holds, as a match flag, a search result of itself or an operation result obtained by calculating a logical product of the search result of itself and the match flag of the preceding one-word circuit 16. A match flag register 60, an OR-AND composite gate 62 and an OR gate 64 forming an AND chain for connecting match flags of a plurality of words, and an AND gate 66 for outputting a match flag of an entry.
[0070]
The signal ACI and the signal ACIEN are input to the input terminals of the OR gate constituting the OR-AND composite gate 62, and the coincidence sense output from the coincidence sense circuit 30 is input to the input terminals of the AND gate. The output of the OR-AND composite gate 62 is input to the match flag register 60. The match flag register 60 latches the signal output from the OR-AND composite gate 62 under the control of the signal MFLT.
[0071]
The output of the match flag register 60 is input to one input terminal of the OR gate 64 and one input terminal of the AND gate 66. The signal ACOEN is input to the other input terminal of the OR gate 64, and the signal ACO is output from the OR gate 64. A signal MFOE is input to the other input terminal of the AND gate 66, and a signal MFO is output from the AND gate 66.
[0072]
As shown in FIG. 1, the signal MFO output from all the one-word circuits 16 of all the CAM blocks CB_3, CB_2, CB_1 and CB_0 is input to the priority encoder 14. The signal ACI input to each one-word circuit 16 of the CAM block CB_0 is connected to a power supply, and the signal ACO output from each one-word circuit 16 of each of the CAM blocks CB_0, CB_1, and CB_2 is a signal ACI. The signals are input to the corresponding one-word circuits 16 of the subsequent CAM blocks CB_1, CB_2, and CB_3.
[0073]
Here, the signal ACI is an AND chain input. When a plurality of words are connected to form one entry, the AND chain output (signal ACO) of the corresponding one-word circuit 16 of the preceding CAM block to be connected is input. Is done. Note that the signal ACI input to the one-word circuit 16 of the first-stage CAM block CB_0 is always at “H”. The signal ACIEN [3: 0] indicates that the ACI input is enabled, "L" indicates that the ACI input is valid, and "H" indicates that the ACI input is invalid.
[0074]
The signal MFLT [3: 0] is a latch control signal for the match flag register 60, and "L" indicates that the match flag register 60 is in the through state, and "H" indicates that the match flag register 60 is in the hold state.
[0075]
Signal MFO is an entry match flag output. Further, the signal MFOE [3: 0] is a match flag output enable, “L” indicates that the match flag output MFO is invalid (in this embodiment, the signal MFO is fixed at “L”), and “H” indicates the match flag output MFO. Is valid.
[0076]
The signal ACO is an AND chain output, and is input as a signal ACI to the corresponding one-word circuit 16 of the connected CAM block at the subsequent stage. The signal ACOEN [3: 0] is an AND chain output enable, and “L” indicates that the AND chain output (signal ACO) is output to the corresponding one-word circuit 16 of the subsequent CAM block. “H” indicates that the AND chain output (signal ACO) is not output to the corresponding one-word circuit 16 of the subsequent CAM block (in the case of the present embodiment, the signal ACO is fixed to “H”).
[0077]
Signal KEYD [m-1: 0] is search data. Further, the signal SLE [3: 0] is a search bit line pair enable and indicates the CAM block 22 to be searched. 'L' indicates that the search bit line pair SL, SLN is disabled, and 'H' indicates that the search bit line pair SL, SLN is enabled. In the signal SLE [3: 0], the search data (signal KEYD [m−1: 0]) is driven only to the search bit line pair SL and SLN of the CAM block corresponding to the bit of “H”.
[0078]
In the one-word circuit 16, as described above, a match sense output is output from the match sense circuit 30 of the CAM word 24 as a result of the search. From the OR-AND composite gate 62 of the word logic 26, when the signal ACien is “H”, the match sense output MT output from the match sense circuit 30 is output as it is, and when the signal ACien is “L”, Is ANDed with the match sense output MT output from the match sense circuit 30 and the signal ACI, and the operation result is output.
[0079]
The signal output from OR-AND composite gate 62 is latched in match flag register 60 under the control of signal MFLT. In the case of the present embodiment, in the CAM block to be searched, the signal MFLT is set to “H” after being set to “L” for a predetermined period, and the output of the OR-AND composite gate 62 is latched by the match flag register 60. . On the other hand, in the CAM blocks not to be searched, the signal MFLT is always set to “H”, and the data of the match flag register 60 is not changed.
[0080]
The OR gate 64 always outputs "H" as the signal ACO when the signal ACOEN is "H", and outputs the match flag latched in the match flag register 60 when the signal ACOEN is "L". Is output. When the one-word circuit 16 of the CAM block is not connected to the one-word circuit 16 of the preceding CAM block, the search result of the one-word circuit 16 is latched in the match flag register 60. A signal that takes the logic of the match flag of the one-word circuit and the search result of the one-word circuit is latched. When the one-word circuit 16 of the CAM block is not connected to the one-word circuit 16 of the subsequent CAM block, the signal ACOEN is set to “H” and the signal ACO is fixed to “H”, so that the power generated by the OR gate 64 is reduced. Consumption can be reduced.
[0081]
When the signal MFOE is “H”, the match flag latched in the match flag register 60 is output from the AND gate 66, and when the signal MFOE is “L”, the match flag is always “L”. 'Is output. When a plurality of words are linked to form one entry, the power consumption by the AND gate 66 is reduced by setting the signal MFOE of the CAM block not to be searched to “L” and fixing the signal MFO to “L”. Can be.
[0082]
Further, an OR-AND composite gate 62, an OR gate 64, and an AND gate 66 are provided, and the control of the signal ACIEN, the signal ACOEN, and the signal MFOE enables and disables the signal ACI input, the signal ACO output, and the signal MFO output. By performing the control, a match search can be performed without initializing the match flag register 60. As a result, a step for initialization can be omitted, and the search throughput can be improved.
[0083]
Hereinafter, the operation of the CAM 10 will be described with a specific example.
[0084]
(1) Retrieval of entry data formed by linking four words (retrieval of entry data that matches all four words)
[0085]
When four words are concatenated to form the entry data, the signal ACOEN [3: 0] = '0000' is set. As a result, the AND chain output (signal ACO) of all the one-word circuits 16 of the CAM blocks CB_0, CB_1, CB_2, and CB_3 becomes valid, and one entry is composed of four words.
[0086]
Before the search, each entry data is registered in the CAM array 12. For example, when the 4-word width entry data shown in FIG. 16 is used, as shown in FIG. 5, the data of the attributes I, II, III, and IV of each entry are respectively stored in the CAM blocks CB_0, CB_1, CB_2, and CB_3. be registered. At the time of search, a total of four searches (AND search) are performed using search data of one word width corresponding to the attributes I, II, III, and IV, respectively.
[0087]
In the first search, the signal KEYD [m-1: 0] = search data of one word width corresponding to the attribute I, the signal SLE [3: 0] = '0001', and the signal ACIEN [3: 0] = 'XXXX ', The signal MFLT [3: 0] =' 1110 ', and the signal MFOE [3: 0] =' 0001 '. 'X' means don't care and is set to either '0' or '1' (which may be set to either '0' or '1').
[0088]
That is, only the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] of the CAM block CB_0 in which the data of the attribute I is registered are searched data (signals KEYD [m-1: 0] ]).
[0089]
Further, only the match flag register 60 of the CAM block CB_0 is set to the through state, and its data is updated. The match flag registers 60 of the CAM blocks CB_1, CB_2, and CB_3 are all held.
[0090]
Only the match flag output (signal MFO) of the CAM block CB_0 is enabled and input to the priority encoder 14. The output of the match flags of the other CAM blocks CB_1, CB_2, and CB_3 are disabled and all are fixed to 'L', that is, the mismatch is detected and input to the priority encoder 14.
[0091]
Since the signal ACI input to the one-word circuit 16 of the CAM block CB_0 is always “H”, the OR-AND composite gate 62 outputs the signal ACI from the coincidence sense circuit 30 regardless of the state of the signal ACIEN. A match sense output is output.
[0092]
That is, the first search is performed only in the CAM block CB_0 in which the data of the attribute I is registered, and the match flag output (signal MFO) output from the CAM block CB_0 is input to the priority encoder 14. By operating the priority encoder 14 in this state, it is possible to output the HMA of the entry for which a match has been detected in the attribute I portion.
[0093]
The AND chain output (signal ACO) of the CAM block CB_0 is input to the subsequent CAM block CB_1 as an AND chain input (signal ACI).
[0094]
Subsequently, in the second search, the signal KEYD [m-1: 0] = search data of one word width corresponding to the attribute II, the signal SLE [3: 0] = '0010', and the signal ACien [3: 0] = 'XX0X', signal MFLT [3: 0] = '1101', and signal MFOE [3: 0] = '0010'.
[0095]
That is, only the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] of the CAM block CB_1 in which the data of the attribute II are registered are search data (signals KEYD [m-1: 0]). ]). Further, only the match flag register 60 of the CAM block CB_1 is set to the through state, and its data is updated. Only the match flag output (signal MFO) of the CAM block CB_1 is enabled and input to the priority encoder 14. Only the OR-AND composite gate 62 of the CAM block CB_1 is enabled, and the AND chain output (signal ACO) output from the preceding CAM block CB_0 and the coincidence sense output from the coincidence sense circuit 30 of the CAM block CB_1. The output is ANDed with the output.
[0096]
That is, the second search is performed only in the CAM block CB_1 in which the data of the attribute II is registered, and the match flag output (signal MFO) output from the CAM block CB_1, that is, the CAM block CB_1 and the CAM block CB_1 The result of the AND search is input to the priority encoder 14. Similarly, by operating the priority encoder 14 in this state, it is possible to output the HMA of the entry for which a match is detected in both the attributes I and II.
[0097]
The AND chain output (signal ACO) of the CAM block CB_1 is input to the subsequent CAM block CB_2 as an AND chain input (signal ACI).
[0098]
Similarly, in the third search, the signal KEYD [m-1: 0] = search data of one word width corresponding to the attribute III, the signal SLE [3: 0] = '0100', and the signal ACien [3: 0] = 'X0XX', signal MFLT [3: 0] = '1011', and signal MFOE [3: 0] = '0100'.
[0099]
That is, the third search is performed only in the CAM block CB_2 in which the data of the attribute III is registered, and the match flag output (signal MFO) output from the CAM block CB_2, that is, the AND of the CAM blocks CB_0, CB_1 and CB_2 The result of the search is input to the priority encoder 14. Similarly, if the priority encoder 14 is operated in this state, it is possible to output the HMA of the entry in which a match is detected in all of the attributes I, II, and III.
[0100]
In the fourth search, the signal KEYD [m-1: 0] = search data of one word width corresponding to the attribute IV, the signal SLE [3: 0] = '1000', and the signal ACien [3: 0] = '0XXX', signal MFLT [3: 0] = '0111', and signal MFOE [3: 0] = '1000'.
[0101]
That is, the fourth search is performed only in the CAM block CB_3 in which the data of the attribute IV is registered, and the match flag output (signal MFO) output from the CAM block CB_3, that is, the CAM blocks CB_0, CB_1, CB_2 and CB_3 Is input to the priority encoder 14. Similarly, by operating the priority encoder 14 in this state, it is possible to output the HMA of the entry for which a match is detected in all of the attributes I, II, III, and IV.
[0102]
As described above, when a search is performed on entry data formed by linking four words, data for one word of each attribute I, II, III, and IV of the entry data and the search data The conventional CAM can be realized by properly associating each word of data (which one-word width of the 4-word search data is to be used) and performing a search only in the CAM block to be searched. , It is possible to prevent output of an erroneous search result.
[0103]
Further, in the above embodiment, the signal MFO is output at the time of searching for each of the attributes I, II, III, and IV. Therefore, by operating the priority encoder 14 after searching for each attribute, it is possible to output the intermediate result of the search. You can also. If an intermediate result is unnecessary, the signal MFOE is set to “L” and the output of the signal MFO is fixed to “L”, so that power consumption can be reduced. In this case, there is no need to operate the priority encoder 14. The same applies to the following search examples.
[0104]
(2) Search for entry data formed by linking two words (search for matching entry data in both words)
[0105]
When two words are concatenated to form entry data, the signal ACOEN [3: 0] is set to '1010'. As a result, the AND chain output (signal ACO) of the one-word circuit 16 of the CAM blocks CB_0 and CB_2 is valid, and the AND chain output of the one-word circuit 16 of the CAM blocks CB_1 and CB_3 is fixed at “H”. CB_0 and CB_1 constitute one entry, and CAM blocks CB_2 and CB_3 constitute one entry.
[0106]
For example, when the entry data having a two-word width shown in FIG. 6 is used, as shown in FIG. 7, the data of the attribute I of each entry is alternately registered in the CAM blocks CB_0 and CB_2, respectively, and the attribute II of each entry is registered. Are alternately registered in the CAM blocks CB_1 and CB_3, respectively. At the time of search, a total of two searches (AND search) are performed using, for example, search data of one word width corresponding to the attributes I and II, respectively.
[0107]
In the first search, the signal KEYD [m-1: 0] = search data of one word width corresponding to the attribute I, the signal SLE [3: 0] = '0101', and the signal ACIEN [3: 0] = 'X1XX'', The signal MFLT [3: 0] =' 1010 'and the signal MFOE [3: 0] =' 0101 '.
[0108]
That is, the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] of the CAM blocks CB_0 and CB_2 in which the data of the attribute I are registered are simultaneously searched data (signal KEYD [m-1 : 0]). Also, the match flag registers 60 of the CAM blocks CB_0 and CB_2 are set to the through state, and the data is updated. The match flag output (signal MFO) of the CAM blocks CB_0 and CB_2 is enabled and input to the priority encoder 14. Further, since the signal ACI input to the CAM blocks CB_0 and CB_2 is “H”, the OR-AND composite gate 62 of the CAM blocks CB_0 and CB_2 outputs its own coincidence sense circuit 30 regardless of the state of the signal ACIEN. Is output as a match sense output.
[0109]
That is, the first search is performed only in the CAM blocks CB_0 and CB_2 in which the data of the attribute I is registered, and the match flag output (signal MFO) output from the CAM blocks CB_0 and CB_2 is input to the priority encoder 14. You. By operating the priority encoder 14 in this state, it is possible to cause the priority encoder 14 to output the HMA of the entry for which a match is detected in the attribute I portion.
[0110]
The AND chain outputs (signal ACO) of the CAM blocks CB_0 and CB_2 are input to the CAM blocks CB_1 and CB_3 as AND chain inputs (signal ACI), respectively.
[0111]
In the second search, the signal KEYD [m-1: 0] = search data of one word width corresponding to the attribute II, the signal SLE [3: 0] = '1010', and the signal ACIEN [3: 0] = '0X0X ', The signal MFLT [3: 0] =' 0101 ', and the signal MFOE [3: 0] =' 1010 '.
[0112]
That is, the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] of the CAM blocks CB_1 and CAM3 in which the data of the attribute II are registered are simultaneously searched data (signal KEYD [m-1 : 0]). Further, the match flag registers 60 of the CAM blocks CB_1 and CB_3 are set to the through state, and the data is updated. The match flag output (signal MFO) of the CAM blocks CB_1 and CB_3 is enabled and input to the priority encoder 14. In the CAM block CB_1, the AND of the AND chain output (signal ACO) output from the preceding CAM block CB_0 and the match sense output output from the match sense circuit 30 of the CAM block CB_1 is output. . Similarly, in the CAM block CB_3, the AND of the AND chain output output from the preceding CAM block CB_2 and the match sense output output from the match sense circuit 30 of the CAM block CB_3 is output.
[0113]
That is, the second search is performed only in the CAM blocks CB_1 and CB_3 in which the data of the attribute II is registered, and the match flag output (signal MFO) output from the CAM blocks CB_1 and CB_3, that is, the CAM blocks CB_0 and CB_1 AND search results of the CAM blocks CB_2 and CB_3 are input to the priority encoder 14. By operating the priority encoder 14 in this state, it is possible to cause the priority encoder 14 to output the HMA of the entry for which a match is detected in both the attributes I and II.
[0114]
(3) Search for 1-word entry data (no word concatenation)
[0115]
If word concatenation is not performed, the signal ACOEN [3: 0] is set to '1111'. As a result, the AND chain output (signal ACO) of the one-word circuit of all the CAM blocks CB_0, CB_1, CB_2, and CB_3 is fixed to “H”, which is invalid, and the CAM blocks CB_0, CB_1, CB_2, CB_3 One entry is configured.
[0116]
For example, when the one-word-width entry data shown in FIG. 8 is used, as shown in FIG. 9, the data of each entry data is sequentially registered in the CAM blocks CB_0, CB_1, CB_2, and CB_3. At the time of search, search is performed in all CAM blocks CB_0, CB_1, CB2, and CB_3 simultaneously using search data of one word width.
[0117]
In the search, the signal KEYD [m-1: 0] = 1 search data having a word width, the signal SLE [3: 0] = '1111', the signal ACIEN [3: 0] = 'XXXX', and the signal MFLT [3: 0]. ] = '0000' and the signal MFOE [3: 0] = '1111'.
[0118]
That is, the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] of all the CAM blocks CB_0, CB_1, CB_2 and CB_3 are simultaneously searched data (signal KEYD [m-1: 0]). Driven according to). Further, the match flag registers 60 of all the CAM blocks CB_0, CB_1, CB_2, and CB_3 are set to the through state, and the data is updated. The match flag outputs (signals MFO) of all the CAM blocks CB_0, CB_1, CB_2, and CB_3 are enabled and input to the priority encoder 14. Also, since the signal ACI input to all the CAM blocks CB_0, CB_1, CB_2 and CB_3 is 'H', the OR-AND composite gates 62 of all the CAM blocks output their own signals regardless of the state of the signal ACIEN. Is output from the match sense circuit 30.
[0119]
That is, the search is performed simultaneously for all the CAM blocks, and the match flag outputs (signals MFO) output from all the CAM blocks are input to the priority encoder 14. By operating the priority encoder 14 in this state, it is possible to output the HMA of the entry for which a match has been detected.
[0120]
(4) Partial search of entry data formed by linking four words (search for entry data in which a part of four words matches)
[0121]
As described above, when the entry data is formed by connecting four words, the signal ACOEN [3: 0] = '0000' is set. For example, a case will be described where a partial search of adjacent attributes II and III is performed in the CAM in which the entry data shown in FIG. 5 is registered.
[0122]
In the first search, the signal KEYD [m-1: 0] = search data of one word width corresponding to the attribute II, the signal SLE [3: 0] = '0010', and the signal ACIEN [3: 0] = 'XX1X ', The signal MFLT [3: 0] =' 1101 'and the signal MFOE [3: 0] =' 0010 '.
[0123]
That is, only the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] of the CAM block CB_1 in which the data of the attribute II are registered are search data (signals KEYD [m-1: 0]). ]). Further, only the match flag register 60 of the CAM block CB_1 is set to the through state, and its data is updated. The match flag output (signal MFO) of the CAM block CB_1 is enabled and input to the priority encoder 14. In addition, the OR-AND composite gate 62 of the CAM block CB_1 outputs a match sense output output from its own match sense circuit 30 regardless of the state of the signal ACI. That is, the CAM block CB_1 does not reflect the search result of the preceding CAM block CB_0.
[0124]
That is, the first search is performed only in the CAM block CB_1 in which the data of the attribute II is registered, and the match flag output (signal MFO) output from the CAM block CB_1 is input to the priority encoder 14. By operating the priority encoder 14 in this state, it is possible to cause the priority encoder 14 to output the HMA of the entry for which a match has been detected in the attribute II part.
[0125]
The AND chain output (signal ACO) of the CAM block CB_1 is input to the subsequent CAM block CB_2 as an AND chain input (signal ACI).
[0126]
In the second search, the signal KEYD [m-1: 0] = search data of one word width corresponding to the attribute III, the signal SLE [3: 0] = '0100', and the signal ACIEN [3: 0] = 'X0XX'', The signal MFLT [3: 0] =' 1011 'and the signal MFOE [3: 0] =' 0100 '.
[0127]
That is, only the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] of the CAM block CB_2 in which the data of the attribute III are registered are searched data (signals KEYD [m-1: 0] ]). Further, the match flag register 60 of the CAM block CB_2 is set to the through state, and the data is updated. Only the match flag output (signal MFO) of the CAM block CB_2 is enabled and input to the priority encoder 14. In the CAM block CB_2, the AND of the AND chain output (signal ACO) output from the preceding CAM block CB_1 and the match sense output output from the match sense circuit 30 of the CAM block CB_2 is output. .
[0128]
That is, the second search is performed only in the CAM block CB_2 in which the data of the attribute III is registered, and the match flag output (signal MFO) output from the CAM block CB_2, that is, the AND search of the CAM blocks CB_1 and CB_2 The result is input to the priority encoder 14. By operating the priority encoder 14 in this state, it is possible to output the HMA of the entry for which a match is detected in both the attributes II and III.
[0129]
Next, a case will be described in which, for example, a partial search of non-adjacent attributes II and IV is performed in the CAM in which the entry data shown in FIG. 5 is registered.
[0130]
The first search is the same as the search for the adjacent attributes II and III.
[0131]
In the second search, the signal KEYD [m-1: 0] = search data of one word width corresponding to the attribute IV, the signal SLE [3: 0] = '1000', and the signal ACIEN [3: 0] = '00XX ', The signal MFLT [3: 0] =' 0011 ', and the signal MFOE [3: 0] =' 1000 '.
[0132]
That is, only the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] of the CAM block CB_3 in which the data of the attribute IV are registered are searched data (signals KEYD [m-1: 0]). ]). Also, the match flag registers 60 of the CAM blocks CB_2 and CB_3 are set to the through state, and the data is updated. Also, only the match flag output (signal MFO) of the CAM block CB_3 is enabled and input to the priority encoder 14. In the CAM blocks CB_2 and CB_3, the AND of the AND chain outputs (signals ACO) output from the preceding CAM blocks CB_1 and CB_2 and the coincidence sense output output from the coincidence sense circuit 30 of itself is calculated. Output.
[0133]
In the CAM block CB_2, since the search bit line pair SL and SLN are not driven, the coincidence sense output is “H” in the initial state, and the OR-AND composite gate 62 outputs the signal ACI, that is, the AND of the CAM device CB_1. The chain output is output. Therefore, the AND chain output output from the CAM block CB_1 is input to the CAM block CB_3 via the CAM block CB_2, and the logical product of the AND chain output output from the CAM block CB_1 and the own match sense output is obtained. Is output.
[0134]
That is, the second search is performed only in the CAM block CB_3 in which the data of the attribute IV is registered, and the match flag output (signal MFO) output from the CAM block CB_3, that is, the AND search of the CAM blocks CB_1 and CB_3 The result is input to the priority encoder 14. By operating the priority encoder 14 in this state, it is possible to output the HMA of the entry for which a match is detected in both the attributes II and IV.
[0135]
As described above, the CAM 10 does not need to perform a dummy search unlike the conventional CAM even when performing a partial search of data between CAM blocks that are not adjacent to each other, thereby preventing a decrease in search throughput.
[0136]
(5) Search in the case where entry data formed by linking two words is registered in two independent tables (search for entry data that matches in both two words)
[0137]
As described above, when two words are concatenated to form entry data, the signal ACOEN [3: 0] is set to '1010'. As a result, the AND chain output (signal ACO) of the one-word circuit of the CAM blocks CB_0 and CB_2 becomes valid, and one entry is formed by the CAM blocks CB_0 and CB_1, and one entry is formed by the CAM blocks CB_2 and CB_3.
[0138]
For example, when using two-word-width entry data included in the two tables 1 and 2 shown in FIG. 10, respectively, as shown in FIG. The data is registered in the CAM blocks CB_0 and CB_1, and the data of the attributes I and II of each entry of the table 2 are registered in the CAM blocks CB_2 and CB_3, respectively. At the time of the search, a total of two searches (AND search) are performed on the table 1, for example, in the order of the attributes I and II, using the corresponding one-word-width search data. The same applies to table 2.
[0139]
Hereinafter, a case of searching for an entry in Table 2 will be described.
[0140]
In the first search, the signal KEYD [m-1: 0] = search data of one word width corresponding to the attribute I, the signal SLE [3: 0] = '0100', and the signal ACIEN [3: 0] = 'X1XX ', The signal MFLT [3: 0] =' 1011 'and the signal MFOE [3: 0] =' 0100 '.
[0141]
That is, only the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] of the CAM block CB_2 in which the data of the attribute I of the table 2 are registered are searched data (signal KEYD [m- 1: 0]). Further, the match flag register 60 of the CAM block CB_2 is set to the through state, and the data is updated. The match flag output (signal MFO) of the CAM block CB_2 is enabled and input to the priority encoder 14. In addition, the OR-AND composite gate 62 of the CAM block CB_2 outputs a match sense output from its own match sense circuit 30 irrespective of the signal ACI.
[0142]
That is, the first search is performed only in the CAM block CB_2 in which the data of the attribute I of Table 2 is registered, and the match flag output (signal MFO) output from the CAM block CB_2 is input to the priority encoder 14. . By operating the priority encoder 14 in this state, it is possible to cause the priority encoder 14 to output the HMA of the entry for which a match is detected in the attribute I portion of the table 2.
[0143]
The AND chain output (signal ACO) of the CAM block CB_2 is input to the subsequent CAM block CB_3 as an AND chain input (signal ACI).
[0144]
In the second search, the signal KEYD [m−1: 0] = search data of one word width corresponding to the attribute II, the signal SLE [3: 0] = “1000”, and the signal ACIEN [3: 0] = “0XXX”. ', The signal MFLT [3: 0] =' 0111 'and the signal MFOE [3: 0] =' 1000 '.
[0145]
That is, only the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] of the CAM block CB_3 in which the data of the attribute II of Table 2 are registered are searched data (signal KEYD [m- 1: 0]). Further, the match flag register 60 of the CAM block CB_3 is set to the through state, and its data is updated. The match flag output (signal MFO) of the CAM block CB_3 is enabled and input to the priority encoder 14. From the OR-AND composite gate 62 of the CAM block CB_3, the logical product of the AND chain output output from the preceding CAM block CB_2 and the match sense output output from the match sense circuit 30 of the CAM block CB_3 is obtained. Output.
[0146]
That is, the second search is performed only in the CAM block CB_3 in which the data of the attribute II of Table 2 is registered, and the match flag output (signal MFO) output from the CAM block CB_3, that is, the CAM blocks CB_2 and CB_3 The AND search result is input to the priority encoder 14. By operating the priority encoder 14 in this state, it is possible to cause the priority encoder 14 to output the HMA of the entry for which a match is detected in both the attributes I and II of Table 2.
[0147]
(6) Search when one word of entry data is registered in four independent tables (no word concatenation)
[0148]
When word concatenation is not performed, the signal ACOEN [3: 0] is set to '1111' as described above. As a result, the AND chain output (signal ACO) of the one-word circuit of all the CAM blocks CB_0, CB_1, CB_2, and CB_3 is fixed to “H”, which is invalid, and the CAM blocks CB_0, CB_1, CB_2, CB_3 One entry is configured.
[0149]
For example, when using one-word-width entry data included in each of the four tables 1, 2, 3, and 4 shown in FIG. 12, as shown in FIG. 13, each entry data of the table 1 is registered in the CAM block CB_0. Then, similarly, each entry data of the tables 2, 3, and 4 is registered in the CAM blocks CB_1, CB_2, and CB3, respectively. At the time of search, a search is performed on the table to be searched using search data having a width of one word.
[0150]
Hereinafter, a case of searching for an entry in Table 3 will be described.
[0151]
In the search, the signal KEYD [m-1: 0] = 1 search data having a word width, the signal SLE [3: 0] = '0100', the signal ACIEN [3: 0] = 'X1XX', and the signal MFLT [3: 0]. ] = '1011' and the signal MFOE [3: 0] = '0100'.
[0152]
That is, only the search bit line pairs SL [m-1: 0] and SLN [m-1: 0] of the CAM block CB_2 in which the entry data of the table 3 is registered are searched data (signals KEYD [m-1: 0]). Further, the match flag register 60 of the CAM block CB_2 is set to the through state, and the data is updated. The match flag output (signal MFO) of the CAM block CB_2 is enabled and input to the priority encoder 14. In addition, the OR-AND composite gate 62 of the CAM block CB_2 outputs a match sense output from its own match sense circuit 30 irrespective of the signal ACI.
[0153]
That is, the search is performed only in the CAM block CB_2 in which the entry data of the table 3 is registered, and the match flag output (signal MFO) output from the CAM block CB_2 is input to the priority encoder 14. By operating the priority encoder 14 in this state, it is possible to output the HMA of the entry whose match is detected in the table 3.
[0154]
As described above, the CAM 10 can perform a search in any state of four-word connection, two-word connection, and no word connection. When four words are connected, an entry that matches all four words can be searched, or an entry that matches only a part of the four words can be searched. It is also possible to register entry data to be searched in a plurality of tables and register them, and to search only entry data included in each table.
[0155]
It should be noted that the CAM of the present invention is not limited to the above embodiments, and one word can be configured by connecting any number of words. Further, the number of tables to be used is not limited at all, and may be appropriately determined as needed. The polarity of each signal such as the signals ACI, ACIEN, MFLT, ACO, ACOEN, MFO, and MFOE may be changed as necessary, and the configuration of the one-word circuit may be appropriately designed according to the polarity of each of these signals. Something to be done.
[0156]
The associative memory of the present invention is basically as described above.
As described above, the associative memory of the present invention has been described in detail. However, the present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. .
[0157]
【The invention's effect】
As described above in detail, the associative memory of the present invention can perform a search correctly in any state with or without word connection. In addition, when performing word concatenation, searching for an entry that matches in all words or a part of words, registering an entry to be searched in a plurality of tables, registering the table separately, and searching separately for each table, etc. Various search operations can be performed.
Further, in the associative memory of the present invention, when word concatenation is performed, a search is performed by correctly associating each one-word data of entry data with each one-word data of corresponding search data. It is possible to prevent the occurrence of an erroneous match which has been a problem in the conventional associative memory.
Further, in the associative memory of the present invention, since the CAM array is divided into a plurality of CAM blocks and the search is performed only in the CAM block to be searched at the time of search, unnecessary current consumption can be suppressed.
Further, in the associative memory of the present invention, since the search can be performed without initializing the match flag register, a step for initialization is unnecessary, and the search throughput can be improved as compared with the related art. Also, when a partial search is performed between CAM blocks that are not adjacent to each other when an entry is formed by connecting a plurality of words, it is not necessary to perform a dummy search in CAM blocks that are not to be searched. Throughput can be improved.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of an embodiment of an associative memory according to the present invention.
FIG. 2 is a schematic configuration diagram of a one-word circuit used in the associative memory shown in FIG. 1;
FIG. 3 is a configuration circuit diagram of a CAM cell used in the one-word circuit shown in FIG. 2;
FIG. 4 is a configuration circuit diagram of a coincidence sense circuit used in the one-word circuit shown in FIG. 2;
FIG. 5 is a conceptual diagram showing a state in which entry data having a 4-word width shown in FIG. 16 is registered in a CAM array.
FIG. 6 is a schematic diagram of two-word width entry data including two pieces of attribute data.
FIG. 7 is a conceptual diagram showing a state in which entry data having a two-word width shown in FIG. 6 is registered in a CAM array.
FIG. 8 is a schematic diagram of one-word-width entry data.
FIG. 9 is a schematic diagram showing a state in which the one-word-width entry data shown in FIG. 8 is registered in a CAM array.
FIG. 10 is a schematic diagram illustrating two tables including entry data having a width of two words.
11 is a conceptual diagram showing a state in which entry data of two words of two tables shown in FIG. 10 is registered in a CAM array.
FIG. 12 is a schematic diagram showing four tables including entry data of one word width.
13 is a schematic diagram showing a state where entry data of one word width of the four tables shown in FIG. 12 is registered in a CAM array.
FIG. 14 is a block diagram illustrating an example of a conventional CAM.
FIG. 15 is a configuration circuit diagram of an example of a conventional bit width extension circuit.
FIG. 16 is a schematic diagram showing an example of 4-word entry data composed of four attribute data.
17 is a conceptual diagram showing a registration example of the entry data shown in FIG.
[Explanation of symbols]
10,70 associative memory
12 CAM array
14,78 Priority encoder
16 1-word circuit
18 Block Driver
20 Search bit line driver
22 buffers
24 CAM words
26 word logic
28 CAM cells
30 Match sense circuit
32 memory circuit
34 Comparison circuit
36,38,52,54 Inverter
40, 42, 44, 46, 48, 50 N-type MOS transistors
56,58 P-type MOS transistor
60, MFR_1, MFR_2, ..., MFR_n match flag register
62 OR-AND composite gate
64 OR gate
66, AD_2, AD_3, ..., AD_n AND gate
72 Comparison Register
74 Mask register
76 Search bit line driver
80-bit width extension circuit
CB_0, CB_1, CB_2, CB_3 CAM block
W_1, W_2, ..., W_n words
LT_1, LT_2, ..., LT_n Latch

Claims (7)

An associative memory having a word connection function,
A CAM array having a plurality of CAM blocks, and a priority encoder that outputs an address of a word in which a match is detected according to a predetermined priority order;
Each of the CAM blocks includes a plurality of one-word circuits,
Each of the one-word circuits stores data of one word, performs a match search between the stored data and search data, and outputs a search result, and a CAM word of the one-word circuit. Means for outputting a signal obtained by taking the logic of the search result output from the CAM block and a match flag output from the corresponding one-word circuit of the preceding CAM block, and a signal output from the first means as a match flag A second means for outputting a match flag output from this register to a corresponding one-word circuit of a CAM block at a subsequent stage, and a match flag output from the register to the priority encoder 3. An associative memory, comprising: third means. The first means outputs the search result output from the CAM word of the one-word circuit as it is, or outputs the search result output from the CAM word of the one-word circuit and the corresponding one-word circuit of the preceding CAM block. Means for controlling whether to output a signal obtained by taking a logic with a match flag output from
The register includes means for controlling whether to latch a signal output from the first means,
The second means includes means for controlling whether or not to output a match flag output from the register to a corresponding one-word circuit of the subsequent CAM block.
2. The associative memory according to claim 1, wherein said third means includes means for controlling whether or not to output a match flag output from said register to said priority encoder. When a plurality of words are connected to form entry data, data of one word constituting each entry data is registered in a one-word circuit of a corresponding CAM block before the search. The search for a match between each one-word data constituting the data and the corresponding one-word data of the search data is sequentially performed only in the CAM block corresponding to each one-word data constituting the entry data. 3. The associative memory according to claim 1, wherein the associative memory is used. 4. The associative memory according to claim 3, wherein a search is made for entry data in which all the one-word data of the entry data and all the one-word data of the search data corresponding to the data match. 4. The associative memory according to claim 3, wherein a search is made for entry data in which a part of one-word data constituting the entry data and a part of one-word data of the search data corresponding thereto match. When sequentially searching one word of data registered in one word circuit of each of the preceding and succeeding CAM blocks that are not adjacent to each other, a search is performed for a CAM block between the preceding and succeeding CAM blocks where no match search is performed. 6. The associative memory according to claim 5, wherein in one word circuit, a match flag output from a corresponding one word circuit of the preceding CAM block is transmitted to a corresponding one word circuit of the following CAM block. Before search, entry data included in a plurality of independent tables are registered in the one-word circuit of the corresponding CAM block, and at the time of search, only the CAM block in which entry data corresponding to the table to be searched is registered 7. The associative memory according to claim 1, wherein a search is performed.

Images