JP2004280272A - Information processing apparatus, control method, control program and record medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce electric power consumption to increase a battery service life in a dive computer with a plurality of microprocessors having different operation clocks. <P>SOLUTION: A sub microcomputer 200 operates in a low-power-consumption operation mode until transmission data next to already received transmission data among a series of transmission data necessary for arithmetic processing transmitted from a main microcomputer are transmitted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus including a plurality of microprocessors having different operation clocks.
[Prior art]
2. Description of the Related Art Conventionally, a divers information processing device (hereinafter referred to as a dive computer) has been known as a portable information processing device (for example, see Patent Document 1).
This dive computer requires a high-speed clock or an 8-bit or 16-bit microprocessor (CPU) in order to provide information in a short amount of time in a complicated operation, for example, a decompression operation. Need a system. However, when these microprocessors are used, there is a problem that the battery life is extremely shortened because a general standby current for a clock and a display is large. Such a state is not preferable for a life-related information device such as a diving computer. In order to avoid this, conventionally, a dive computer is configured by mounting two microprocessors, a low-speed low-power consumption microprocessor and a high-speed high power consumption microprocessor, and one of the microprocessors Had a configuration in which processing was performed.
Specifically, a low-speed, low-power-consumption microprocessor (for example, a clock frequency of 32 kHz, a 4-bit microprocessor) performs time-keeping processing and display processing, and requires high-load operation processing such as decompression operation. In such a case, a microprocessor (for example, a clock frequency of 4 MHz, 16-bit microprocessor) operating at high speed and high power consumption is operated, and data communication is performed between the two microprocessors to cooperate with each other, thereby securing a battery life. Was.
[0002]
[Patent Document 1]
JP-A-11-20787
[0003]
[Problems to be solved by the invention]
By the way, in the microprocessor of the above-mentioned conventional dive computer, when performing the decompression operation, it is sufficient to perform the operation on nitrogen and oxygen.
However, in recent dive computers, it has become necessary for the microprocessor to further perform an operation on helium, the necessary information on decompression has increased, and not only the operation time but also the use of two The data communication time between processors has also been increasing.
Since the two microprocessors have different operation clocks as described above, in order to synchronize the operation clocks of the two microprocessors, it is necessary to match the operation timing with the low-speed microprocessor, which is wasteful for the high-speed microprocessor. However, there is a problem that a standby time is generated and power consumption is unnecessarily increased.
Therefore, an object of the present invention is to reduce the power consumption and prolong the battery life of a diver's information processing apparatus including a plurality of microprocessors having different operation clocks without hindering operation.
[0004]
[Means for Solving the Problems]
In order to solve the above problem, a first arithmetic processing unit that operates with a first operation clock and a second arithmetic processing unit that operates with a second operation clock that is faster than the first operation clock are provided. In the information processing apparatus for divers having, the second arithmetic processing unit is configured to perform the next transmission of the transmission data already received among a series of transmission data necessary for arithmetic processing transmitted from the first arithmetic processing unit. It operates in a low power consumption operation mode during a period until data is transmitted.
[0005]
In this case, the second arithmetic processing unit may shift to the low power consumption operation mode every time reception of each of the transmission data constituting the series of transmission data is completed.
Further, the second arithmetic processing unit may shift to the normal operation mode after a predetermined timing at which new transmission data can be received.
Further, the second arithmetic processing unit sets a timing synchronized with a transition timing of the synchronization clock signal input from the first arithmetic processing unit as a timing at which the new transmission data can be received. It may be.
Diversity information processing, comprising: a first arithmetic processing unit that operates with a first operation clock; and a second arithmetic processing unit that operates with a second operation clock that is faster than the first operation clock. In the apparatus, the second arithmetic processing unit operates in a low power consumption operation mode during a period until a next transmission data of a series of transmission data to be transmitted to the first arithmetic processing unit is transmitted. It is characterized by:
[0006]
In this case, the second arithmetic processing unit may shift to the low power consumption operation mode every time reception of each of the transmission data constituting the series of transmission data is completed.
Further, the second arithmetic processing unit may set a timing synchronized with a transition timing of the synchronization clock signal input from the first arithmetic processing unit as a timing for shifting to the low power consumption operation mode. Good.
Further, the low power consumption mode includes a first low power consumption mode in which oscillation of the oscillation circuit is continued when power is supplied to the return circuit, and a second low power consumption mode in which oscillation of the oscillation circuit is stopped. There may be.
Furthermore, the selection of the first low power consumption mode or the second low power consumption mode may be made according to the content of the arithmetic processing.
Diversity information processing, comprising: a first arithmetic processing unit that operates with a first operation clock; and a second arithmetic processing unit that operates with a second operation clock that is faster than the first operation clock. The control method of the device includes a receiving step of receiving a series of transmission data necessary for an arithmetic processing transmitted from the first arithmetic processing unit, and a step of receiving the next transmission data following the already received transmission data. And an operation mode shift step of shifting the second arithmetic processing unit to the low power consumption operation mode during the period.
[0007]
Diversity information processing, comprising: a first arithmetic processing unit that operates with a first operation clock; and a second arithmetic processing unit that operates with a second operation clock that is faster than the first operation clock. The control method of the device includes a transmitting step of transmitting transmission data from the second processing unit to the first processing unit, and a step of transmitting the next transmission data in the series of transmission data to be transmitted. And operating the second arithmetic processing unit in the low power consumption operation mode during the period.
[0008]
In these cases, the low power consumption mode includes a first low power consumption mode in which oscillation of the oscillation circuit is continued when power is supplied to the return circuit, and a second low power consumption mode in which oscillation of the oscillation circuit is stopped. There may be a mode.
The selection of the first low power consumption mode or the second low power consumption mode may be made according to the content of the arithmetic processing.
Diversity information processing, comprising: a first arithmetic processing unit that operates with a first operation clock; and a second arithmetic processing unit that operates with a second operation clock that is faster than the first operation clock. A control program for controlling the apparatus by a computer causes the second arithmetic processing unit to receive a series of transmission data required for arithmetic processing transmitted from the first arithmetic processing unit, and the transmission data already received. The second arithmetic processing unit is shifted to a low power consumption operation mode during a period until the next transmission data is transmitted.
[0009]
Diversity information processing, comprising: a first arithmetic processing unit that operates with a first operation clock; and a second arithmetic processing unit that operates with a second operation clock that is faster than the first operation clock. A control program for controlling the device by a computer causes the second arithmetic processing unit to transmit transmission data to the first arithmetic processing unit, and transmits the next transmission data in the series of transmission data to be transmitted. The second arithmetic processing unit is operated in a low power consumption operation mode during a period before transmission.
[0010]
In these cases, the low power consumption mode includes a first low power consumption mode in which oscillation of the oscillation circuit is continued when power is supplied to the return circuit, and a second low power consumption mode in which oscillation of the oscillation circuit is stopped. There is a mode, and the selection of the first low power consumption mode or the second low power consumption mode may be performed according to the content of the arithmetic processing.
Each of the above control programs can be recorded on a computer-readable recording medium.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, a preferred embodiment of the present invention will be described.
[1] First Embodiment
FIG. 1 is an external front view of the dive computer according to the first embodiment.
The dive computer 1 calculates and displays the depth and dive time of the diver during the dive, measures the amount of inert gas (mainly the amount of nitrogen gas) accumulated in the body during the dive, and from the measurement results after the dive It is configured to display the time until nitrogen accumulated in the body is discharged from the body in a state of rising from water.
The dive computer 1 is used by attaching arm bands 3 and 4 to the disc-shaped apparatus main body 2 in the vertical direction in the drawing, and wearing the dive computer 1 on the user's arm in the same manner as a wristwatch by the arm bands 3 and 4. It has become.
The apparatus main body 2 has an upper case and a lower case fixed in a completely watertight state by means of screws or the like, and incorporates various electronic components (not shown). A display unit 10 having a liquid crystal display panel 11 is provided on the front side of the apparatus main body 2 in the drawing.
[0012]
Further, an operation unit 5 for selecting / switching various operation modes in the dive computer 1 is formed on a lower side of the drawing of the apparatus main body 2, and the operation unit 5 has two switches A and B of a push button type. ing. On the left side of the apparatus main body 2 in the drawing, a diving operation switch 30 using a conduction sensor used for determining whether or not diving has started is configured. The diving operation monitoring switch 30 has electrodes 31 and 32 provided on the front side of the apparatus main body 2 in the drawing. When the electrodes 31 and 32 are brought into conduction by seawater or the like, the resistance between the electrodes 31 and 32 is changed. When the value becomes smaller, it is determined that water has entered. However, the diving operation switch 30 is only used to detect that water has been entered and to shift the operation mode of the dive computer 1 to the diving mode, and to detect that diving has actually started. It is not used for That is, in some cases, the arm of the user wearing the dive computer 1 may simply be immersed in seawater, and it is not preferable to determine that diving has started in such a state.
For this reason, in this dive computer, when the water pressure (water depth) is equal to or more than a predetermined value by the pressure sensor built in the apparatus main body 2, more specifically, when the water pressure becomes equal to or more than 1.5 [m] in water depth. The diving is considered to have started, and when the water pressure becomes less than 1.5 [m] in water depth, the diving is considered to have ended.
[0013]
FIG. 2 is a schematic functional configuration block diagram of the dive computer according to the embodiment.
The dive computer 1 is roughly divided into a main microcomputer 100, a switch unit 101, a buzzer unit 102, an EEPROM 103, a sensor unit 104, an LCD unit 105, a main oscillation circuit unit 106, an EL unit 107, A sub microcomputer 200, a sub oscillation circuit unit 201, and a communication bus 300 are provided.
The main microcomputer 100 roughly includes a microprocessor 50, a ROM 51, and a RAM 52.
The microprocessor 50 controls the entire main microcomputer 100 based on the first reference clock signal from the main oscillation circuit unit 106 and a control program stored in the ROM 51 in advance.
The ROM 51 stores various control programs and control data in advance.
[0014]
The RAM 52 temporarily stores various data.
The switch unit 101 includes the above-described two switches A and B constituting the operation unit 5.
The buzzer unit 102 outputs various warnings to the diver who is the user, a notification to the user by an alarm sound of a warning sound, and the like.
The EEPROM 103 stores various setting data or diving records in a nonvolatile manner.
The sensor unit 104 includes the diving operation monitoring switch 30 and a pressure sensor (not shown) for measuring atmospheric pressure or water pressure.
The LCD unit 105 includes a liquid crystal display panel 11 for displaying various information and a liquid crystal driver for driving the liquid crystal display panel 11.
The main oscillation circuit unit 106 generates a first reference clock signal (32 kHz in this embodiment) serving as a reference clock of the main microcomputer 100 and outputs the first reference clock signal to the main microcomputer 100.
The EL unit 107 includes an EL panel and an EL panel driver for performing illumination as a backlight of the LCD unit 105.
[0015]
The sub-microcomputer 200 roughly includes a microprocessor 60, a ROM 61, and a RAM 62.
The microprocessor 60 controls the entire sub-microcomputer 200 based on the second reference clock signal from the sub-oscillation circuit unit and a control program stored in the ROM 61 in advance.
The ROM 61 stores various control programs and control data in advance.
The RAM 62 temporarily stores various data.
The sub-oscillation circuit unit 201 generates a second reference clock signal (4 MHz in the present embodiment) serving as a reference clock of the sub-microcomputer 200 and outputs it to the sub-microcomputer 200.
The communication bus 300 roughly includes a write command line L1, a clock line L2, a read command line L3, and a data line L4.
The write command line L1 connects between the write command output terminal P11 of the main microcomputer 100 and the write command input terminal P21 of the sub-microcomputer 200. By being output to the microcomputer 200, it is notified that the data output process on the main microcomputer 100 is completed, and the sub-microcomputer 200 shifts to a data receiving state.
[0016]
The clock line L2 connects between the clock output terminal P12 of the main microcomputer 100 and the clock input terminal P22 of the sub-microcomputer 200, and the main microcomputer 100 outputs a clock CLK for operation synchronization.
The read command line L3 connects between the read command input terminal P13 of the main microcomputer 100 and the read command output terminal P23 of the sub microcomputer 200, and the read command READ from the sub microcomputer 200 is sent to the main microcomputer 100. By being output, it is notified that the data output processing on the side of the sub-microcomputer 200 is completed, and the main microcomputer 100 shifts to a data receiving state.
The data line L4 connects between the data input / output terminal P14 of the main microcomputer 100 and the data input / output terminal P24 of the sub microcomputer 200, and various data is input / output based on a write command or a read command. You.
[0017]
Next, the communication operation will be described.
First, the general operation will be described.
In the dive computer 1, only the main microcomputer 100 operates during normal processing such as time counting for time display.
Then, when performing a complicated calculation relating to the inert gas, the sub-microcomputer 200 operated by the high-speed clock is shifted to the operating state. That is, the main microcomputer 100 transmits data such as water depth to the sub microcomputer 200 side. As a result, the sub microcomputer 200 shifts to the normal operation mode, and after the processing is completed, transmits the result to the main microcomputer 100.
Then, the main microcomputer 100 receiving the processing result performs the display processing.
Next, a specific communication operation will be described.
FIG. 3 is a timing chart of a data communication operation when data is transmitted from the main microcomputer 100 to the sub microcomputer 200.
[0018]
When a write command WRITE is input from the main microcomputer 100 to the sub-microcomputer 200 via the write command line L1, the microprocessor 60 of the sub-microcomputer 200 is input at time t1 via the clock line L2. When the clock signal CLK rises, it shifts from the standby state (low power consumption operation mode) to the normal state (normal operation mode) in synchronization with the clock signal CLK.
Then, the microprocessor 60 reads the data D1 output to the data input / output line L4 in synchronization with the clock signal CLK at time t2.
Then, when the reading of the data D1 is completed, the microprocessor 60, and eventually the sub-microcomputer 200, shifts to the standby state again at time t3.
Hereinafter, similarly, the microprocessor 60 reads the data D2 output to the data input / output line L4 in synchronization with the clock signal CLK at time t4, and upon completion of reading the data D2, waits again at time t5. Transition to the state.
[0019]
Further, the microprocessor 60 reads the data D3 output to the data input / output line L4 in synchronization with the clock signal CLK at the time t6, and when the reading of the data D3 is completed, the microprocessor 60 shifts to the standby state again at the time t7. .
Then, at time t8, when reading of the last data Dn of the series of data necessary for the operation is completed, the microprocessor 60 maintains the normal state (normal operation mode) even after the data reading is completed, and receives and reads. The operation shifts to the actual calculation based on the data D1 to Dn.
[0020]
FIG. 4 is a timing chart of a data communication operation when data is transmitted from the sub microcomputer 200 to the main microcomputer 100.
When the sub microcomputer 200 completes the arithmetic processing, the microprocessor 60 outputs the data D11 to the data line L4 and outputs a read command to the read command line L3 at time t11.
At time t12, the microprocessor 60 shifts to the standby state.
Thereafter, when the clock signal CLK rises at time t13, the microprocessor 50 of the main microcomputer 100 reads the data D11 at time t14 in synchronization with the rise of the clock signal CLK.
At time t15, when the clock signal CLK falls again, in synchronization with this, at time t16, the microprocessor 60 of the sub-microcomputer 200 shifts to the normal operation state again, and outputs the data D12 to the data line L4. At time t17, the state shifts to the standby state.
[0021]
Thereafter, at time t18, when the clock signal CLK rises, in synchronization with this, at time t19, the microprocessor 50 of the main microcomputer 100 reads the data D12.
At time t20, when the clock signal CLK falls again, in synchronization with this, at time t21, the microprocessor 60 of the sub-microcomputer 200 shifts to the normal operation state again, and outputs the data D13 to the data line L4. At a time t22, the state shifts to the standby state.
Thereafter, at time t23, when the clock signal CLK rises, in synchronization with this, the microprocessor 50 of the main microcomputer 100 reads the data D12 at time t24.
Thereafter, the same processing is repeated until time t25 is reached, and when the clock signal CLK rises, in synchronization with this, at time t26, the microprocessor 50 of the main microcomputer 100 reads the last data D1n of the series of data.
Then, at time t27, when the clock signal CLK falls, in synchronization with this, at time t28, the microprocessor 60 of the sub-microcomputer 200 shifts to the normal operation state again, performs port setting, etc., and at t29 The process shifts to the standby state, and prepares for the next data communication operation with the main computer 100.
[0022]
As described above, according to the first embodiment, the sub-microcomputer 200 transmits the next transmission of the already received transmission data in the series of transmission data necessary for the arithmetic processing transmitted from the main microcomputer 100. Since the device operates in the standby state (low power consumption operation mode) until data is transmitted, it is possible to reduce power consumption without hindering operation.
[0023]
[2] Second embodiment
Although the standby state of the sub-microcomputer 200 has not been described in detail in the first embodiment, the second embodiment is an embodiment in which there are two standby states.
That is, in the standby state of the microprocessor 60 of the sub-microcomputer 200, the so-called HALT state (first low power consumption mode) in which the oscillation of the oscillation circuit is continued to stop the operation of the logic circuit and the like, and the oscillation circuit , The so-called stop state (second low power consumption mode).
Comparing the HALT state and the stop state, the time required for transition to the normal state (normal operation mode) can be instantaneous transition from the HALT state, but the oscillation is stable in the stop state. Since it takes a long time to complete, it may take several hundred msec. As for power consumption, the stop state is two to three times less than the HALT state.
In addition, there are roughly two types of operations in the dive computer. The type of the operation can be identified by, for example, the microprocessor 60 of the sub-microcomputer 200 based on data transmitted from the main microcomputer 100 via the data line L4.
[0024]
The first type of calculation is a calculation for calculating the amount of the inert gas that dissolves or is discharged into the body within a predetermined time.
The second type of calculation is a calculation for calculating a no-decompression diving time, which is a time during which no decompression is performed, based on the amount of the inert gas calculated by the first calculation.
Of the two calculations, the calculation of the amount of the inert gas by the first type of calculation can be performed relatively easily on the calculation formula, so that the calculation time is short and the calculation is completed in 100 msec.
On the other hand, the calculation of the non-decompression diving possible time by the second type of calculation uses an iterative calculation method, so that when it takes a long time, it may take 800 msec.
By the way, in the state of diving, the dive computer needs to measure the water depth every second and calculate and display the non-decompression diving time based on the water depth measured every second.
At this time, if the sub-microcomputer 200 is always set to the stop state, even if an interrupt request is made from the main microcomputer 100 for the calculation processing of the no-decompression diving possible time, the non-decompression diving possible time is calculated, and the result is obtained. May take more than one second to return, and it is not possible to shift to the low power consumption mode.
[0025]
Therefore, during a dive, when performing a time-consuming non-decompression diving time calculation, the standby state is set to HALT so that the dive can be started up instantaneously.
In addition, on land, the calculation of the emission of the inert gas dissolved in the body, which is calculated every predetermined time, is completed within one second even if it rises from the stop state because the calculation time is short. Will not occur.
When the type of operation to be performed is known in advance, it is possible to efficiently obtain necessary information by switching the standby state of the microprocessor 60 of the sub-microcomputer 200 according to the required operation. Has become.
Also, on land (during non-diving), where the use time is longer than the use time during diving, the microprocessor 60 can be made to wait in the state of the lowest current consumption.
[0026]
[3] Specific effects of the embodiment
If the processing speed of the microprocessor 50 of the main microcomputer 100 is one instruction and one machine cycle, and one machine cycle is two clocks, in the case of the above example, since it operates at 32 kHz, one instruction is about 61 μsec.
On the other hand, the processing speed of the microprocessor 60 of the sub-microcomputer 200 is about 500 nsec for one instruction since it operates at 4 MHz in the above example.
That is, the clock of the microprocessor 50 of the main microcomputer 100 needs a width of at least 61 μsec.
In an actual operation, data must be output or input from a data input / output terminal, and a write or read operation to the RAM is also required. Therefore, a time of at least 300 μsec from the rise of the clock is required.
[0027]
On the other hand, even if the reception or transmission processing of the microprocessor 60 of the sub-microcomputer 200 determines that the data is expanded into the RAM, it is about 50 machine cycles, and the actual time is considered to be 25 μsec. Therefore, if the system does not shift to the standby state, it must continue operating in the normal state (normal operation mode) until the next data processing.
Assuming that the microprocessor 60 of the sub-microcomputer 200 operates with the above-mentioned clock of 4 MHz, it can be generally considered that about 2 mA is consumed. On the other hand, it is 1 μA or less in the standby state.
As a result, the power consumption of the entire sub-microcomputer 200 can be reduced about 10 times.
The reduction in power consumption makes it possible to extend the operation time of the portable device, and the safety of a portable device, such as a dive computer, which is critical to life is greatly enhanced. In addition, since the frequency of battery replacement is reduced, an effect can be obtained also in waterproofness.
[0028]
[4] Modification of Embodiment
In the above description, the case where the control program is stored in the ROMs 51 and 61 in advance has been described. However, the control program is recorded in advance on a recording medium such as various magnetic disks, optical disks, and memory cards, and these recording programs are recorded. It is also possible to configure to read from the medium and install. It is also possible to provide a communication interface, download the control program via a network such as the Internet or a LAN, install and execute the control program.
In the above description, the case where the dive computer is of the arm-mounted type has been described. However, the present invention is not limited to this, and modifications such as a diving suit embedded type, a torso mounted type, and an underwater mask built-in type are conceivable.
[0029]
【The invention's effect】
According to the present invention, it is possible to reduce power consumption without hindering operation. As a result, the battery life of the divers information processing apparatus can be extended, and the number of times of battery replacement can be reduced.
[Brief description of the drawings]
FIG. 1 is an external view of a dive computer.
FIG. 2 is a schematic block diagram of a dive computer.
FIG. 3 is a timing chart when a sub microcomputer reads data from a main microcomputer.
FIG. 4 is a timing chart when a main microcomputer reads data from a sub microcomputer.
[Explanation of symbols]
1. Dive computer
50 ... Microprocessor
51… ROM
52 ... RAM
60 ... Microprocessor
61 ... ROM
62 ... RAM
100 ... Main microcomputer
101 ... Switch section
102… Buzzer part
103… EEPROM
104 ... Sensor part
105 ... LCD section
106: Main oscillation circuit section
107 ... EL section
200 ... Sub microcomputer
201 ... Sub oscillation circuit diagram
300 ... Communication bus

Claims (17)

An information processing apparatus, comprising: a first arithmetic processing unit that operates with a first operation clock; and a second arithmetic processing unit that operates with a second operation clock that is faster than the first operation clock.
The second arithmetic processing unit is configured to perform a period until the next transmission data of the already received transmission data is transmitted in a series of transmission data necessary for the arithmetic processing transmitted from the first arithmetic processing unit. An information processing device that operates in a low power consumption operation mode. The information processing apparatus according to claim 1,
The information processing device, wherein the second arithmetic processing unit shifts to the low power consumption operation mode every time reception of each of the transmission data constituting the series of transmission data is completed. In the information processing apparatus according to claim 1 or 2,
The information processing apparatus, wherein the second arithmetic processing unit shifts to a normal operation mode after a predetermined timing at which new transmission data can be received. The information processing apparatus according to claim 3,
The second arithmetic processing unit is characterized in that a timing synchronized with a transition timing of a synchronization clock signal input from the first arithmetic processing unit is a timing at which the new transmission data can be received. Information processing device. A first arithmetic processing unit that operates on a first operation clock;
An information processing apparatus comprising: a second arithmetic processing unit that operates with a second operation clock that is faster than the first operation clock;
The second arithmetic processing unit operates in a low power consumption operation mode during a period until a next transmission data is transmitted from a series of transmission data to be transmitted to the first arithmetic processing unit. Information processing device. The information processing apparatus according to claim 5,
The information processing device, wherein the second arithmetic processing unit shifts to the low power consumption operation mode every time reception of each of the transmission data constituting the series of transmission data is completed. In the information processing apparatus according to claim 5 or 6,
The information processing apparatus, wherein the second arithmetic processing unit sets a timing synchronized with a transition timing of the synchronization clock signal input from the first arithmetic processing unit as a timing for shifting to a normal operation mode. The information processing apparatus according to any one of claims 1 to 7,
The low power consumption mode includes a first low power consumption mode in which oscillation of the oscillation circuit is continued when supplying power to the return circuit, and a second low power consumption mode in which oscillation of the oscillation circuit is stopped. An information processing apparatus characterized by the above-mentioned. The information processing apparatus according to claim 8,
The information processing apparatus according to claim 1, wherein the selection of the first low power consumption mode or the second low power consumption mode is performed according to the content of the arithmetic processing. A control method for an information processing apparatus, comprising: a first arithmetic processing unit that operates with a first operation clock; and a second arithmetic processing unit that operates with a second operation clock that is faster than the first operation clock. At
A receiving step of receiving a series of transmission data necessary for arithmetic processing transmitted from the first arithmetic processing unit;
An operation mode transition step of causing the second arithmetic processing unit to transition to a low power consumption operation mode during a period until the next transmission data of the already received transmission data is transmitted;
A control method comprising: A control method for an information processing apparatus, comprising: a first arithmetic processing unit that operates with a first operation clock; and a second arithmetic processing unit that operates with a second operation clock that is faster than the first operation clock. At
A transmitting step of transmitting transmission data from the second arithmetic processing unit to the first arithmetic processing unit;
An operation mode transition step of operating the second arithmetic processing unit in the low power consumption operation mode during a period before transmitting the next transmission data in the series of transmission data to be transmitted;
A control method comprising: In the control method according to claim 10 or 11,
The low power consumption mode includes a first low power consumption mode in which oscillation of the oscillation circuit is continued when supplying power to the return circuit, and a second low power consumption mode in which oscillation of the oscillation circuit is stopped. A control method characterized by the above-mentioned. The control method according to claim 12,
The control method according to claim 1, wherein the selection of the first low power consumption mode or the second low power consumption mode is performed according to the content of the arithmetic processing. An information processing apparatus having a first arithmetic processing unit operating with a first operating clock and a second arithmetic processing unit operating with a second operating clock faster than the first operating clock is processed by a computer. In the control program for controlling,
Causing the second arithmetic processing unit to receive a series of transmission data necessary for arithmetic processing transmitted from the first arithmetic processing unit,
Causing the second arithmetic processing unit to shift to the low power consumption operation mode during a period until the next transmission data of the already received transmission data is transmitted;
A control program characterized by the above-mentioned. An information processing apparatus having a first arithmetic processing unit operating with a first operating clock and a second arithmetic processing unit operating with a second operating clock faster than the first operating clock is processed by a computer. In the control program for controlling,
Transmitting transmission data from the second arithmetic processing unit to the first arithmetic processing unit;
Operating the second arithmetic processing unit in the low power consumption operation mode during a period until the next transmission data of the series of transmission data to be transmitted is transmitted;
A control program characterized by the above-mentioned. In the control program according to claim 14 or 15,
The low power consumption mode includes a first low power consumption mode in which oscillation of the oscillation circuit is continued when power is supplied to the return circuit, and a second low power consumption mode in which oscillation of the oscillation circuit is stopped. A control program for causing a user to select the first low power consumption mode or the second low power consumption mode according to the content of the arithmetic processing. A computer-readable recording medium on which the control program according to claim 14 is recorded.

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