JP2004279850A - Video display unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video display unit for easily and accurately performing regulation working in correction of zigzag vertical line obstruction. <P>SOLUTION: The video display unit modulates the frequency of a clock signal CK2 generated from a second PLL circuit for correcting horizontal positional deviation dH of the corresponding pixel in the scanning line of an outward trip and the scanning line of a return trip on a screen 500 from a clock modulation circuit; displays a pixel TL based on a video signal of the scanning line of the outward trip on a first region on the screen 500 from a video mask circuit, displays a pixel RL, based on the video signal of the scanning line of the return trip on a second region adjacent to a vertical direction to the first region, without displaying the pixel RL, on the basis of the video signal of the scanning line of the return trip; and processes the video signal read from a memory so as not to display the pixel TL, based on the video signal of the scanning line of the return trip. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image display device provided with a reciprocating deflection circuit for reciprocally scanning an electron beam on a display screen.
[0002]
[Prior art]
In the field of video display devices such as a cathode ray tube (hereinafter, referred to as CRT) display device, use of a reciprocating deflection circuit suitable for displaying a high-definition image has been proposed. This reciprocating deflection system is a device for reciprocally scanning an electron beam using a horizontal deflection coil. In the reciprocating deflection system, since the horizontal deflection coil equivalently has an inductance component and a resistance component connected in series with the horizontal deflection coil, the pixels that should be arranged vertically in a vertical line between the forward scan and the backward scan. It may shift in the horizontal direction.
[0003]
FIG. 6 is a diagram for explaining the change over time of the horizontal deflection current flowing in the horizontal deflection coil. FIG. 7 is a view for explaining the state of the display screen corresponding to the current waveform of the horizontal deflection current shown in FIG. In FIG. 7, the horizontal direction is called an x coordinate, and the vertical direction is called a y coordinate.
[0004]
FIG. 6A shows an ideal current waveform of the horizontal deflection current. In the state shown in FIG. 6A, the length of the forward scanning period T1 of the electron beam coincides with the length of the backward scanning period T2, and the times t1 and t2 at which the current becomes 0 in the forward scanning and the backward scanning are determined. Each coincides with an intermediate point between the scanning periods T1 and T2. Therefore, as shown in FIG. 7A, pixels that should be arranged in a line vertically are displayed on the same x coordinate in the forward scan and the backward scan. For example, in the forward scan and the backward scan, the display positions of the center pixels e1 and e2 in the horizontal direction of the screen in FIG. 7A are on the same x coordinate.
[0005]
FIG. 6B shows a current waveform having distortion due to a resistance component of the horizontal deflection coil. In the state shown in FIG. 6B, the length of the forward scanning period T3 and the length of the backward scanning period T4 match, but the intermediate points t4 and t6 of the forward and backward scanning periods T3 and T4 are the same. It does not coincide with the time points t3 and t5 when the horizontal deflection current becomes 0. For this reason, as shown in FIG. 7B, a zigzag vertical line fault occurs in which pixels that should be vertically aligned in a line are shifted in a zigzag manner in the forward scan and the backward scan. For example, in the forward scan and the backward scan, the x coordinates of the display position of the center pixels e1 and e2 in the horizontal direction of the screen in FIG.
[0006]
Therefore, in order to prevent such a zigzag vertical line failure, there has been proposed a deflection device that corrects a deviation between a pixel display position in a forward scan and a pixel display position in a backward scan by clock modulation (see FIG. For example, see Patent Literatures 1 and 2). In such a deflecting device, a digital video signal is written to a memory in response to a write clock signal, and a digital video signal is read from the memory in response to a read clock signal. In this case, by modulating the frequency of the read clock signal, the read timing of the digital video signal is controlled in the forward scan or the backward scan, and the display position of the pixel in the forward scan and the display position of the pixel in the forward scan are determined. They can be matched in the horizontal direction.
[0007]
[Patent Document 1]
JP-A-8-172543
[Patent Document 2]
JP 2000-341552 A
[0008]
[Problems to be solved by the invention]
The amount of deviation between the pixel display position in the forward scan and the pixel display position in the backward scan differs depending on the magnitude of the resistance component of the horizontal deflection coil, and varies from video display device to video display device.
[0009]
Therefore, in the manufacturing process, it is necessary for an operator to inspect the shift amount of the pixel display position for each video display device and adjust the correction amount by the clock modulation according to the shift amount. In this case, the operator observes the vertical line displayed on the screen and adjusts the correction amount by the clock modulation so that the vertical line is corrected from zigzag to linear. However, it is difficult to recognize that the zigzag vertical line has been accurately corrected to a straight line, and such adjustment requires a high level of skill and requires a lot of adjustment time.
[0010]
SUMMARY OF THE INVENTION It is an object of the present invention to provide an image display device capable of easily and accurately performing an adjustment operation for correcting a zigzag vertical line obstacle.
[0011]
[Means for Solving the Problems]
(1) First invention
An image display device according to the present invention is an image display device that displays an image based on an image signal by reciprocally deflecting a scanning line on a screen, and a storage unit for storing the image signal, and scanning of an outward path and a return path. A first clock generating means for generating a first clock signal for writing a video signal corresponding to the above to the storage means, and a second clock signal for reading a video signal corresponding to forward and backward scanning from the storage means A second clock generating means for generating the image signal, a display means for displaying an image signal as an image by irradiating an electron beam on the screen based on the image signal read from the storage means, A horizontal deflection coil that reciprocates in the direction to form a forward scan line and a return scan line on the screen, and a corresponding pixel in the forward scan line and the backward scan line on the screen. A clock modulating means for modulating the frequency of a second clock signal generated by the second clock generating means for correcting a displacement in a horizontal direction; and a forward scanning line in a first area on a screen during adjustment A pixel based on the video signal of the backward scanning line in the second area adjacent to the first area in the vertical direction without displaying the pixel based on the video signal of the backward scanning line. And processing means for processing the video signal read from the storage means so as not to display pixels based on the video signal of the outward scanning line.
[0012]
In the video display device according to the first invention, the video signal is written to the storage unit in response to the first clock signal generated by the first clock generation unit, and is generated by the second clock generation unit. The video signal is read from the storage means in response to the second clock signal. An electron beam based on the video signal read from the storage means is irradiated on a screen and displayed as an image by the display means. In this case, the electron beam is reciprocally deflected in the horizontal direction by the horizontal deflection coil, and scanning lines on the screen are formed on the screen. The frequency of the second clock signal generated by the second clock generation means is modulated by the clock modulation means to correct the horizontal displacement of the corresponding pixels on the forward scan line and the return scan line on the screen. Is done. Thereby, the timing of reading the video signal from the storage means is controlled, and the display position of the pixel on the screen is controlled.
[0013]
At the time of adjustment, the processing unit displays pixels based on the video signal of the forward scan line in the first area on the screen, and does not display the pixels based on the video signal of the backward scan line, and displays the pixel in the vertical direction with respect to the first area. The video signal read from the storage means is processed so that pixels based on the video signal of the backward scanning line are displayed in the second area adjacent to the pixel and the pixels based on the video signal of the outward scanning line are not displayed.
[0014]
Thereby, when a vertical line is displayed on the screen, a linear vertical line is displayed in the first area by the forward scan, and a linear vertical line is displayed in the second area by the return scan. . Therefore, based on the deviation between the end of the vertical line displayed in the first area and the end of the vertical line displayed in the second area, the display position of the pixel by the forward scan and the pixel by the backward scan are determined. Can be easily and accurately recognized. Therefore, the zigzag vertical line failure can be accurately corrected in a short time without requiring a high level of skill. As a result, manufacturing costs and manufacturing time are reduced.
[0015]
(2) Second invention
A video display device according to a second aspect of the present invention is the video display device according to the first aspect, wherein the processing unit is configured to perform a forward scan line to be displayed in the first area on the screen from the storage unit at the time of adjustment. When the video signal is read, the read video signal is output to the display means, and the video signal of the backward scanning line to be displayed in the first area on the screen is read from the storage means. A predetermined value is output to the display means when the video signal is read out, and the video signal read when the video signal of the return scanning line to be displayed in the second area on the screen is read from the storage means. Is output to the display means, and a predetermined value is output to the display means when the video signal of the outward scanning line to be displayed in the second area on the screen is being read from the storage means.
[0016]
Thus, pixels based on the video signal of the outward scan line can be displayed in the first area, and pixels based on the video signal of the return scan line can be displayed in the second area.
[0017]
(3) Third invention
A video display device according to a third aspect of the present invention is the video display device according to the first aspect, wherein the processing means is activated or disabled by a predetermined activation signal. It outputs a signal to the display means.
[0018]
In this case, the processing means can be activated or deactivated by a predetermined activation signal. Therefore, by activating the processing means at the time of adjustment, the zigzag vertical line failure can be accurately corrected in a short time. In addition, by disabling the processing means at the time of non-adjustment, an image based on a normal image signal is displayed on the screen by the display means. Further, the zigzag vertical line fault can be readjusted by activating the processing means with the activation signal.
[0019]
(4) Fourth invention
The video display device according to a fourth aspect is the video display device according to any one of the first to third aspects, wherein the clock modulation unit is generated by the second clock generation unit based on the input correction amount. Modulates the frequency of the second clock signal.
[0020]
In this case, the frequency of the second clock signal can be modulated based on the input correction amount. Therefore, the worker displays a vertical line on the screen, and performs input so that the end of the vertical line displayed in the first area matches the end of the vertical line displayed in the second area. By adjusting the correction amount to be performed, the zigzag vertical line obstacle can be corrected easily and accurately.
[0021]
(5) Fifth invention
The video display device according to a fifth aspect of the present invention is the video display device according to the fourth aspect, further comprising a correction amount storage unit that stores an input correction amount, and wherein the clock modulation unit stores the correction amount in the correction amount storage unit. The frequency of the second clock signal generated by the second clock generation means is modulated based on the stored correction amount.
[0022]
In this case, the frequency of the second clock signal is modulated based on the correction amount stored in the correction amount storage unit. Therefore, by correcting the correction amount stored in the correction amount storage means, readjustment can be performed after correcting the zigzag vertical line failure.
[0023]
(6) Sixth invention
In the video display device according to a sixth aspect, in the configuration of the video display device according to any one of the first to fifth aspects, the processing means generates a scan identification signal for identifying forward scan and backward scan. Scanning identification generating means, an area identification signal generating means for generating an area identification signal for identifying the first area and the second area, and a scanning identification signal generated by the scanning identification signal generating means at the time of adjustment. Displaying pixels based on the video signal of the outward scanning line and displaying pixels based on the video signal of the returning scanning line in the first area on the screen based on the area identification signal generated by the identification signal generating means. In the second area adjacent to the first area in the vertical direction, pixels based on the video signal of the backward scan line are displayed and read out from the storage means so as not to display the pixels based on the video signal of the forward scan line. Video It is intended to include a video signal processing means for processing the issue.
[0024]
In this case, a scan identification signal for identifying the forward scan and the return scan is generated by the scan identification generator, and an area identification signal for identifying the first area and the second area is generated by the area identification signal generator. Then, based on the scanning identification signal and the area identification signal, pixels based on the video signal of the outward scanning line are displayed in the first area on the screen, and pixels based on the video signal of the returning scanning line are not displayed. In the second area, pixels based on the video signal of the backward scanning line are displayed, and pixels based on the video signal of the outward scanning line are not displayed. Thus, the first area and the second area can be arbitrarily changed by the area identification signal. Therefore, it is possible to perform adjustment in correcting the zigzag vertical line failure at an arbitrary position on the screen.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a video display device according to an embodiment of the present invention will be described.
[0026]
FIG. 1 is a block diagram showing a configuration of a video display device according to one embodiment of the present invention.
[0027]
1 includes a video signal processing circuit 1, a color signal processing circuit 2, a synchronization signal separation circuit 3, a vertical deflection circuit 4, a horizontal deflection circuit 5, and a cathode ray tube (hereinafter, referred to as a CRT) 6. A vertical deflection yoke LV of the vertical deflection circuit 4 and a horizontal deflection yoke LH of the horizontal deflection circuit 5 are attached to the CRT 6.
[0028]
The video signal TV is input to the video signal processing circuit 1 and the synchronization signal separation circuit 3 in FIG.
[0029]
The synchronization signal separation circuit 3 separates a vertical synchronization signal V and a horizontal synchronization signal H from the input video signal TV. The synchronization signal separation circuit 3 supplies the separated vertical synchronization signal V and horizontal synchronization signal H to the video signal processing circuit 1. The synchronization signal separation circuit 3 supplies the separated vertical synchronization signal V to the vertical deflection circuit 4 and supplies the separated horizontal synchronization signal H to the horizontal deflection circuit 5.
[0030]
The shift amount ZR and the reciprocating mask area information MI are input to the video signal processing circuit 1 from outside (for example, an operator). The video signal processing circuit 1 receives an input video according to a vertical synchronization signal V and a horizontal synchronization signal H supplied from the synchronization signal separation circuit 3 and a scanning shift amount ZR and reciprocating mask area information MI input from outside. The processing described later is performed on the signal TV, and the processed video signal VM is supplied to the color signal processing circuit 2. The details of the video signal processing circuit 1 will be described later.
[0031]
The color signal processing circuit 2 separates a color difference signal (I, Q) and a luminance signal Y from the video signal VM given from the video signal processing circuit 1, and further separates the color signal from the color difference signal (I, Q) and the luminance signal Y. Is reproduced and given to the CRT 6 as a display signal Vo.
[0032]
The vertical deflection circuit 4 supplies a vertical deflection current to the vertical deflection yoke LV attached to the CRT 6 using the vertical synchronization signal V given from the synchronization signal separation circuit 3. On the other hand, the horizontal deflection circuit 5 supplies a horizontal deflection current to the horizontal deflection yoke LH attached to the CRT 6 according to the horizontal synchronization signal H given from the synchronization signal separation circuit 3.
[0033]
In the CRT 6, the electron beam is scanned by the function of the vertical deflection yoke LV of the vertical deflection circuit 4 and the horizontal deflection yoke LH of the horizontal deflection circuit 5, and an image based on the primary color signal Vo given by the color signal processing circuit 2 is displayed. .
[0034]
Next, details of the video signal processing circuit 1 of FIG. 1 will be described. FIG. 2 is a block diagram showing a configuration of the video signal processing circuit 1 of FIG.
[0035]
The video signal processing circuit 1 shown in FIG. 2 includes a first PLL (Phase Lock Loop) circuit 21, a second PLL (Phase Lock Loop) circuit 22, a clock modulation circuit 23, and an A / D. (Analog / digital) converter 24, memory 25, first scanning line identity control circuit 26, write control circuit 27, readout control circuit 28, video mask circuit 29, second scanning line identity control circuit 30, D / A (digital (Analog) converter 31, a shift amount setting unit 32, a shift amount storage unit 33, and a clock adjustment circuit 34.
[0036]
The horizontal synchronization signal H is input to the first PLL circuit 21 from the synchronization signal separation circuit 3 in FIG. The first PLL circuit 21 generates a first clock signal CK1 and a first horizontal synchronization signal H1 according to the horizontal synchronization signal H. The first horizontal synchronization signal H1 is output from a frequency divider (not shown) of the first PLL circuit 21. The first PLL circuit 21 supplies the generated first clock signal CK1 to the A / D converter 24 and the write control circuit 27, and supplies the first horizontal synchronization signal H1 to the first scan line identity control circuit 26 and the write It is given to the control circuit 27.
[0037]
On the other hand, the shift amount ZR of the reciprocating scanning is input to the shift amount setting unit 32 from the outside as a correction amount. The shift amount setting unit 32 gives the shift amount ZR to the shift amount storage unit 33. The shift amount storage unit 33 is composed of, for example, a non-volatile memory, and stores the shift amount ZR and provides the same to the clock modulation circuit 23.
[0038]
The clock modulation circuit 23 generates a modulation waveform TCK based on the shift amount ZR given from the shift amount storage unit 33.
[0039]
The second PLL circuit 22 is supplied with the horizontal synchronizing signal H from the synchronizing signal separation circuit 3 of FIG. 1 and the modulation waveform TCK from the clock modulation circuit 23.
[0040]
The second PLL circuit 22 generates a second clock signal CK2 and a second horizontal synchronization signal H2 from the horizontal synchronization signal H and the modulation waveform TCK. Here, the second PLL circuit 22 has a voltage-controlled oscillator, a division cycle, a phase comparator, a loop filter, and an adder. The output of the loop filter and the modulation waveform TCK are input to the adder, and the output of the adder is supplied to the voltage controlled oscillator. The second horizontal synchronization signal H2 is output from the frequency divider of the second PLL circuit 22.
[0041]
The second PLL circuit 22 supplies the generated second clock signal CK2 to the read control circuit 28 and the D / A converter 31, and also supplies the generated second horizontal synchronization signal H2 to the read control circuit 28.
[0042]
Further, the first scan line identity control circuit 26 generates a first identity control signal AS1 in response to the first horizontal synchronization signal H1 given from the first PLL circuit 21, and the write control circuit 27 and the read control Circuit 28 and a video mask circuit 29. Here, the first identity control signal AS1 is a signal for identifying whether each scanning line is a forward scanning line or a backward scanning line. For example, in the case of a forward scanning line, 1 is assigned. 0 in the case of the backward scanning line.
[0043]
The write control circuit 27 receives the first clock signal CK1 and the first horizontal synchronization signal H1 provided from the first PLL circuit 21 and the first identity control signal AS1 provided from the first scan line identity control circuit 26. In response, a write clock pulse WCK and a write address signal WAD are generated and applied to memory 25. The write control circuit 27 supplies the first horizontal synchronization signal H1 to the read control circuit 28.
[0044]
The read control circuit 28 includes a second clock signal CK2 and a second horizontal synchronization signal H2 supplied from the second PLL circuit 22, a first horizontal synchronization signal H1 supplied from the write control circuit 27, and a first scanning line identity. A read clock pulse RCK and a read address signal RAD are generated and supplied to the memory 25 in accordance with a first identity control signal AS1 supplied from the control circuit.
[0045]
On the other hand, the A / D converter 24 receives an analog video signal TV. The A / D converter 24 performs analog-to-digital conversion of the video signal TV according to the first clock signal CK <b> 1 supplied from the first PLL circuit 21, and supplies a digital video signal to the memory 25.
[0046]
The memory 25 stores the digital video signal supplied from the A / D converter 24 at the address specified by the write address signal WAD in response to the write clock pulse WCK supplied from the write control circuit 27, and In response to the applied read clock pulse RCK, a digital video signal is read from the address specified by the read address signal RAD and output to the video mask circuit 29.
[0047]
Here, the read control circuit 28 changes the read address signal RAD so that the relationship between the writing order and the reading order of the digital video signals in the memory 25 is inverted every horizontal scanning period. For example, in the forward horizontal scanning period, the digital video signal is read from the memory 25 in the same order as the writing order of the digital video signal to the memory 25. In the returning horizontal scanning period, the digital video signal is written to the memory 25. Digital video signals are read from the memory 25 in the reverse order. A specific example of the digital video signal read from the memory 25 will be described later.
[0048]
On the other hand, the second scanning line identity control circuit 30 is supplied with the vertical synchronizing signal V from the synchronizing signal separation circuit 3 of FIG. 1 and also receives reciprocating mask area information MI from outside. Here, the reciprocating mask area information MI is a signal indicating the ratio between the mask area of the forward scan line and the mask area of the backward scan line.
[0049]
The second scanning line identity control circuit 30 generates a second identity control signal AS2 based on the vertical synchronization signal V and the reciprocating mask area information MI, and provides the same to the video mask circuit 29. The second identity signal AS2 is a signal indicating the mask area of the forward scan line and the return scan line. For example, it is 1 in the case of the mask area of the forward scan line, and is 1 in the mask area of the forward scan line. In this case, it becomes 0.
[0050]
The video mask circuit 29 is provided from the memory 25 in response to a first identity control signal AS1 given from the first scanning line identity control circuit 26 and a second identity control signal AS2 given from the second scanning line identity control circuit 30. The supplied digital video signal is subjected to mask processing, and the digital video signal subjected to the mask processing is supplied to the D / A converter 31. Details of the mask processing of the video mask circuit 29 will be described later. The video mask circuit 29 is switched between activation and disabling by an activation signal ACT. For example, when the activation signal ACT is 1, the video mask circuit 29 is activated, and performs a mask process described later. On the other hand, when the activation signal ACT is 0, the video mask circuit 29 is disabled, and the digital video signal read from the memory 25 is output to the D / A converter 31 without performing mask processing. The activation signal ACT is set to 1 during the adjustment operation in the manufacturing process, and the activation signal ACT is fixed to 0 after the adjustment operation is completed.
[0051]
The D / A converter 31 performs digital-to-analog conversion of the digital video signal supplied from the video mask circuit 29 according to the second clock signal CK2 supplied from the second PLL circuit 22, and outputs an analog video signal VM. I do.
[0052]
Next, the operation of the video mask circuit 29 of FIG. 2 will be described in detail. FIG. 3 is a schematic diagram showing a part of a video signal in each section of the video signal processing circuit 1 of FIG.
[0053]
3A shows a part of a digital video signal written in the memory 25, FIG. 3B shows a digital video signal read from the memory 25, and FIG. 3C shows a first scanning line identity control circuit. FIG. 3D shows a first identification control signal AS2 generated by the second scanning line identification control circuit 30, and FIG. 3E shows an image. 4 shows a digital video signal masked by the mask circuit 29.
[0054]
First, the digital video signal written in the memory 25 in FIG. 2 is a 720-line video signal of the progressive scanning method. In the following description, the digital video signal of the 363th line is extracted from the digital video signal of the 356th line shown in FIG.
[0055]
In this example, the digital video signal of the even-numbered line is used as the digital video signal of the forward scan, and the digital video signal of the odd-numbered line is used as the digital video signal of the backward scan.
[0056]
As shown in FIG. 3A, the memory 25 stores a digital video signal 356T on the 356 line, a digital video signal 357R on the 357th line, a digital video signal 358T on the 358th line, and a digital video signal 359R on the 359th line. The digital video signal 360T on the 360th line, the digital video signal 361R on the 361th line, the digital video signal 362T on the 362th line, and the digital video signal 363R on the 363th line are written in this order.
[0057]
In FIG. 3B, “1” to “n” indicate the first to nth digital video signals of each line. That is, digital video signals are read in the order of the first to n-th in the even-numbered line, and digital video signals are read in the order of the n-th to the first in the odd-numbered line. For example, the video signal 356T on the 356th line is read out in the same order as the writing order, and the video signal 357R on the 357th line is read out in the reverse order to the writing order. Similarly, the digital video signals 358T, 360T, and 362T of the even lines are read in the same order as the writing order, and the digital video signals 357R, 359R, 361R, and 363R of the odd lines are read in the reverse order of the writing order. .
[0058]
Next, as shown in FIG. 3C, the first identity control signal AS1 indicates 1 in the case of forward scanning, and indicates 0 in the case of backward scanning.
[0059]
When the reciprocating mask area information MI is 1, the ratio of the mask area of the forward scan line to the mask area of the backward scan line is 1. Accordingly, in this example, as shown in FIG. 3D, the second scanning line identity signal AS2 is generated when the digital video signal of the 360th line is read from the digital video signal of the 0th line. It becomes 1 and becomes 0 when the digital video signal on the 720th line is read from the digital video signal on the 361th line.
[0060]
The video mask circuit 29 performs a masking process on the digital video signal read from the memory 25 based on the first identity control signal AS1 and the second identity control signal AS2 shown in FIGS. 3C and 3D. Is determined, and mask processing is performed according to the determination result.
[0061]
The video mask circuit 29 is formed of an exclusive OR circuit, and the value of the first identity control signal AS1 in FIG. 3C matches the value of the second identity control signal AS2 in FIG. 3D. The digital video signal read from the memory 25 is output to the memory 25. When the value of the first identity control signal AS1 and the value of the second identity control signal AS2 are different, the digital video signal read from the memory 25 is masked. . Here, the mask processing refers to outputting a black level value (for example, 0) without outputting a digital video signal read from the memory 25.
[0062]
For example, when the first identity control signal AS1 indicates 1 and the second identity control signal AS2 indicates 1, the video mask circuit 29 outputs the digital video signal read from the memory 25 as it is, and outputs the first identity control signal. When the control signal AS1 indicates 0 and the second identity control signal AS2 indicates 1, mask processing is performed on the digital video signal read from the memory 25. As a result, as shown in FIG. 3E, the digital video signal 356T of the 356th line, the digital video signal 358T of the 358th line, and the digital video signal 360T of the 360th line are subjected to D / A conversion without mask processing. The digital video signal 357R on the 357th line and the digital video signal 359R on the 359th line are masked and not supplied to the D / A converter 31.
[0063]
When the first ident control signal AS1 indicates 0 and the second ident control signal AS2 indicates 0, the video mask circuit 29 outputs the digital video signal read from the memory 25 as it is and performs the first ident control. When the signal AS1 indicates 1 and the second identity control signal AS2 indicates 0, mask processing is performed on the digital video signal read from the memory 25. As a result, as shown in FIG. 3E, the digital video signal 361R of the 361th line and the digital video signal 363R of the 363th line are output to the D / A converter 31 without being subjected to the mask processing, and are output to the 362th line. The digital video signal 362T is masked and is not output to the D / A converter 31.
[0064]
In this way, of the digital video signals from the 0th line to the 360th line, the digital video signal of the forward scan line is displayed on the screen, and the digital video signal of the return scan line is masked. On the other hand, of the digital video signals from the 361st line to the 720th line, the digital video signal of the outward scanning line is masked, and the digital video signal of the returning scanning line is displayed on the screen.
[0065]
Next, FIG. 4 is a diagram showing the adjustment of the correction amount of the zigzag vertical line failure when the mask processing by the video mask circuit 29 of FIG. 2 is not performed, and FIG. 5 is the mask processing by the video mask circuit 29 of FIG. FIG. 14 is a diagram showing adjustment of a correction amount of a zigzag vertical line obstacle when the correction is performed.
[0066]
FIG. 4 (a1) shows a state where an adjustment video signal having a predetermined value of adjustment pixel at the center of the video signal of each scanning line is displayed on the screen 500, and FIG. 4 (a2) shows the state of FIG. 4 (a1). FIG. 4B1 shows a state in which a part of the adjustment pixels displayed on the screen 500 is enlarged. FIG. 4B1 shows a state in which the correction amount of the zigzag vertical line failure is adjusted based on the adjustment video signal in FIG. FIG. 4B2 shows a state in which a part of the adjustment pixels displayed on the screen 500 of FIG. 4B1 is enlarged.
[0067]
On the other hand, FIG. 5 (a1) shows a state in which a masking process is performed on an adjustment video signal having a predetermined value of an adjustment pixel at the center of the digital video signal of each scanning line and displayed on the screen 500, and FIG. ) Shows a state in which a part of the adjustment pixels displayed on the screen 500 in FIG. 5A1 is enlarged, and FIG. 5B1 shows a zigzag vertical line based on the adjustment video signal in FIG. FIG. 5B2 shows a state where the correction amount of the obstacle is adjusted, and FIG. 5B2 shows a state where a part of the adjustment pixels displayed on the screen 500 of FIG. 5B1 is enlarged. 4 (a2) and 4 (b2) and FIGS. 5 (a2) and 5 (b2), black squares indicate adjustment pixels displayed on the screen 500, and white squares indicate adjustments not displayed on the screen 500 due to mask processing. 1 shows a pixel for use.
[0068]
When the mask processing is not performed, as shown in FIG. 4A1, the adjustment pixels are displayed by the zigzag line ZL due to the zigzag vertical line obstacle. In this case, as shown in FIG. 4 (a2), the adjustment pixels for the forward scan line and the adjustment pixels for the return scan line are displayed at positions shifted in the horizontal direction. The horizontal shift amount between the forward scan line adjustment pixel and the backward scan line adjustment pixel in the horizontal direction is dH. The worker in the manufacturing process sets the shift amount ZR input to the shift amount setting unit 32 in FIG. 2 so that the shift amount dH becomes 0 on the screen 500, as shown in FIGS. 4 (b1) and (b2). adjust. However, since the pixels for adjusting the forward scan line and the pixels for adjusting the backward scan line are alternately displayed, it is highly skilled in order to visually determine whether or not the shift amount dH is zero. And a long time is required for adjustment.
[0069]
On the other hand, when the mask processing is performed, as shown in FIG. 5A1, the adjustment pixels are displayed as two vertical lines TL and TR at positions shifted in the horizontal direction due to a zigzag vertical line obstacle. You. In this case, as shown in FIG. 5 (a2), only the pixels for adjustment of the forward scan line are displayed in the upper half of the screen 500 by mask processing, and the backward scan line is displayed in the lower half of the screen by mask processing. Only the adjustment pixels are displayed. As a result, the vertical line TL is displayed on the upper half of the screen 500 by the pixels for adjusting the forward scan line, and the vertical line RL is displayed on the lower half of the screen 500 by the pixels for adjusting the backward scan line. The ratio between the length of the vertical line TL and the length of the vertical line TR displayed on the screen 500 is determined by the reciprocating mask area information MI.
[0070]
The worker in the manufacturing process sets the shift amount ZR to be input to the shift amount setting unit 32 in FIG. 2 so that the shift amount dH becomes 0 on the screen 500 as shown in FIGS. 5 (a1) and (a2). adjust. In this case, the shift amount ZR is adjusted so that the lower end of the vertical line TL formed by the pixels for adjustment of the forward scan line and the upper end of the vertical line TR formed by the pixels for adjustment of the return scan line coincide with each other. Thus, the shift amount dH can be easily and accurately set to zero. Therefore, the zigzag vertical line failure can be corrected in a short time without requiring a high level of skill. As a result, manufacturing costs and manufacturing time are reduced.
[0071]
By changing the reciprocating mask area information MI, it is possible to change the ratio between the mask area of the forward scan line and the mask area of the backward scan line. As a result, it is possible to perform adjustment in correcting the zigzag vertical line failure at an arbitrary position on the screen.
[0072]
In the present embodiment, the memory 25 corresponds to a storage unit, the first PLL circuit 21 corresponds to a first clock generation unit, the second PLL circuit 22 corresponds to a second clock generation unit, The CRT 6 corresponds to a display unit, the clock modulation circuit 23 corresponds to a clock modulation unit, the video mask circuit 29 corresponds to a processing unit, the deviation amount ZR corresponds to an input correction amount, and the deviation amount storage unit 33 The first scanning line identity control circuit 26 corresponds to a scanning identification signal generation unit, the second scanning line identification control circuit 30 corresponds to a region identification signal generation unit, and the first identification control signal corresponds to a correction amount storage unit. AS1 corresponds to the scanning identification signal, and the second identity control signal AS2 corresponds to the area identification signal.
[0073]
【The invention's effect】
According to the present invention, when a vertical line is displayed on the screen, a linear vertical line is displayed in the first area by the forward scan, and a linear vertical line is displayed in the second area by the return scan. Is displayed. Therefore, based on the deviation between the end of the vertical line displayed in the first area and the end of the vertical line displayed in the second area, the display position of the pixel by the forward scan and the pixel by the backward scan are determined. Can be easily and accurately recognized. Therefore, the zigzag vertical line failure can be accurately corrected in a short time without requiring a high level of skill. As a result, manufacturing costs and manufacturing time are reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a video display device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a video signal processing circuit of FIG. 1;
FIG. 3 is a schematic diagram showing a part of a video signal in each section of the video signal processing circuit in FIG. 2;
FIG. 4 is a diagram showing adjustment of a correction amount of a zigzag vertical line defect when mask processing is not performed by the video mask circuit of FIG. 2;
FIG. 5 is a diagram showing adjustment of a correction amount of a zigzag vertical line defect when mask processing is performed by the video mask circuit of FIG. 2;
FIG. 6 is a diagram for explaining a temporal change of a horizontal deflection current flowing in a horizontal deflection coil.
FIG. 7 is a view for explaining a state of a display screen corresponding to the current waveform of the horizontal deflection current shown in FIG. 6;
[Explanation of symbols]
1 Video signal processing circuit
Two-color signal processing circuit
3 Synchronous signal separation circuit
4 Vertical deflection circuit
5 Horizontal deflection circuit
6 CRT (cathode ray tube)
21 1st PLL circuit
22 Second PLL circuit
23 Clock modulation circuit
24 A / D converter
25 memory
26 First Scan Line Identity Control Circuit
27 Write control circuit
28 Read control circuit
29 Image Mask Circuit
30 Second scan line identity control circuit
31 D / A converter
32 Shift amount setting section
33 shift amount storage unit

Claims (6)

An image display device that displays an image based on an image signal by reciprocating a scanning line on a screen,
Storage means for storing the video signal,
First clock generating means for generating a first clock signal for writing a video signal corresponding to forward and backward scanning to the storage means;
Second clock generation means for generating a second clock signal for reading out from the storage means a video signal corresponding to forward scan and return scan,
Display means for displaying the video signal as a video by irradiating the screen with an electron beam based on the video signal read from the storage means,
A horizontal deflection coil for horizontally reciprocatingly deflecting the electron beam of the display means to form forward and backward scanning lines on the screen;
The frequency of the second clock signal generated by the second clock generation unit is modulated in order to correct horizontal displacement of corresponding pixels on the forward scan line and the backward scan line on the screen. Clock modulation means;
At the time of adjustment, pixels based on the video signal of the outward scan line are displayed in the first area on the screen, and pixels based on the video signal of the backward scan line are not displayed. Processing means for processing a video signal read from the storage means so as to display pixels based on the video signal of the backward scanning line in the adjacent second area and not to display pixels based on the video signal of the outward scanning line; A video display device comprising: The processing means displays the video signal read when the video signal of the outward scanning line to be displayed in the first area on the screen is read from the storage means at the time of adjustment. And outputting a predetermined value to the display means when the video signal of the backward scanning line to be displayed in the first area on the screen is read from the storage means. When the video signal of the backward scanning line to be displayed in the second area on the screen is being read out, the read video signal is output to the display means, 2. The video display device according to claim 1, wherein a predetermined value is output to said display means when a video signal of a forward scanning line to be displayed in said second area is being read. 2. The video display device according to claim 1, wherein the processing unit is activated or disabled by a predetermined activation signal, and outputs the video signal read from the storage unit to the display unit when the processing unit is disabled. . 4. The clock modulator according to claim 1, wherein the clock modulator modulates a frequency of the second clock signal generated by the second clock generator based on an input correction amount. The image display device according to the above. A correction amount storage unit that stores an input correction amount, wherein the clock modulation unit is configured to generate the second clock generated by the second clock generation unit based on the correction amount stored in the correction amount storage unit. 5. The video display device according to claim 4, wherein the frequency of the clock signal is modulated. The processing means includes:
Scanning identification signal generating means for generating a scanning identification signal for identifying forward scanning and backward scanning,
Area identification signal generation means for generating an area identification signal for identifying the first area and the second area;
At the time of adjustment, a video signal of a scanning line goes to the first area on the screen based on the scanning identification signal generated by the scanning identification signal generating means and the area identification signal generated by the area identification signal generating means. And displaying pixels based on the video signal of the backward scanning line in a second area adjacent to the first area in the vertical direction without displaying the pixel based on the video signal of the backward scanning line. 6. A video signal processing means for processing a video signal read from said storage means so as not to display a pixel based on a video signal of a forward scanning line. Video display device.

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