JP2004274077A5

JP2004274077A5 -

Info

Publication number: JP2004274077A5
Application number: JP2004144257A
Authority: JP
Filing date: 2004-05-14
Publication date: 2005-06-30

Claims

A semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs whose gate electrodes and drains are cross-connected,
An interlayer insulating film formed on the n-channel MISFET;
A conductive layer connecting the gate electrode and the drain, formed in a pair of connection holes extending from the gate electrode to the drain, a pair of conductive layers having a recess on the surface;
A capacitive insulating film formed on the conductive layer including the inside of the recess;
An upper electrode formed on the capacitive insulating film;
A semiconductor integrated circuit device comprising:

2. The semiconductor integrated circuit device according to claim 1, wherein a thickness of the capacitive insulating film is smaller than a depth of the recess.

2. The semiconductor integrated circuit according to claim 1, wherein the memory cell includes a pair of transfer n-channel MISFETs and a pair of load p-channel MISFETs in addition to the pair of n-channel MISFETs. apparatus.

The semiconductor integrated circuit device according to claim 1, wherein a power supply voltage is supplied to the upper electrode.

A memory cell having a pair of inverters composed of a pair of drive MISFETs and a pair of load MISFETs and a pair of transfer MISFETs, each gate electrode and drain of the pair of drive MISFETs being cross-connected. A semiconductor integrated circuit device comprising:
An interlayer insulating film formed on the driving MISFET;
A first conductive layer of the pair of connecting the gate electrode and the drain, wherein are formed in a pair of connection hole extending from the gate electrode to the drain, the first conductive pair having a recess on its surface Layers,
A capacitive insulating film formed on the conductive layer including the inside of the recess;
An upper electrode formed on the capacitor insulating film,
The semiconductor integrated circuit device characterized in that it comprises a.

The semiconductor integrated circuit device further includes a pair of second conductive layers electrically connected to the source of the load MISFET,
The capacitive insulating film has a pair of openings,
6. The semiconductor integrated circuit device according to claim 5, wherein the upper electrode is electrically connected to the pair of second conductive layers through the pair of openings.

In the semiconductor integrated circuit device,
6. The semiconductor integrated circuit device according to claim 5, wherein the pair of first conductive layers protrude above the main surface of the interlayer insulating film.

In the semiconductor integrated circuit device, a plurality of memory cells are arranged in a first direction in which wirings connected to the cross-connecting portion via other n-channel MISFETs extend and in a second direction orthogonal thereto. A memory cell array disposed;
2. The semiconductor integrated circuit device according to claim 1, wherein the upper electrode is connected along the first direction, but is divided for each memory cell arranged in the second direction.

A method for manufacturing a semiconductor integrated circuit device having a memory cell having a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected to each other,
(A) forming the n-channel MISFET;
(B) forming an interlayer insulating film on the n-channel MISFET;
(C) forming a pair of connection holes extending from the gate electrode to the drain of the n-channel MISFET;
(D) depositing a conductive film on the interlayer insulating film including the inside of the pair of connection holes, and depositing a conductive film having a film thickness smaller than the radius of the pair of connection holes;
(E) forming the conductive layer embedded in the pair of connection holes by polishing the conductive film until the surface of the interlayer insulating film is exposed;
(F) forming a capacitive insulating film on the conductive layer;
(G) forming an upper electrode on the capacitive insulating film;
A method for manufacturing a semiconductor integrated circuit device, comprising:

10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the thickness of the capacitive insulating film is smaller than the depth of the recess.

The memory cell includes a pair of transfer n-channel MISFETs and a pair of p-channel load MISFETs in addition to the pair of n-channel MISFETs.
10. The semiconductor integrated circuit device according to claim 9, wherein the conductive layer extends to a drain of any one of the pair of p-channel load MISFETs. Production method.

The method for manufacturing the semiconductor integrated circuit device further includes:
Forming another interlayer insulating film on the upper electrode;
Forming another connection hole by selectively removing the other interlayer insulating film and the upper electrode;
Forming a plug by embedding a conductive material in the other connection hole;
10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, further comprising:

The method for manufacturing the semiconductor integrated circuit device includes:
Forming an opening by selectively removing the capacitive insulating film after forming the capacitive insulating film and before forming the upper electrode;
Forming an upper electrode on the capacitive insulating film including in the opening;
Forming another interlayer insulating film on the upper electrode;
Forming another connection hole by selectively removing the other interlayer insulating film;
Forming a plug by embedding a conductive material in the other connection hole;
10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, further comprising:

A method for manufacturing a semiconductor integrated circuit device having a memory cell having a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected to each other,
(A) forming an interlayer insulating film on the pair of n-channel MISFETs;
(B) a first connection hole extending from the gate electrode of one n-channel MISFET to the drain of the other n-channel MISFET of the pair of n-channel MISFETs, and the gate of the other n-channel MISFET Forming a second connection hole extending from above the electrode to the drain of one n-channel MISFET;
(C) depositing a conductive film having a thickness smaller than the radius of the connection hole on the interlayer insulating film including the inside of the first and second connection holes;
(D) first and second conductive layers embedded in the first and second connection holes by polishing the conductive film until the surface of the interlayer insulating film is exposed; Forming first and second conductive layers having recesses on top;
(E) forming a capacitive insulating film on each of the first and second conductive layers;
(F) forming an opening by selectively removing the capacitive insulating film on the first conductive layer;
(G) forming an upper electrode on the capacitive insulating film including the inside of the opening;
A method for manufacturing a semiconductor integrated circuit device, comprising:

In the semiconductor integrated circuit device, a plurality of memory cells are arranged in a first direction in which wirings connected to the cross-connecting portion via other n-channel MISFETs extend and in a second direction orthogonal thereto. A memory cell array disposed;
10. The semiconductor integrated circuit device according to claim 9, wherein the upper electrode is connected along the first direction, but is divided for each memory cell arranged in the second direction. Production method.

6. The semiconductor integrated circuit device according to claim 1, wherein the memory cell is an SRAM memory cell.

15. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the memory cell is an SRAM memory cell.

6. The semiconductor integrated circuit device according to claim 5, wherein the pair of drive MISFETs and transfer MISFETs are n-channel MISFETs, and the load MISFETs are p-channel MISFETs.