JP2004273904A - Semiconductor device and wire bonding method - Google Patents

Semiconductor device and wire bonding method Download PDF

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Publication number
JP2004273904A
JP2004273904A JP2003064867A JP2003064867A JP2004273904A JP 2004273904 A JP2004273904 A JP 2004273904A JP 2003064867 A JP2003064867 A JP 2003064867A JP 2003064867 A JP2003064867 A JP 2003064867A JP 2004273904 A JP2004273904 A JP 2004273904A
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Prior art keywords
wire
bond point
bump
bond
bonding method
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Yoshihito Hagiwara
美仁 萩原
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Shinkawa Ltd
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Shinkawa Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/4848—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
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    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To make realizable the prevention of a short circuit due to sagging of a wire loop at a low cost. <P>SOLUTION: In a semiconductor device in which a pad 2a, which is a first bonding point 3 of a semiconductor chip 2 fixed on a lead frame 1, and a second bonding point 4 of a lead 1a of the lead frame 1 are electrically connected by a wire 5, a bump 6 is provided from the second bonding point 4 to the semiconductor chip 2 side by a wire bonding method. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、回路基板上に固定された半導体チップの電極と、回路基板上に配設された配線パターンの配線とを、ワイヤにより電気的に接続してなる半導体装置及びワイヤボンディング方法に関する。
【０００２】
【従来の技術】
半導体装置においては、半導体チップと配線パターンの所望の配線とを電気的に接続したワイヤが他の配線ににショートするのを防止し、またワイヤループの垂れや変形に起因する電気的なショートを防止する必要がある。特に、積層された半導体チップにおける多層ワイヤ、低ワイヤループ、第１ボンド点と第２ボンド点が長い長ワイヤループ、ワイヤが他のワイヤを跨いでいる場合等においては、ワイヤ垂れが生じ易い。
【０００３】
従来は、リードフレームのダイパッド上に半導体チップを囲むように全面に絶縁ブロックを設け、この絶縁ブロックによってワイヤループの弛みを防止している（例えば、特許文献１参照）。また、回路基板上に配設された配線パターンの複数種類の配線間に、これらの配線より高さが高い絶縁体を設け、この絶縁体によってワイヤループの弛みを防止している（例えば、特許文献２参照）。
【０００４】
なお、本発明の要旨とは異なるが、バンプ形成方法として例えば特許文献３及び４等が挙げられる。
【０００５】
【特許文献１】
特開平５−１０２２２４号公報
【特許文献２】
特開平１１−１２１５００号公報
【特許文献３】
特公平６−９５４６８号公報
【特許文献４】
特開平８−２６４５４０号公報（特許第２７３５０２２号公報）
【０００６】
【発明が解決しようとする課題】
特許文献１及び２は、いずれも基板上に絶縁体を設けており、絶縁体はワイヤボンディング前に別工程で設ける必要があり、コスト高になるという問題があった。
【０００７】
本発明の第１の課題は、ワイヤループの垂れによるショートの防止を低コストで実現できる半導体装置及びワイヤボンディング方法を提供することにある。
【０００８】
本発明の第２の課題は、樹脂封止の際に接続されたワイヤの流動変形によるワイヤ同士のショートを防止することができる半導体装置及びワイヤボンディング方法を提供することにある。
【０００９】
【課題を解決するための手段】
上記第１の課題を解決するための本発明の請求項１は、回路基板上に固定された半導体チップの第１ボンド点である電極と、回路基板上に配設された配線パターンの配線の第２ボンド点とを、ワイヤにより電気的に接続してなる半導体装置において、前記第２ボンド点より前記半導体チップ側にワイヤボンディング方法によってバンプを設けたことを特徴とする。
【００１０】
上記第１の課題を解決するための本発明の請求項２は、回路基板上に固定された半導体チップの第１ボンド点である電極上に１次ボンディングを行った後、ワイヤをルーピングして回路基板上に配設された配線パターンの配線の第２ボンド点に２次ボンディングを行い、前記第１ボンド点と前記第２ボンド点間をワイヤにより電気的に接続するワイヤボンディング方法において、前記第２ボンド点より前記半導体チップ側にワイヤボンディング方法によってバンプを形成した後、前記１次ボンディングを行い、次に前記２次ボンディングを行うことを特徴とする。
【００１１】
上記第１の課題を解決するための本発明の請求項３は、上記請求項２において、ワイヤループの垂れ下がりを防止する必要がある第２ボンド点に対して全て又は複数個前記バンプを形成した後、この形成されたバンプに対応する第２ボンド点と、この第２ボンド点に対応する前記第１ボンド点に対して前記１次ボンディング及び前記２次ボンディングを行うことを特徴とする。
【００１２】
上記第１の課題を解決するための本発明の請求項４は、上記請求項２において、１個の前記バンプを形成した後、続いて該バンプに対応する第２ボンド点と、この第２ボンド点に対応する前記第１ボンド点に対して前記１次ボンディング及び前記２次ボンディングを行うことを特徴とする。
【００１３】
上記第１の課題を解決するための本発明の請求項５は、上記請求項１又は２において、前記バンプは、前記第２ボンド点の直前に設けられていることを特徴とする。
【００１４】
上記第１及び第２の課題を解決するための本発明の請求項６は、上記請求項１又は２において、前記バンプ上に上方に突出した突出部を形成し、前記ワイヤは前記突出部より樹脂流入側にルーピングされていることを特徴とする。
【００１５】
【発明の実施の形態】
図１は、本発明の第１の実施の形態を示す半導体装置で、回路基板がリードフレームである場合を示す。リードフレーム１上には、パッド２ａが形成された半導体チップ２がマウントされている。第１ボンド点３であるパッド２ａとリードフレーム１の配線であるリード１ａの第２ボンド点４とは、ワイヤ５によって電気的に接続されている。本実施の形態においては、第２ボンド点４より半導体チップ２側のリード１ａ上にはワイヤボンディング方法によってバンプ６が設けられている。
【００１６】
図２は、本発明の第２の実施の形態を示す半導体装置で、回路基板がセラミック基板やプリント基板等の基板である場合を示す。基板７上には、パッド２ａが形成された半導体チップ２がマウントされている。また基板７には配線８が形成されている。本実施の形態においても前記実施の形態と同様に、第１ボンド点３であるパッド２ａと配線８の第２ボンド点４とは、ワイヤ５によって電気的に接続されている。また第２ボンド点４より半導体チップ２側の基板７上にはワイヤボンディング方法によってバンプ６が設けられている。
【００１７】
次に図１及び図２に示す半導体装置のワイヤボンディング方法について説明する。図１の場合は、リード１ａの第２ボンド点４より半導体チップ２側のリード１ａ上に、図２の場合は、配線８の第２ボンド点４より半導体チップ２側の基板７上に、ワイヤボンディング方法によってバンプ６を形成する。次にワイヤボンディング方法によって第１ボンド点３に１次ボンディングを行った後、ワイヤ５をルーピングして第２ボンド点４に２次ボンディングを行い、第１ボンド点３と第２ボンド点４間をワイヤ５により電気的に接続する。
【００１８】
このように、第２ボンド点４より半導体チップ２側にはバンプ６が形成されているので、第２ボンド点４側のワイヤ５はバンプ６によって持ち上げられ、ワイヤ５の垂れによるショートが防止され、半導体装置としての信頼性が向上する。
またバンプ６の形成及びワイヤ５の接続は、ワイヤボンディング方法の一連の工程によって行うことができるので、コスト低減が図れる。
【００１９】
前記バンプ６の形状は特に限定されるものではなく、例えば図３に示すような種々の形状のものでもよい。図３（ａ）は、一般的なバンプ形状のものを示す。
図３（ｂ）は、バンプ６ａ上にバンプ６ｂを形成した２段バンプ６を示す。勿論、３段以上のバンプを形成してもよい。このような２段以上のバンプ６は、例えば従来の技術の項で挙げた特許文献４の方法によって形成することができる。図３（ｃ）は、バンプ６の上部にテール６ｃを形成した場合を示す。図３（ｄ）及び図３（ｅ）は、バンプ６上に湾曲形状の頂部６ｄを形成した場合を示す。このようなバンプ６は、例えば従来の技術の項で挙げた特許文献３の方法によって形成することができる。
【００２０】
図３（ｃ）、図３（ｄ）、図３（ｅ）に示すように、バンプ６上に上方に突出したテール６ｃ、頂部６ｄ等の突出部を形成した場合には、ワイヤ５をテール６ｃ又は頂部６ｄより樹脂封止の際の樹脂流入側にルーピングすると、樹脂流動によるワイヤ５の変形は、テール６ｃまたは頂部６ｄによって受けられ、ワイヤ５の変形が抑えられる。またワイヤ５に加わる樹脂流動力は、テール６ｃ、頂部６ｄで受けられるので、樹脂流動力によって第２ボンド点４よりワイヤ５を剥離させる力が減殺され、更に信頼性が向上する。
【００２１】
【発明の効果】
本発明は、回路基板上に固定された半導体チップの第１ボンド点である電極と、回路基板上に配設された配線パターンの配線の第２ボンド点とを、ワイヤにより電気的に接続してなる半導体装置において、前記第２ボンド点より前記半導体チップ側にワイヤボンディング方法によってバンプを設けたので、前記バンプの形成及び前記ワイヤの接続を一連のワイヤボンディング方法によって行うことができ、ワイヤループの垂れによるショートの防止を低コストで実現できる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態の半導体装置を示す正面図である。
【図２】本発明の第２の実施の形態の半導体装置を示す正面図である。
【図３】バンプ形状を示す正面図である。
【符号の説明】
１ リードフレーム
１ａ リード
２ 半導体チップ
２ａ パッド
３ 第１ボンド点
４ 第２ボンド点
５ ワイヤ
６、６ａ、６ｂ バンプ
６ｃ テール
６ｄ 頂部
７ 基板
８ 配線[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a wire bonding method in which an electrode of a semiconductor chip fixed on a circuit board and a wiring of a wiring pattern arranged on the circuit board are electrically connected by a wire.
[0002]
[Prior art]
In a semiconductor device, a wire that electrically connects a semiconductor chip and a desired wiring of a wiring pattern is prevented from being short-circuited to other wiring, and an electrical short circuit caused by drooping or deformation of a wire loop is prevented. There is a need to prevent. In particular, wire sagging is likely to occur in multilayered semiconductor chips, such as multilayer wires, low wire loops, long wire loops with long first and second bond points, and wires straddling other wires.
[0003]
Conventionally, an insulating block is provided on the entire surface so as to surround a semiconductor chip on a die pad of a lead frame, and the loosening of the wire loop is prevented by this insulating block (see, for example, Patent Document 1). In addition, an insulator having a height higher than these wirings is provided between a plurality of types of wirings arranged on the circuit board, and the wire loop is prevented from slacking by this insulator (for example, patents) Reference 2).
[0004]
Although different from the gist of the present invention, Patent Documents 3 and 4, for example, can be cited as bump forming methods.
[0005]
[Patent Document 1]
Japanese Patent Laid-Open No. 5-102224 [Patent Document 2]
Japanese Patent Laid-Open No. 11-121500 [Patent Document 3]
Japanese Patent Publication No. 6-95468 [Patent Document 4]
JP-A-8-264540 (Patent No. 2735022)
[0006]
[Problems to be solved by the invention]
In each of Patent Documents 1 and 2, an insulator is provided on a substrate, and the insulator needs to be provided in a separate process before wire bonding, which increases the cost.
[0007]
SUMMARY OF THE INVENTION A first object of the present invention is to provide a semiconductor device and a wire bonding method capable of realizing a short circuit prevention due to a droop of a wire loop at a low cost.
[0008]
A second object of the present invention is to provide a semiconductor device and a wire bonding method capable of preventing short-circuiting of wires due to flow deformation of wires connected during resin sealing.
[0009]
[Means for Solving the Problems]
According to a first aspect of the present invention for solving the first problem, an electrode which is a first bond point of a semiconductor chip fixed on a circuit board, and wiring of a wiring pattern disposed on the circuit board are provided. In a semiconductor device in which a second bond point is electrically connected by a wire, a bump is provided on the semiconductor chip side from the second bond point by a wire bonding method.
[0010]
According to a second aspect of the present invention for solving the first problem, a wire is looped after primary bonding is performed on an electrode which is a first bond point of a semiconductor chip fixed on a circuit board. In the wire bonding method of performing secondary bonding on the second bond point of the wiring of the wiring pattern disposed on the circuit board, and electrically connecting the first bond point and the second bond point with a wire, A bump is formed on the semiconductor chip side from the second bond point by a wire bonding method, the primary bonding is performed, and then the secondary bonding is performed.
[0011]
According to a third aspect of the present invention for solving the first problem, in the second aspect, all or a plurality of the bumps are formed for the second bond points where it is necessary to prevent the wire loop from drooping. Thereafter, the primary bonding and the secondary bonding are performed on a second bond point corresponding to the formed bump and the first bond point corresponding to the second bond point.
[0012]
According to a fourth aspect of the present invention for solving the first problem, in the second aspect, after forming the one bump, a second bond point corresponding to the bump, and a second bond point. The primary bonding and the secondary bonding are performed on the first bond point corresponding to the bond point.
[0013]
A fifth aspect of the present invention for solving the first problem is characterized in that in the first or second aspect, the bump is provided immediately before the second bond point.
[0014]
According to a sixth aspect of the present invention for solving the first and second problems, in the first or second aspect, a protruding portion protruding upward is formed on the bump, and the wire is formed from the protruding portion. It is characterized by being looped on the resin inflow side.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a semiconductor device according to a first embodiment of the present invention, in which a circuit board is a lead frame. On the lead frame 1, a semiconductor chip 2 on which pads 2a are formed is mounted. A pad 2 a that is the first bond point 3 and a second bond point 4 of the lead 1 a that is the wiring of the lead frame 1 are electrically connected by a wire 5. In the present embodiment, bumps 6 are provided on the lead 1a on the semiconductor chip 2 side from the second bond point 4 by a wire bonding method.
[0016]
FIG. 2 shows a semiconductor device according to the second embodiment of the present invention, in which the circuit board is a board such as a ceramic board or a printed board. On the substrate 7, the semiconductor chip 2 on which the pads 2a are formed is mounted. A wiring 8 is formed on the substrate 7. Also in the present embodiment, the pad 2a as the first bond point 3 and the second bond point 4 of the wiring 8 are electrically connected by the wire 5 as in the above embodiment. A bump 6 is provided on the substrate 7 on the semiconductor chip 2 side from the second bond point 4 by a wire bonding method.
[0017]
Next, a wire bonding method for the semiconductor device shown in FIGS. 1 and 2 will be described. In the case of FIG. 1, on the lead 1a on the semiconductor chip 2 side from the second bond point 4 of the lead 1a, in the case of FIG. 2, on the substrate 7 on the semiconductor chip 2 side from the second bond point 4 of the wiring 8. Bumps 6 are formed by a wire bonding method. Next, after the primary bonding is performed to the first bond point 3 by the wire bonding method, the wire 5 is looped to perform the secondary bonding to the second bond point 4, and between the first bond point 3 and the second bond point 4. Are electrically connected by a wire 5.
[0018]
Thus, since the bump 6 is formed on the semiconductor chip 2 side from the second bond point 4, the wire 5 on the second bond point 4 side is lifted by the bump 6, and a short circuit due to the drooping of the wire 5 is prevented. The reliability as a semiconductor device is improved.
Further, the formation of the bump 6 and the connection of the wire 5 can be performed by a series of steps of the wire bonding method, so that the cost can be reduced.
[0019]
The shape of the bump 6 is not particularly limited, and may be various shapes as shown in FIG. FIG. 3A shows a general bump shape.
FIG. 3B shows the two-step bump 6 in which the bump 6b is formed on the bump 6a. Of course, three or more bumps may be formed. Such two or more bumps 6 can be formed, for example, by the method of Patent Document 4 mentioned in the section of the prior art. FIG. 3C shows a case where the tail 6 c is formed on the bump 6. FIG. 3D and FIG. 3E show the case where a curved top portion 6 d is formed on the bump 6. Such a bump 6 can be formed, for example, by the method of Patent Document 3 mentioned in the section of the prior art.
[0020]
As shown in FIG. 3C, FIG. 3D, and FIG. 3E, when protruding portions such as a tail 6c and a top portion 6d that protrude upward are formed on the bump 6, the wire 5 is connected to the tail. When looping from 6c or top portion 6d to the resin inflow side during resin sealing, deformation of wire 5 due to resin flow is received by tail 6c or top portion 6d, and deformation of wire 5 is suppressed. Further, since the resin flow force applied to the wire 5 is received by the tail 6c and the top portion 6d, the force for peeling the wire 5 from the second bond point 4 is reduced by the resin flow force, and the reliability is further improved.
[0021]
【The invention's effect】
The present invention electrically connects an electrode, which is a first bond point of a semiconductor chip fixed on a circuit board, and a second bond point of a wiring of a wiring pattern disposed on the circuit board by a wire. In the semiconductor device, the bump is provided on the semiconductor chip side from the second bond point by the wire bonding method, so that the formation of the bump and the connection of the wire can be performed by a series of wire bonding methods. Prevention of short circuit due to sagging can be realized at low cost.
[Brief description of the drawings]
FIG. 1 is a front view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a front view showing a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a front view showing a bump shape.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Lead frame 1a Lead 2 Semiconductor chip 2a Pad 3 1st bond point 4 2nd bond point 5 Wire 6, 6a, 6b Bump 6c Tail 6d Top part 7 Substrate 8 Wiring

Claims (6)

回路基板上に固定された半導体チップの第１ボンド点である電極と、回路基板上に配設された配線パターンの配線の第２ボンド点とを、ワイヤにより電気的に接続してなる半導体装置において、前記第２ボンド点より前記半導体チップ側にワイヤボンディング方法によってバンプを設けたことを特徴とする半導体装置。A semiconductor device in which an electrode, which is a first bond point of a semiconductor chip fixed on a circuit board, and a second bond point of a wiring pattern arranged on the circuit board are electrically connected by a wire And a bump is provided on the semiconductor chip side from the second bond point by a wire bonding method. 回路基板上に固定された半導体チップの第１ボンド点である電極上に１次ボンディングを行った後、ワイヤをルーピングして回路基板上に配設された配線パターンの配線の第２ボンド点に２次ボンディングを行い、前記第１ボンド点と前記第２ボンド点間をワイヤにより電気的に接続するワイヤボンディング方法において、前記第２ボンド点より前記半導体チップ側にワイヤボンディング方法によってバンプを形成した後、前記１次ボンディングを行い、次に前記２次ボンディングを行うことを特徴とするワイヤボンディング方法。After the primary bonding is performed on the electrode, which is the first bond point of the semiconductor chip fixed on the circuit board, the wire is looped to the second bond point of the wiring pattern arranged on the circuit board. In the wire bonding method in which secondary bonding is performed and the first bond point and the second bond point are electrically connected by a wire, bumps are formed on the semiconductor chip side from the second bond point by the wire bonding method. Thereafter, the primary bonding is performed, and then the secondary bonding is performed. ワイヤループの垂れ下がりを防止する必要がある第２ボンド点に対して全て又は複数個前記バンプを形成した後、この形成されたバンプに対応する第２ボンド点と、この第２ボンド点に対応する前記第１ボンド点に対して前記１次ボンディング及び前記２次ボンディングを行うことを特徴とする請求項２記載のワイヤボンディング方法。After all or a plurality of the bumps are formed with respect to the second bond points that need to prevent the wire loop from sagging, the second bond points corresponding to the formed bumps and the second bond points correspond to the second bond points. The wire bonding method according to claim 2, wherein the primary bonding and the secondary bonding are performed on the first bond point. １個の前記バンプを形成した後、続いて該バンプに対応する第２ボンド点と、この第２ボンド点に対応する前記第１ボンド点に対して前記１次ボンディング及び前記２次ボンディングを行うことを特徴とする請求項２記載のワイヤボンディング方法。After forming the one bump, the primary bonding and the secondary bonding are subsequently performed on the second bond point corresponding to the bump and the first bond point corresponding to the second bond point. The wire bonding method according to claim 2. 前記バンプは、前記第２ボンド点の直前に設けられていることを特徴とする請求項１又は２記載の半導体装置又はワイヤボンディング方法。The semiconductor device or the wire bonding method according to claim 1, wherein the bump is provided immediately before the second bond point. 前記バンプ上に上方に突出した突出部を形成し、前記ワイヤは前記突出部より樹脂流入側にルーピングされていることを特徴とする請求項１又は２記載の半導体装置又はワイヤボンディング方法。3. A semiconductor device or a wire bonding method according to claim 1, wherein a protruding portion protruding upward is formed on the bump, and the wire is looped from the protruding portion to the resin inflow side.
JP2003064867A 2003-03-11 2003-03-11 Semiconductor device and wire bonding method Withdrawn JP2004273904A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012174776A (en) * 2011-02-18 2012-09-10 Mitsubishi Electric Corp Semiconductor device for electric power

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012174776A (en) * 2011-02-18 2012-09-10 Mitsubishi Electric Corp Semiconductor device for electric power

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