JP2004272241A - Focus detecting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To hold a proper integral value of a CCD line sensor nearly constant irrelevantly to subject luminance by a focus detecting device equipped with the CCD line sensor. <P>SOLUTION: There are provided a plurality of line sensors I1 to I10, monitor sensors M1 to M10 which are provided adjacently to reference areas I1a to I10a of the respective line sensors I1 to I10 and monitor the amount of light received by adjacent reference areas I1a to I10a, an AGC circuit which amplifies and outputs outputs of the respective monitor sensors M1 to M10 as monitor signals, and ends integration of line sensors I1 to I10 corresponding to monitor sensors M1 to M10 when monitor signals reach a given end value, and a CPU which performs logarithmic compression of each integration time during integration of the line sensors I1 to I10 and controls the gain level of each AGC circuit according to the logarithmically compressed integration time. The CPU adjusts the gain level of the AGC circuit so that proper integral values of the line sensors I1 to I10 when monitor signals reach the given end value are substantially a given value irrelevantly to the integration time. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a focus detection apparatus suitable for camera focus detection.

A conventional AF single-lens reflex camera is equipped with a focus detection device including a phase difference type CCD focus detection element. The CCD focus detection element includes a CCD optical sensor and a monitor sensor corresponding to a photographing optical system and a focus detection area. The monitor sensor receives subject light in substantially the same area as the adjacent CCD line sensor, outputs a monitor signal corresponding to the amount of received light, amplifies the monitor signal with an auto gain controller, and the amplified monitor signal is a predetermined signal. When the integration end value is reached, the integration of the corresponding CCD line sensor is ended (Patent Document).
JP 2000-035530

  However, it has been found that the integrated value of the CCD line sensor and the monitor output of the monitor sensor may not be linearly proportional. That is, it has been found that as the integration time becomes longer (the subject becomes darker), the proper integration value of the CCD line sensor becomes smaller than the monitor signal of the monitor sensor. In this state, in the case of high luminance, the integral value of the high luminance portion of the CCD line sensor exceeds the saturation integral value, and accurate phase difference measurement cannot be performed. On the other hand, in the case of low luminance, the integral value becomes smaller than the proper integral value, and the dynamic range of the CCD line sensor cannot be effectively used, and the contrast cannot be obtained. As described above, the conventional focus detection apparatus using the CCD line sensor may have a non-uniform output from the CCD line sensor due to the luminance of the subject, and may not be able to perform accurate measurement.

  The present invention has been made in view of the above-described conventional problems, and in a focus detection device equipped with a CCD line sensor, the proper integration value of the CCD line sensor can be maintained at a substantially constant value regardless of subject brightness. An object is to provide a focus detection device.

The focus detection apparatus of the present invention that achieves this object includes a plurality of line sensors that each have a plurality of pixels, photoelectrically convert and integrate subject light received by each pixel, and output as an image signal; A monitor sensor that is provided adjacent to the sensor and monitors the integrated value of the adjacent line sensor, and outputs the monitor sensor after amplifying the output of each monitor sensor, and when the monitor signal reaches a predetermined end value Control means for terminating the integration of the line sensor corresponding to the monitor sensor, and gain adjusting means for adjusting the gain level of each control means according to each integration time during the integration of the line sensor, The adjusting means is configured to control the control means so that an appropriate integrated value of the line sensor when the monitor signal reaches a predetermined end value becomes substantially a predetermined value regardless of an integration time. Characterized in that adjusting the gain level.
With this configuration, the proper integrated value of the line sensor can be kept substantially constant regardless of subject brightness and integration time. Therefore, the so-called effective dynamic range of the line sensor can be used efficiently even when the subject brightness is high or low.

  The gain adjusting means includes calculation means for calculating a correction value by using a logarithmically compressed integration time and a predetermined coefficient.

  After the control means causes the line sensor and the monitor sensor to start integration, the control means includes detection means for detecting that the amplified monitor signal has reached a predetermined end value for ending the integration of the line sensor. Then, the control means sends a first end signal from the first control terminal to the gain adjusting means when the detecting means detects that the monitor signal of any of the monitor sensors has reached the end value. Output, and then sequentially output the integration end information of each monitor sensor from the first control terminal to the gain adjustment unit, the gain adjustment unit measures the integration time based on the integration end information, The correction value is calculated.

  The focus detection apparatus may include a focus detection element including the line sensors, a monitor sensor, and a control unit, and the gain adjustment unit as separate bodies. In this case, the gain adjusting means can use the control means of the device on which the image sensor is mounted. When mounted on a camera, the camera control means can function as a gain adjustment means.

  As is apparent from the above description, the focus detection apparatus of the present invention is configured so that the gain adjustment means for adjusting the gain level of each auto gain controller according to each integration time during the integration of the line sensor has the monitor signal set to a predetermined end value. Since the gain level of the auto gain controller is adjusted so that the appropriate integral value of the line sensor when it reaches the predetermined value regardless of the integration time, a substantially constant appropriate value is obtained from each line sensor regardless of the subject brightness. An integral value is obtained.

  The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an outline of a single-lens reflex camera equipped with a CCD focus detection element of the present invention.

This AF single-lens reflex camera has a camera body 11 including an AF module (focus detection module) 60 having a CCD focus detection element 61 as a focus detection element, and an AF-compatible photographic lens 51 that can be attached to and detached from the camera body 11. And. The camera body 11 includes a main CPU 31 that collectively controls the camera body 11 and the photographing lens 51.

  Most of the subject luminous flux that has entered the camera body 11 from the photographic lens 51 is reflected by the main mirror 13 toward the pentaprism 17 constituting the finder optical system, is reflected by the pentaprism 17 and exits from the eyepiece. Part of the subject light beam emitted from the pentaprism 17 is incident on the light receiving element of the photometry IC 18. On the other hand, a part of the light beam incident on the half mirror portion 14 formed at the center portion of the main mirror 13 is transmitted through the half mirror portion 14 and reflected downward by the sub mirror 15 provided on the back surface of the main mirror 13, and AF The light enters the module 60.

  The photometric IC 18 inputs an electrical signal photoelectrically converted according to the amount of received light as a photometric signal to the main CPU 31 via the peripheral control circuit 21. The main CPU 31 performs a predetermined exposure calculation based on the photometric signal, film sensitivity information, and the like, and calculates an appropriate shutter speed and aperture value for exposure. Based on these shutter speeds and aperture values, the aperture mechanism 22 and the exposure mechanism 23 are driven to expose the film. Further, the peripheral control circuit 21 drives the mirror motor 25 through the motor drive circuit (moder IC) 24 to raise the main mirror 13 during the photographing process, and drives the mirror motor 25 after the exposure to main. The mirror 13 is lowered and the film winding motor 26 is driven to wind up the film by one frame.

  The AF module 60 is a so-called pupil division phase difference method, and includes a CCD focus detection element 61 having a plurality of CC line sensors and a focus detection surface equivalent to an imaging surface (not shown) as a plurality of focal points. An optical system is provided that divides a subject luminous flux that forms a subject image in a detection area into two and divides it into a corresponding line sensor. The CCD focus detection element 61 receives and integrates a pair of so-called pupil-divided subject luminous fluxes, and monitors a received light quantity of each line sensor I, that is, a monitor sensor M that checks an integrated value. It has. Each line sensor I and monitor sensor M is driven and controlled by a control circuit system provided in the CCD focus detection element 61. When the monitor voltage (output voltage) of the monitor sensor M reaches a predetermined threshold value, the control circuit system ends the integration of the line sensor I corresponding to the monitor sensor M. When the integration of all the line sensors I is finished, the electric charges integrated by the line sensors I are converted into voltages for each line sensor in units of pixels and output to the main CPU 31 as video signals in units of pixels.

  The main CPU 31 calculates a defocus amount by a predetermined calculation based on the image signal input from the AF module 60 (CCD focus detection element 61), and the rotation direction and the number of rotations of the AF motor 33 based on the calculated defocus amount. (The number of pulses output by the encoder 37) is calculated as the lens driving amount. The main CPU 31 drives the AF motor 33 via the AF motor driver 32 based on the rotation direction and the number of pulses. During this driving, the main CPU 31 counts the pulses output from the encoder 37 in conjunction with the rotation of the AF motor 33 by the counter 31d, and stops the AF motor 33 when the count value reaches the number of pulses.

  On the other hand, the photographic lens 51 is detachably attached to the lens CPU 57, a gear block 53 that drives the focus adjustment lens 52 in the optical axis direction, and the joint 35 of the camera body 11 provided in the mount portion of the photographic lens 51. A joint 55 for connection is provided. The rotation of the AF motor 33 is transmitted to the gear block 53 through the gear block 34 and the joints 35 and 55, and moves the focus adjustment lens group 52 forward and backward through the gear block 53.

  The main CPU 31 includes a ROM 31a storing a control program, a RAM 31b temporarily storing predetermined data for calculation and control, a timer 31c for counting, a counter 31d, and an AF module 60 (CCD focus detection element 61). An A / D converter 31e for A / D converting the input VOUT signal (image signal / Video signal) and a D / A converter 31f for D / A converting and outputting the VMS signal are incorporated, and the EEPROM 38 is an external memory means. Connected as. The EEPROM 38 stores various constants specific to the camera body 11, mode data related to the monitor sensor M and line sensor I used by the CCD focus detection element 61, and the like.

  Further, the main CPU 31 includes a main switch SWM for turning on / off the power, an auto focus switch SWAF for switching between auto focus control and manual focus control, a photometry switch SWS which is turned on between half-press of the release button and the release button. A release switch SWR that is turned on when the button is fully pressed is connected.

  When the photometric switch SWS is turned on, the main CPU 31 activates the photometric IC 18 via the peripheral control circuit 21 to measure the subject luminance and execute the exposure calculation, and activates the AF module 60 to activate a predetermined line sensor. Then, the integration signal is input, the defocus amount is calculated, the lens drive amount is calculated based on the defocus amount, and the AF motor 33 is driven by the calculated lens drive amount.

  The main CPU 31 displays the set AF, exposure, shooting mode, shutter speed, aperture value, and the like on the display 39. The display device 39 normally includes display panels provided at two locations within the outer surface of the camera body 11 and the viewfinder field of view.

  The lens CPU 57 is connected to the peripheral portion control circuit 21 of the camera body 11 through the connection of the electrical contact groups 56 and 36, and is opened to the main CPU 31 through the peripheral portion control circuit 21. Predetermined data communication such as maximum F value information, focal length information, and lens position (distance) information is performed.

  Next, details of the CCD focus detection element 61 mounted on the single-lens reflex camera will be described with reference to FIG. FIG. 2 is a diagram showing an embodiment of the arrangement of the line sensor I and the monitor sensor M on the light receiving surface 61 a of the CCD focus detection element 61. In this embodiment, a sensor set including a line sensor I and a monitor sensor M that are set in advance for each model and that can be used in actual AF processing is provided as a plurality of selection modes. A suitable selection mode is selected, and the line sensor I and the monitor sensor M included in the selected mode can be driven and controlled by the control circuit 71 of the CCD focus detection element 61. The control circuit 71 of the CCD focus detection element 61 is formed on a single circuit board 80.

  On the light receiving surface 61a, as a line sensor I, three rows of horizontal line sensors I1, I2, and I3 extending in the horizontal direction are arranged in parallel at a predetermined interval in the vertical direction, and these I1, I2, and I3 are arranged in parallel. Seven vertical line sensors I4, I5, I6, I7, I8, I9, and I10 extending in the vertical direction across the top and bottom are arranged in parallel at predetermined intervals in the horizontal direction. The line sensor of this embodiment is a so-called CCD line sensor, and a large number of light receiving elements are arranged in the longitudinal direction.

  The horizontal line sensors I1 to I3 are identified as reference blocks (reference line sensors I1a to I3a) in which the left half portion from the center of the light receiving surface 61a is a reference region, and the reference block (reference line) whose right half is a reference region Identified as sensors I1b-I3b).

  Each of the horizontal line sensors I1 to I3 includes four reference areas (I1-1a to I1-4a) to (I3-1a to I3-4a), each of the reference line sensors I1a to I3a and the reference line sensors I1b to I3b. , The reference regions (I1-1b to I1-4b) to (I3-1b to I3-4b), and the regions (I1-1a to I1-4a) to (I3-1a) of the reference line sensors I1a to I4a. ~ I3-4a) are adjacent to monitor sensors (M1-1, M1-2, M1-3, M1-4) ~ (M3-1, M3-2, M3-3, M3-4) Yes.

  Each of these monitor sensors (M1-1 to M1-4) to (M3-1 to M3-4) operates independently, and each region (I1-1a to I1-4a) of the adjacent reference line sensors I1a to I3a. ) To (I3-1a to I3-4a) are monitored.

  Each vertical line sensor I4, I5, I6, I7, I8, I9, I10 is identified as a reference block (reference line sensors I4a to I10a) located above the horizontal line sensors I1, I2, I3, and below Those located are identified as reference blocks (reference line sensors I4b-I10b).

  Each of the vertical line sensors I4 to I10 includes two reference areas (I4-1a, I4-2a) to (I10−) in which the respective reference line sensors I4a to I10a and the reference line sensors I4b to I10b divide the longitudinal direction into two. 1a, I10-2a) and reference areas (I4-1b, I4-2b) to (I10-1b, I10-2b), and reference areas (I4-1a, I4-2a) of the respective reference line sensors I4a to I10a ) To (I10-1a, I10-2a), monitor sensors (M4-1, M4-2) to (M10-1, M10-2) are arranged.

  Each of these monitor sensors (M4-1, M4-2) to (M10-1, M10-2) operates independently, and each reference region (I4-1a, I4-) of the adjacent reference line sensors I4a to I10a. 2a)-(I10-1a, I10-2a) monitor the amount of received light.

  Each of the line sensors I1 to I10 thus configured receives one of the pair of subject luminous fluxes divided into pupils for a plurality of distance measuring zones by the reference line sensors I1a to I10a and the other receives the reference line sensor I1b. Used to receive light at ~ I10b.

  Further, the CCD focus detection element 61 is arranged adjacent to and parallel to the line sensors I1 to I10 on the opposite side of the monitor sensor M, and the charges accumulated by the line sensors I1 to I10 are line sensors I1, I2, I3, I4. Shift registers 62, 63, 64, 621 to 623, 634 to 6310, and 644 to 6410 transferred in units of .about.I10. The electric charges photoelectrically converted and integrated by the photodiodes of the line sensors I1 to I10 are held in an ST (storage) unit (not shown) at the end of integration for each of the line sensors I1 to I10.

When the integration of all the line sensors I1 to I10 is completed, it is read out serially from the charge detector 65 via the shift registers 62, 63, 64. The shift register 62 is directly connected to the charge detection unit 65, and the shift register 63 is joined to the shift register 62 and connected to the charge detection unit 65.
In the vertical line sensors I4 to I10 of this embodiment, the charges of the reference line sensors I4a to I10a are transferred to the charge detector 65 by the shift register 63, and the charges of the reference line sensors I4b to I10b are transferred by the shift register 64.

  In FIG. 3, the main part of the control circuit system formed on the circuit board 80 of the CCD focus detection element 61 is shown as a block. The operation of the CCD focus detection element 61 is controlled by a control circuit 71 formed on the circuit board 80. The CCD focus detection element 61 is characterized in that the line sensor I and the monitor sensor M to be used can be selected by the control circuit system. The control circuit 71 operates in response to an instruction from the main CPU 31. In the CCD focus detection element 61 of this embodiment, the control circuit 71 selects and controls the line sensor I and the monitor sensor M specified by the command from the main CPU 31.

  Next, the configuration of the CCD focus detection element 61 will be described. Since the basic operations of the line sensors I and the monitor sensor M are the same, the specific operations of the line sensor I and the monitor sensor M are as follows. I1-1 to I1-4) and the corresponding monitor sensors M1 (M1-1 to M1-4) will be described.

  When starting the integration, the control circuit 71 immediately drives the line sensor I1 so as to sweep out the charge accumulated in each pixel (photodiode), and starts integration (charge accumulation) in units of each pixel. . At the same time, the monitor sensors M1-1 to M1-4 are cleared, and integration amount monitoring by the monitor sensors M1-1 to M1-4 is started. The output voltage of each monitor sensor M controls the integration time with an auto gain controller AGC via a buffer. Each auto gain controller AGC is controlled by a VMS signal output from the main CPU 31.

  The monitor signal output from the auto gain controller AGC is input to the control circuit 71 and the monitor output selection circuit 72. The control circuit 71 incorporates logic (for example, an operational amplifier) as detection means for detecting that each monitor signal has reached a predetermined integration end threshold (integration end value), and when the output of any logic changes. The integration OR signal (first end signal) is output to the port TINT via the selection circuit 73. Based on the signal output to the port TINT, the main CPU 31 detects that one of the line sensors I has finished integration. In this embodiment, the control circuit 71 drops the integration OR signal output to the selection circuit 73 from the high level to the low level when any of the logics falls from the high level to the low level. The integration OR signal is a high level signal at the start of integration.

  The control circuit 71 ends the integration of the line sensor I corresponding to the monitor sensor M when the output of the logic changes, that is, when the monitor signal reaches a predetermined threshold value. The integration termination process is to terminate the accumulation of charges in the ST portions of the corresponding line sensors I1 to I10.

  The monitor signals of the monitor sensor M input to the monitor output selection circuit 72 are output to the output selection circuit 70 one by one and output from the port VOUT via the output selection circuit 70.

The main CPU 31 outputs a DATA signal designating the monitor sensor M to the CCD focus detection element 61. The control circuit 71 of the CCD focus detection element 61 selects the monitor signal of the monitor sensor M designated from the main CPU 31 by the monitor output selection circuit 72 and outputs it to the main CPU 31 as the VOUT signal via the output selection circuit 70. At the same time, the control circuit 71 outputs an integration AND signal from the port SP via the selection circuit 74, and the main CPU 31 inputs this integration AND signal from the port TRIG. / D conversion.
The main CPU 31 A / D converts the input monitor signal of the monitor sensor M and uses it for integration time prediction and gain setting.

  The CCD focus detection element 61 of this embodiment alternatively outputs a monitor signal from the monitor output selection circuit 72 as a VOUT signal after the start of integration. After the monitor signals of all the monitor sensors M reach a predetermined threshold value or when a predetermined time (longest integration time) elapses, whichever comes first, that is, the integration of all the CCD line sensors I is completed or forcibly terminated. Thereafter, the image signal (Video signal) read from the CCD line sensor I is output from the port VOUT as a VOUT signal via the output selection circuit 70.

  When the control circuit 71 detects that the monitor signals of all the monitor sensors M have reached the threshold value within a predetermined time, the control circuit 71 sends an integral AND signal (second end signal) from the port SP via the selection circuit 74. It outputs to CPU31. When a predetermined time elapses before the monitor signals of all the monitor sensors M reach the threshold value, the control circuit 71 ends the integration of the line sensors I corresponding to all the monitor sensors M whose monitor signals have not reached the threshold value. Then, the integration AND signal (second end signal) is output from the port SP to the main CPU 31 via the selection circuit 73.

  When the integration of all the line sensors I is completed, the charges of the line sensors I1, I2, I3, I4 to I10 are transferred in units of the line sensors I1 to I10 and their pixels via the shift registers 62, 63, 64. The data are sequentially transferred, converted into a voltage signal by the charge detector 65, and output.

  The charge unit voltage signal is amplified by an amplifier (Gain AMP) 66, and then the OB voltage is clamped by a sample hold circuit (S / H) 67 and a clamp circuit 68, and from the buffer 69 via an output selection circuit 70. Output from the port VOUT as a VOUT signal (video signal). The main CPU 31 inputs from the port A / D. The main CPU 31 converts the input VOUT signal into a digital signal for each pixel by the built-in A / D converter 31e, and sequentially stores it in the built-in RAM 31b.

  The above monitor, integration, and readout processes can be executed for all the monitor sensors M and line sensors I, but this embodiment arbitrarily selects a set (selection mode) of the line sensors I and monitor sensors M to be executed, It is possible to combine them. That is, only the line sensor I and the monitor sensor M specified in the selection mode can be monitored, integrated, and read out. Furthermore, monitoring, integration, and readout processing can be executed for any line sensor I and monitor sensor M from among the line sensor I and monitor sensor M specified in the selection mode.

  FIG. 4 shows the relationship between the main CPU 31 and the CCD focus detection element 61 and the signals to be transmitted and received. A signal is transmitted in the direction of the arrow.

Main CPU 31 CCD focus detection element 61
Chip enable signal CE IST
Serial clock SCK RST
Data signal SO DATA

Main CPU 31 CCD focus detection element 61
Gain setting signal D / A VMS

Main CPU 31 CCD focus detection element 61
SI TINT Integration OR signal / Integration end information
(First control terminal)
Integration OR signal; high level during integration The integration OR signal falls from high to low when any monitor sensor M completes integration, and the selection circuit 73 switches to integration end information output. Thereafter, the main CPU 31 checks the integration end information of the other monitor sensors M and measures the integration time of the other monitor sensors M. That is, switching to the integration end information check is when the integration OR signal is output from the port TINTI.

Main CPU 31 CCD focus detection element 61
TRIG SP Integral AND signal / A / D sync signal
(Second control terminal)
Integral AND (total integration end) signal; high level during integration When all monitor sensors M have completed integration, they drop from high to low, and the selection circuit 74 switches to A / D synchronization signal output.

Main CPU 31 CCD focus detection element 61
A / D VOUT Line sensor image signal

  Next, operations of the main CPU 31 and the CCD focus detection element 61 will be described with reference to timing charts shown in FIGS.

  FIG. 5 is a timing chart relating to communication settings between the main CPU 31 and the control circuit 71, in which the main CPU 31 communicates with the control circuit 71. When starting communication, the main CPU 31 causes the port CE to fall and outputs a low-level chip enable signal to the port IST. The control circuit 71 shifts to a communication state when the level of the port IST falls to a low level, and maintains a communicable state during the low level.

  Next, the main CPU 31 outputs a clock pulse from the port SCK. The control circuit 71 inputs a clock pulse from the port RST, and starts communication setting processing in synchronization with the input clock pulse.

  Further, the main CPU 31 outputs 16-bit data from the port SO in synchronization with the clock pulse of the port SCK. The control circuit 71 inputs 16-bit data from the port DATA, and sets each control and parameter based on the input 16-bit data.

  Table 1 shows examples of control codes and control parameters, which are examples of the contents of 16-bit data transmitted and received by this communication setting. In this embodiment, 1 to 3 bits out of 16 bits represent a control code number, and 4 to 16 bits represent a control parameter. Control code number 0 is integration end information (AGC = 26), control code numbers 1 and 2 are AGC automatic end individual prohibition settings, control code number 4 is read line selection, transfer speed, gain setting, control code number 5 Indicates start / end of integration, AGC selection, output monitor M selection, AGC automatic end all prohibition setting, and control code number 7 specifies logic reset (default setting).

Examples of control parameters are shown in Table 2, Table 3, and Table 4.
Table 2 shows the contents of control code number 1. Control code number 1 represents AGC automatic termination prohibition setting 1. Control parameter specifies monitor sensor M to be prohibited among line sensors I1 to I4-1. is doing. The monitor sensor M prohibited by the control code number 1 and the corresponding line sensor I are not used. That is, from the line sensor I and the monitor sensor M included in the selection mode, for example, the line sensor I and the monitor sensor M that are used for focus detection in multipoint distance measurement or the like can be selected. In this embodiment, the integration termination process is performed in the total integration termination operation.

  Table 3 shows the contents of the control code number 2, and the control code number 2 represents the AGC automatic termination prohibition setting 2. The control parameter designates the monitor sensor M that prohibits automatic end of AGC among the line sensors I4-2 to I10-2. That is, the monitor sensor M and the corresponding line sensor I for which the AGC automatic termination prohibition is designated by the control parameter of the control code number 2 are not used.

  Table 4 shows the contents of control code number 5, which specifies integration start / end, AGC selection, output monitor selection or AGC automatic end all prohibition based on the contents of bits 4 to 16 of the control parameter. To do. In this embodiment, integration start is specified when bit 4 is 0, and integration end is specified when bit 4 is 0. Bits 5 to 7 specify any one of MODE (Mode) 1 to MODE (Mode) 5 as selection modes, and bits 8 to 12 indicate any of the VREF output and the line sensors I1-1 to I10-2. Any one of the AGC black outputs is selected, and bit 13 is set to 0 to specify that AGC automatic termination is completely prohibited.

Next, the integration operation of the image sensor 61 will be described with reference to a timing chart relating to the entire sequence shown in FIG.
(A) The communication setting selection pulse output from the port IST falls to a low level and rises to a high level after a predetermined time. While the communication setting selection pulse falls to the low level, communication data is input from the port DATA in synchronization with the communication CK pulse input from the port RST. Here, communication data (control code number 7) for resetting the logic of the CCD focus detection element 61 is input. The control circuit 71 that has received this communication data resets the logic and sweeps out the charges accumulated in each line sensor I at high speed.

  (B) Next, while the communication setting selection pulse of the port IST falls to the low level, the control circuit 71 inputs communication data (control code number 7) for setting the logic to the standard setting from the port DATA. The control circuit 71 having received this communication data (control code number 7) returns the logic to the standard setting.

  (C) The process corresponding to the control parameter of control code number 1 or 2 is set before the start of integration as necessary. That is, for example, an auto gain controller AGC (monitor sensor M) that prohibits automatic end of AGC specified by a control parameter is set.

  (D) While the communication setting selection pulse of the port IST falls to the low level, communication data (control code number 5) relating to the start of integration is received. The control circuit 71 that has received this communication data (control code 5) resets the monitor sensor M corresponding to the designated MODE1 to MODE5, raises the port SP to high level, and causes the line sensor I to start integration. The start of integration is transmitted to the main CPU 31. In this embodiment, all line sensors I are integrated.

(E) When the port IST rises to a high level, the level of the port TINT is raised to a high level. When the integration is started, the monitor signal (output voltage) of the monitor sensor M that is alternatively output from the port VOUT rises with time.
When any of the monitor sensors M for which AGC automatic termination prohibition is not set reaches a predetermined threshold value, a low-level integration OR signal (first termination signal) is output from the port TINT via the selection circuit 73 from the control circuit 71. Output to the port SI of the main CPU 31.

  (F) When the main CPU 31 receives the integration OR signal (first end signal) from the port SI, the main CPU 31 outputs a chip enable signal from the port CE to the port IST of the CCD focus detection element 61. The control circuit 71 of the CCD focus detection element 61 latches the integration information of the monitor signal of the monitor sensor M by the input chip enable signal and outputs it from the output selection circuit 73 as the SOUT signal. Regarding the signal for identifying the integration end state of the monitor sensor M, the monitor sensor M being integrated is at a high level, and the monitor sensor M after the integration is at a low level.

  (G) When the output voltages of all the monitor sensors M that are not prohibited from AGC automatic termination reach a predetermined threshold value, an integration AND signal is output from the selection circuit 74.

  (H) A line sensor for which AGC automatic termination prohibition is not set, that is, any one of line sensors I1, I2, I3, and I4 to I10 to be used is selected.

  (I) In synchronization with the rise of the port IST, reading of any of the selected line sensors I1, I2, I3, I4 to I10 is started, and an image signal is output from the output selection circuit 70 as a VOUT signal. Then, an A / D synchronization signal is output from the port SP via the selection circuit 74. The main CPU 31 A / D converts the input VOUT signal in synchronization with the A / D synchronization signal.

  Thereafter, the operations (h) and (i) are executed in an arbitrary order for all the line sensors to be used among the line sensors I1, I2, I3, and I4 to I10, and when all the readings are completed, the CCD control is finished. To do.

  FIG. 7 shows a timing chart of the process in which the main CPU 31 inputs the integration end information of each monitor sensor M in (f) above. When the output of any one of the monitor sensors M reaches a predetermined threshold value, the control circuit 71 outputs an integration OR signal (low level) from the port TINT via the selection circuit 73. When the main CPU 31 receives the integration OR signal from the port SI, the main CPU 31 lowers the port CE to low level and the port IST of the control circuit 71 to low level. As a result, the control circuit 71 sequentially outputs integration end information of each monitor sensor M from the port TINT via the selection circuit 73 every time a pulse is input to the port RST. In the illustrated embodiment, the integration end information is output in the order of the monitor sensors M corresponding to the line sensors I1-1 to I1-4, I2-1 to I2-4, to I10-1, and I10-2.

Since the main CPU 31 can first detect that the output of the monitor sensor M has reached the threshold value by communication from the control circuit 71, the main CPU 31 is not restricted until the communication is received, and the subject brightness is very high. Even when the output of M reaches the threshold value in a very short time, the output of each monitor sensor M is detected in parallel by the logic of the control circuit 71 of the CCD image sensor 61, so the outputs of all the monitor sensors M are accurately detected. In addition, accurate integration end information can be obtained for each corresponding line sensor I.
In addition, in this embodiment, since the integration end information can be input by communication between the same ports TINT and SI, the ports can be used effectively.

Next, examples of usage patterns of the line sensor I and the monitor sensor M of the CCD focus detection element 61 will be described. In this embodiment, five types of selection modes are provided. An example of the correspondence between the line sensor I and the monitor sensor M used in each of the MODEs 1 to 5 is shown in Table 5. In Table 5, “ALL” means all four monitor sensors (M1-1 to M1-4) to (M3-1 to M3-4) and vertical line sensors I4 to I4 in the horizontal line sensors I1 to I3, respectively. In the case of I10, it is meaningful to make the monitor which has been initially integrated out of all two monitor sensors (M4-1, M4-2) to (M10-1, M10-2) effective. In this case, the line sensors are collectively designated as “Mx” in the block I (I1 to I3).
You may enable it to designate every line sensor I1-10.

  10 to 12 show usage patterns of the line sensor I and the monitor sensor M of the CCD focus detection element 61 used in MODEs 1 to 3. FIG. In these figures, the area surrounded by the thick broken line is the used block. In Table 5, for example, a sensor monitor not used in block 4 of MODE 1 is designated by “M3”. Depending on the AF optical system, a part of the sensor M1-4a may be used instead of the sensor boundary region as shown by the broken line in FIG. 10, and therefore, it is assumed that the sensor M1-3a is expanded. This is because the monitor sensor shares the monitor M3 corresponding to the sensor M1-3a.

FIG. 10 shows a MODE1 pattern corresponding to MODE1. In the MODE1 pattern, the three horizontal line sensors I1 to I3 have a reference block of the first to third blocks and a reference block of the second to fourth blocks, that is, the horizontal line sensor reference areas (I1-1a to I1). -3a) to (I3-1a to I3-3a), horizontal line sensor reference areas (I1-2b to I1-4b) to (I3-2b to I3-4b), and three corresponding to each area Monitor sensors (M1-1 to M1-3) to (M3-1 to M3-3) are used. The seven vertical line sensors I4 to I10 each have a total area (first and second), that is, vertical line sensor reference areas (I4-1a, I4-2a) to (I10-1a, I10-2a), vertical lines. The sensor reference areas (I4-1b, I4-2b) to (I10-1b, I10-2b) are used, and the monitor sensors are all monitor sensors (M4-1, M4-2) to ( Use M10-1 and M10-2).
This MODE1 pattern is suitable for an optical system that requires highly accurate focus detection or a relatively large optical system.

A MODE2 pattern corresponding to MODE2 is shown in FIG. In this MODE2 pattern, the three horizontal line sensors I1 to I3 are respectively the second and third blocks, that is, the horizontal line sensor reference areas (I1-2a, I1-3a) to (I3-2a, I3-3a). The horizontal line sensor reference areas (I1-2b, I1-3b) to (I3-2b, I3-3b) are used, and the monitor sensor M includes two monitor sensors corresponding to the second and third areas, respectively ( M1-2, M1-3) to (M3-2, M3-3) are used. The seven vertical line sensors I4 to I10 are the second areas closer to the center of the five vertical line sensors I5 to I9 except for both ends, that is, the vertical line sensor reference areas (I5-2a) to (I9-2a). ), Vertical line sensor reference areas (I5-1b) to (I9-1b) are used, and second monitor sensors M5-2 to M9-2 are used, respectively.
This MODE2 pattern is suitable for medium to small optical systems.

FIG. 12 shows a MODE3 pattern corresponding to MODE3. In this MODE3 pattern, for the three horizontal line sensors I1 to I3, the reference block is the second to fourth block, the reference block is the first to third block, that is, the horizontal line sensor reference region (I1-2a, I1-4a) to (I3-2a, I3-4a), horizontal line sensor reference areas (I1-1b, I1-3b) to (I3-1b, I3-3b) are used, and 3 corresponding to each area. The monitor sensors (M1-2 to M1-4) to (M3-2 to M3-4) are used. None of the seven vertical line sensors I4 to I10 and the monitor sensors M4 to M10 are used.
This MODE3 pattern is suitable for a small optical system.

  The above usage patterns are examples, and usage patterns can be set according to various optical systems such as usage patterns corresponding to MODEs 4 and 5.

FIG. 8 shows an example of a focus detection area on the viewfinder field corresponding to this MODE1 pattern, and FIG. 9 shows an example of an AF optical system.
The subject light beam reflected by the quick return 15 toward the AF module 60 is converged by the condenser lens 81 and deflected by the mirror 82 in the direction substantially parallel to the optical axis of the photographing lens, and the infrared cut filter 83 and the auxiliary lens 84. Pass through. The subject luminous flux separated through the opening of the separator mask 85 having a pair of openings formed corresponding to each focus detection area is subject to the subject on the line sensor I of the CCD focus detection element 61 by each lens of the separator lens 86. Project an image.

  Next, the integration process executed by the main CPU 31 with the control circuit 71 of the CCD focus detection element 61 will be described with reference to the flowchart shown in FIG. 13 and the timing charts shown in FIGS. This integration process is controlled by the main CPU 31 by lowering the port IST to a low level and outputting a chip enable signal CE for communication. In the following description, the step is abbreviated as “S”.

  In the integration process, first, the main CPU 31 performs AGC prohibition communication of the monitor sensor M corresponding to the AGC automatic termination prohibition settings 1 and 2 of the control code numbers 1 and 2 (S101), and performs AGC mode selection communication (S101). S102). In this embodiment, it is set to be selectable from five types of AGC modes of MODE1 to MODE5. Among these, the pattern of the line sensor I corresponding to MODE1 to MODE3 is as shown in FIGS.

  Next, integration start communication is executed. At that time, the port SP and the port TINT rise to a high level (S103). By this processing, the monitor sensor M and the line sensor I integration are started.

  Next, it is checked whether an integral OR signal has been output (whether the port TINT has dropped to a low level), that is, whether the output signal of any monitor sensor M has reached a predetermined threshold (S104). When the integration OR signal is not output (S104; N), the shortest integration time is updated and the process proceeds to S109 (S108, S109).

When the integration OR signal is output (S104; Y), the integration end information communication is executed (S105), and it is checked whether there is a used block (line sensor I) during integration (S106). The “used block” means a block including the line sensor I that is not prohibited from AGC automatic termination.
If there is a block being integrated (S106; Y), the integration time of the block being integrated is updated and the process proceeds to S109 (S107, S109). If there is no block being integrated (S106; N), it remains as it is. The process proceeds to S109 (S109).
The processes of S104 to S108 are processes for measuring the integration time. The measured integration time is logarithmically compressed, and the logarithmically compressed integration time is used for AGC level correction.

  In S109, the monitor signal is A / D converted. Then, AGC level correction is performed according to the integration time (S110). AGC level correction is a process for keeping the output voltage at the end of integration constant regardless of the length of integration time.

  It is checked whether the integration for all the line sensors I has been completed, that is, whether the port SP has fallen to a low level and an integration AND signal has been output (S111). If all the integrations have not been completed (S111; N), it is checked based on the end information whether the integration of the used block (line sensor corresponding to the MODE number) has been completed (S112). If the integration of the used block is not completed (S112; N), the process returns to S104 and the processes of S104 to S111 and S112 are repeated.

When integration of all line sensors is completed (S111; Y) or when integration of all used blocks is completed (S111; N, S112; Y), integration completion communication is executed (S113), and the VOUT signal (Video data) , A / D conversion is performed in synchronization with the port SP signal, and this process is terminated (S114, RET).
This integration process is repeatedly executed every predetermined time.

  The relationship between the VOUT signal and the VMS signal is shown graphically in FIG. In this graph, the horizontal axis indicates the apex display equivalent value Ev of the brightness of the subject, and the vertical axis indicates the VOUT signal.

  The VMS signal is implemented so that the integral value of the line sensor I becomes a predetermined integral value when the monitor signal output from the monitor sensor M at the reference subject luminance reaches a predetermined integration end value (threshold value). In the embodiment, the amplified VOUT signal is adjusted to a predetermined value. However, the line sensor I and the monitor sensor M have a characteristic that the VOUT signal becomes smaller than a predetermined value as the integration time becomes longer (the subject becomes darker) (FIG. 15A). In this state, in the case of high luminance, the integrated value of the high luminance portion is saturated, and accurate phase difference measurement cannot be performed. Since the integral value becomes smaller than the proper integral value at low luminance, the dynamic range of the CCD cannot be used effectively and the contrast cannot be obtained.

  Therefore, in the present embodiment, the VMS signal serving as the AGC reference level is corrected (adjusted) so that the appropriate VOUT signal becomes a predetermined value regardless of the brightness of the subject, that is, the length of the integration time (FIG. 15B). ). S110 is the correction process, and the AGC level correction process by the integration time correction will be described with reference to the flowchart shown in FIG. 14 and FIG.

  In this AGC level correction process, the brightness corresponding to Ev = 12, which is an apex display value (logarithmic value), is set as the reference brightness, and the integration end time 1 mS (1024 μS) at this brightness is used as a reference to logarithm the actual integration time. The VMS signal is corrected so that the appropriate VOUT signal becomes constant according to the time of compression and logarithmic compression.

When the AGC level correction process is started, first, an AGC reference value is set (S201). This reference value is the reference value voltage VMS.
Next, the Ev value corresponding to the apex display value is set to the maximum value, which is 16 in this embodiment (S202). Then, it is checked whether the integration time is 128 μS or more (S203). If it is above (S203; Y), the integration time is halved (S204), 1 is subtracted from the Ev value, and the process returns to S203 (S205, S203). The above loop processing is repeated until the integration time becomes less than 128 μS. By this loop processing, an Ev value corresponding to the integration time is obtained. In this embodiment, since the initial value (maximum value) of the Ev value is set to 16, the Ev value remains 16 when the integration time is less than 128 μS and the luminance is higher than Ev16.

When the integration time is less than 128 μS or less than 128 μS due to the processing of S204 (S203; N), Ev ′ is expressed by the equation (Ev-12) − (the remainder of (integration time / 64 μS)) / 64
(S206).
From this equation, the difference between the current Ev value set in the processing of S202 to S205 and the reference Ev value (12) can be obtained. In the above equation, “((remainder of integration time / 64 μS)) / 64” is a calculation of a portion less than 1 Ev remaining in the loop processing of S203 to S205. Here, up to 1/8 Ev is calculated.

Then, the reference voltage VMS is corrected by the formula VMS−Ev ′ × correction value (S207), the corrected reference voltage VMS is D / A converted, applied to the corresponding auto gain controller AGC, and the process returns (S208). RET).

By this AGC level correction processing, the reference voltage VMS is adjusted so that the output of the appropriate integral value is constant regardless of the brightness of the subject, so that the maximum output voltage of each line sensor is not cut and each line is cut. The dynamic range of the sensor can be used effectively.
Normally, each value of the AGC level correction process, for example, the reference value voltage VMS in S201, the Ev value in S202, 128 μS in S203, and the coefficient in S206 are set in advance according to the characteristics of the line sensor I, etc. It is written in the EEPROM 38.

  As described above, the CCD focus detection element 61 according to an embodiment of the present invention includes a plurality of sensor sets each including a line sensor and a monitor sensor, and the control circuit including the main CPU 31 and the CCD focus detection element 61 as the sensor set to be used. Since it can be specified by communication between 71, the set of line sensors and monitor sensors to be used can be selected according to the specifications of the mounted camera, the photographing optical system, and the focus detection area. That is, the same CCD focus detection element 61 can be adapted to the specifications of various devices to be mounted.

  Further, the CCD focus detection element 61 can be used in a larger number of finer patterns because each line sensor can be identified as a plurality of areas and a monitor sensor is provided for each area so that the monitor sensor can be controlled for each area. It became possible to do.

It is a figure which shows the outline | summary of the single-lens reflex camera which mounts the CCD focus detection element of this invention with a block. It is a figure which shows embodiment of arrangement | positioning of the line sensor of the CCD focus detection element of this invention. It is a figure which shows the outline of the control circuit on the CCD focus detection element in a block. It is a figure which shows the communication line between the CCD focus detection element and CPU of a camera. It is a figure which shows the timing chart regarding the communication setting content of the CCD focus detection element. It is a figure which shows the timing chart regarding the whole operation | movement of the CCD focus detection element. It is a figure which shows the timing chart regarding the completion | finish operation | movement of the CCD focus detection element. It is a figure which shows one Example of the focus detection area in the finder image of the focus detection apparatus of the single-lens reflex camera using the CCD focus detection element. It is a figure which shows one Example of the AF optical system of the focus detection apparatus of the single-lens reflex camera using the CCD focus detection element. It is a figure which shows the 1st usage example of the line sensor and monitor sensor of the CCD focus detection element. It is a figure which shows the 2nd usage example of the line sensor and monitor sensor of the CCD focus detection element. It is a figure which shows the 3rd usage example of the line sensor and monitor sensor of the CCD focus detection element. It is a figure which shows the integration process of the same CCD focus detection element with a flowchart. It is a figure which shows the AGC level correction process of the CCD focus detection element with a flowchart. FIG. 6 is a graph showing the relationship between the brightness of an object and the output voltage of the CCD focus detection element, where (A) is a diagram before AGC level correction processing, and (B) is a diagram after AGC level correction processing.

Explanation of symbols

11 Camera body 13 Main mirror 14 Half mirror section 15 Sub mirror 31 Main CPU
31a ROM
31b RAM
31c Reference timer 31d Counter 32 AF motor driver 33 AF motor 34 Gear block 35 Joint 37 Encoder 38 EEPROM
51 Shooting Lens 52 Focus Adjustment Lens 53 Gear Block 55 Joint 57 Lens CPU
60 AF module 61 CCD focus detection element 62 63 64 shift register 621 to 623 shift register 634 to 6310 644 to 6410 shift register 65 charge detection unit 70 output selection circuit (output selection means)
71 Control circuit (control means, detection means)
72 Monitor output selection circuit (monitor selection means)
73 selection circuit 74 selection circuit 80 circuit board I line sensor I1 I2 I3 horizontal line sensor I4 I5 I6 I7 I8 I9 I10 vertical line sensor M monitor sensor M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 monitor sensor

Claims (7)

A plurality of line sensors each having a plurality of pixels, photoelectrically converting and integrating subject light received by each pixel, and outputting as image signals;
A monitor sensor that is provided adjacent to each line sensor and monitors an integral value of the adjacent line sensor;
Control means for amplifying the output of each monitor sensor and outputting it as a monitor signal, and terminating the integration of the line sensor corresponding to the monitor sensor when the monitor signal reaches a predetermined end value;
During the integration of the line sensor, comprising a gain adjustment means for adjusting the gain level of each control means according to each integration time,
The gain adjusting means adjusts the gain level of the control means so that an appropriate integrated value of the line sensor when the monitor signal reaches a predetermined end value becomes substantially a predetermined value regardless of an integration time. Feature focus detection device. The focus detection apparatus according to claim 1, wherein the gain adjustment unit includes a calculation unit that calculates a correction value based on an integration time obtained by logarithmically compressing the integration time and a predetermined coefficient. A detection means for detecting that the amplified monitor signal has reached a predetermined end value for terminating the integration of the line sensor after the control means has started the integration of the line sensor and the monitor sensor;
The control means outputs a first end signal from a first control terminal to the gain adjusting means when the detection means detects that the monitor signal of any monitor sensor has reached the end value, Thereafter, the integration end information of each monitor sensor is sequentially output from the first control terminal to the gain adjustment unit, and the gain adjustment unit measures the integration time based on the integration end information, and the correction value. The focus detection apparatus according to claim 1, wherein the focus detection apparatus calculates the following. The focus detection apparatus according to claim 3, wherein the gain adjusting unit measures an integration time based on integration end information output from the first control terminal. The focus detection apparatus according to claim 1, wherein the focus detection apparatus includes the line sensors, a monitor sensor, and a control unit, and the gain adjustment unit is provided separately. The focus detection apparatus according to claim 5, wherein the gain adjustment means is a control means of an apparatus on which the focus detection apparatus is mounted. The focus detection apparatus according to claim 5, wherein the focus detection apparatus is mounted on a camera, and a control unit of the camera functions as the gain adjustment unit.

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