JP2004265597A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To adjust drive timing of a sense amplifier to operation timing of a word line while reducing a load of a word line potential generating circuit and securing a write-in potential for a memory cell. <P>SOLUTION: This semiconductor memory device is provided with a memory cell array, word lines 7, bit lines 8, a sense amplifier 5, a sense amplifier starting circuit 2, a sense amplifier control circuit 3, sense amplifier drive circuits 4A, 4B, 4C, drive power source supply wiring 12A, 12B, 12C, and a voltage switching timing generating circuit 18 for controlling timing for switching output signals of power source voltage switching circuits 1A, 1B, 1C to an external power source potential VDD and an internal drop voltage potential VINT. The voltage switching timing generating circuit 18 has the same circuit constitution as the sense amplifier starting circuit 2. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a data amplifier circuit capable of high-speed data amplification and a semiconductor memory device using the same.

  In recent years, as the speed of the CPU, the performance of applications, and the speed of the entire system have been increasing, there has been a demand for faster data transfer in the main memory and faster random access. On the other hand, in portable information terminal devices, low power consumption of a main storage memory is strongly demanded in order to enable long-time battery drive. Until now, in the DRAM, a method of operating the internal elements using the internal step-down power supply VINT has been adopted in order to secure the reliability of the internal elements and reduce the power consumption. However, the amplification speed of data amplification, particularly the amplification speed of the sense amplifier, has been reduced, which has hindered the speeding up of random access.

  Conventionally, the following method has been used.

  The first method is a method disclosed in Patent Literature 1, in which an external power supply potential VDD is temporarily used as a power supply voltage of the sense amplifier at the start of the amplification operation of the sense amplifier instead of the internal step-down potential VINT. It is a method.

  This is a method proposed to solve the following problems. That is, when amplifying read data from a memory cell by the sense amplifier, a large amount of current is consumed in the sense amplifier. Originally, the internal step-down power supply potential VINT is used as the power supply potential of the sense amplifier in order to reduce power consumption. However, the current supply capability of the internal step-down power supply potential VINT is limited. Therefore, at the time of data amplification by the above-described sense amplifier, a voltage drop occurs due to insufficient charge supply, and the data amplification speed of the sense amplifier is reduced.

  On the other hand, in the method disclosed in Patent Document 1, as shown in FIG. 16, a power supply voltage switching circuit for switching the power supply potential of each sense amplifier drive circuit between an internal high-voltage power supply potential VINT and an external power supply potential VDD. Is provided for each sense amplifier block, and instead of the internal step-down power supply potential VINT, an external power supply potential VDD having sufficient charge supply capability is switched and supplied during data amplification. The switching of the power supply potential prevents a delay in the data amplification speed of the sense amplifier due to a shortage of charge supply, thereby realizing high speed operation.

  The second method is a method disclosed in Patent Literature 2 or Patent Literature 3, in which read data from a cell is once taken into a sense amplifier, and then the data between the sense amplifier and the bit line is amplified when the data is amplified. This is a method of completely closing a switching transistor (shared switch: SS).

  This method has been proposed to solve the following problems. Usually, when the sense amplifier is not selected, the gate potential of the shared switch is the external power supply potential VDD. The gate potential of the shared switch on the memory cell side selected at the time of selection of the sense amplifier transits to the word line boosted potential VPP which is a rewriting potential, and the gate potential of the non-selected shared switch transits to the ground potential VSS. The switch is closed. However, since the shared switch is completely open when data is amplified by the sense amplifier, the capacity and resistance of the bit line on the memory cell side act as a load on the sense amplifier via this shared switch, and the The amplification operation was delayed.

  On the other hand, in the methods disclosed in Patent Documents 2 and 3 described above, as shown in FIG. 17A, when a word line is activated, a shared switch opens to read data from a memory cell. The charge is taken into the sense amplifier, and thereafter, the gate potential of the shared switch is lowered from the external power supply potential VDD to the ground potential VSS, and the shared switch is completely closed. As a result, when data is subsequently amplified by the sense amplifier, the capacitance and resistance of the bit line on the memory cell side do not become a load on the sense amplifier via the shared switch, and the data amplification operation of the sense amplifier is speeded up. Can be realized. After the data is amplified, the gate potential of the shared switch is raised from the ground potential VSS to the power supply potential VPP of the word line at a stretch, and rewriting is performed.

  The third method is a method disclosed in Non-Patent Document 1 in which the gate potential of a shared switch at the time of data amplification by a sense amplifier is required for a minute read charge from a memory cell to be taken into the sense amplifier. In addition, it is a method that keeps it at the lowest level.

  In this method, as shown in FIG. 17B, when the sense amplifier is not selected, the gate potential of the shared switch is set to the ground potential VSS, and the shared switch is closed to close the bit line and the memory on the sense amplifier side. The cell-side bit lines are completely separated. At this time, the bit line precharge potential on the sense amplifier side is set to be higher than the bit line precharge potential on the memory cell side. When the sense amplifier is selected, the gate potential of the shared switch is raised to the lowest level (β + Vtn) (Vtn is the threshold voltage of the NMOS transistor) necessary for the charge read from the memory cell to be taken into the sense amplifier. Performs the data amplification operation in the sense amplifier. Also at the time of rewriting to the memory cell, the gate potential of the shared switch does not change, and maintains the minimum level necessary for the charge read from the memory cell to be taken into the sense amplifier.

  Therefore, when the sense amplifier is selected, the precharge potential is higher and the capacity is smaller on the bit line on the sense amplifier side than on the bit line on the memory cell side. In this case, the potential difference between the bit lines of the bit line pair (BIT, / BIT) becomes larger than that in the previous read operation (the potential on the Low side decreases and the potential difference on the Hi side increases). This reduces the load on the sense amplifier due to the capacitance and resistance of the bit line on the memory cell side from the shared switch during data amplification by the sense amplifier, and reduces the potential difference between the paired bit lines at the start of the amplification operation. By increasing the size, the speed of data amplification of the sense amplifier was to be increased.

  The fourth method is a method using an inverter chain connected to a capacitor as a timing setting delay element for starting a sense amplifier.

This is because, as shown in FIG. 18, the start / stop timing of the sense amplifier is matched with the RC delay characteristics of the rise and fall times of the word line from the start of the word line. This is a method of setting the delay time of the stop timing by using an inverter chain connected to a capacitor as the delay circuit. As a result, the circuit configuration can eliminate the extra delay time of the start / stop timing of the sense amplifier with respect to the start / stop timing of the word line required in response to the temperature change, and the start timing of the sense amplifier is advanced. Was trying to achieve higher speed.
JP-A-9-204777 (FIG. 2, paragraph [0014]) JP-A-9-330593 (FIG. 2, paragraph [0021]) JP-A-10-125067 (abstract) ISSCC-1997 DIGEST OF TECHNICAL PAPER P.66-67

  However, these conventional methods also have the following disadvantages.

  In the first method, although the amount of electric charge supplied during data amplification by the sense amplifier increases, the amount of electric charge supplied from the voltage switching circuit becomes insufficient with respect to the electric charge consumed by the sense amplifier operating simultaneously when the sense amplifier block is selected. The situation was inviting. For this reason, the amplification capability of the sense amplifier cannot be sufficiently increased, and the effect of increasing the data amplification speed cannot be sufficiently obtained.

  In the second method, it is difficult to adjust the timing of stepping down the gate potential of the shared switch to the ground potential VSS after the charge read from the memory cell is taken into the sense amplifier. In this timing setting, it is necessary to add a timing margin in consideration of power supply voltage dependency, temperature dependency, and process variation. For example, power supply voltage dependency has the following disadvantages. When the power supply voltage is high, the timing required for reading by the sense amplifier is short, but when the power supply voltage is low, the timing is long. Therefore, if the timing is set in accordance with the read characteristics at the time of low voltage, the shared switch is closed before data is taken in at the time of read at high voltage. On the other hand, if the timing is set in accordance with the read characteristics at the time of high voltage, the shared switch does not readily close even when data is taken in at the time of read at the time of low voltage, which causes a delay in the activation of the sense amplifier. That is, although it may be possible to increase the speed of the amplification operation itself of the sense amplifier, it is difficult to increase the operation speed of the sense amplifier, including starting and rewriting, while performing accurate timing adjustment.

  Further, at the time of rewriting, the gate potential of the shared switch is boosted from the ground potential VSS to the power supply potential of the word line at a stretch, so that the load on the word line boosted potential generation circuit, which is the potential generation circuit, is increased, and this word line boosted potential is increased. Increasing the power consumption of the generating circuit itself by increasing the charge supply capability of the generating circuit and increasing the chip area by increasing the capacitance for reducing the fluctuation of the word line boosted potential are caused.

  In the third method, the read potential difference from the memory cell between the paired bit lines (BIT, / BIT) can be increased during data amplification, but rewriting to the cell is not possible only with the shared switch potential control method. For this to be sufficient, the configuration of the sense amplifier needs to be complicated. Specifically, it is necessary to provide a P-type MOS transistor on the bit line side of the shared switch to sufficiently raise the level of Hi-side data. However, if this configuration is adopted, the number of P-type MOS transistors is increased by two compared with a normal sense amplifier, and the area of the sense amplifier itself is increased and the structure becomes complicated when well separation is taken into consideration. Further, when inverting the memory cell data, it is necessary to invert the data according to the data that captures the potential difference between the bit lines via the P-type MOS transistor while sandwiching the shared switch therebetween. Causes a delay in speed.

  In the fourth method, the start / stop timing of the sense amplifier is set by setting the delay characteristics of the sense amplifier start signal generation circuit with respect to changes in external power supply voltage and process variations and the time from the start of the word line to the rise of the word line. In addition, it is necessary to consider the difference in the delay characteristics of the time from the stop to the fall of the word line, so it is necessary to provide a margin for the start and stop timing of the sense amplifier with respect to the start and stop timing of the word line. This causes delay in the start timing of the sense amplifier.

  A main object of the present invention is to improve read operation speed without violating demands for lower voltage, lower power consumption, and smaller size.

 More specifically, supply of sufficient charge when amplifying data in a memory cell by a sense amplifier, reducing the load on the sense amplifier at the time of data amplification while simplifying potential switching control of the gate potential of the shared switch, and It is possible to reduce the burden on the word line potential generation circuit at the time of writing, or to match the timing of starting and stopping the operation of the word line with the timing of starting and stopping the word line while ensuring sufficient write potential to the memory cells. It is an object of the present invention to provide a semiconductor memory device that performs the following.

  A semiconductor memory device according to the present invention includes a memory cell for storing information, a word line and a bit line connected to the memory cell, a sense amplifier for amplifying information stored in the memory cell, and a word line. A word line selection signal generation circuit for generating a line selection signal, a word signal drive signal generation circuit for generating a word line drive signal, and inputting the word line selection signal and the word line drive signal, A word line drive circuit for driving a line; and a sense amplifier start signal generating circuit for outputting a start signal for the sense amplifier. The sense amplifier start signal generating circuit includes the word line selection signal generating circuit and the word line. It is constituted by a circuit having the same structure as at least one of the drive signal generation circuit and the word line drive circuit.

  Thus, the output timing of the sense amplifier start signal for setting the start and stop timing of the sense amplifier, including the influence of the external power supply voltage dependency, the temperature dependency, and the process variation, can be changed to the word line start / stop timing. It becomes possible to match.

  The word line selection signal generation circuit, the word line drive signal generation circuit, and the sense amplifier activation signal generation circuit are configured to be activated by a normal word line selection signal or a redundancy selection signal which is an output signal of a redundancy judgment circuit. Thus, the start timing of starting and stopping the sense amplifier and the timing of starting and stopping the word line are matched.

  First voltage generating means for generating a voltage with little external power supply potential within the range of the external power supply potential in accordance with the external power supply potential and applying the voltage to the word line; Second voltage generating means for generating a voltage having little dependence on the external power supply potential and supplying the voltage to at least some of the sense amplifier start signal generating circuits may be further provided.

  As a result, the operation of extracting data from the memory cell and the operation of amplifying the sense amplifier can be controlled by using a voltage with little power supply dependency, so that the timing of both can be easily adjusted, and the amplification of memory cell data can be performed at high speed. Can be done at

  A voltage having little dependency on the external power supply potential within the range of the external power supply potential is input to the word line, and at least some of the sense amplifier start signal generation circuits receive an external voltage within the range of the external power supply potential. It is preferable that a voltage with little power supply potential dependency be input.

  The sense amplifier activation signal generation circuit includes a portion having the same structure as at least one of the word line selection signal generation circuit, the word line drive signal generation circuit, and the word line drive circuit, and a sense amplifier activation signal. The delay circuit can be constituted by a conductor having the same layout structure as the word line.

  As a result, when adjusting the timing of each operation, the power supply voltage dependence such as the delay characteristics of the members constituting the circuit and the effects of process variations can be almost ignored.

  By configuring the delay circuit by arranging dummy memory cells having the same layout structure as the memory cell transistors and not used for storing information, the operation speed can be increased by utilizing the dummy memory cells. .

  By arranging the dummy memory cell at an end of the memory cell region, a step existing between the memory cell region and the sense amplifier can be reduced.

  The sense amplifier activation signal generation circuit includes a portion having the same structure as at least one of the word line selection signal generation circuit, the word line drive signal generation circuit, and the word line drive circuit, and a sense amplifier activation signal. And a third wiring extending opposite to the first and second wirings connected to the ground potential with an insulating film interposed therebetween. The wiring can be formed as gates of a plurality of NMOS transistors.

  This makes it possible to form a delay circuit with the third wiring having the same delay characteristic as a word line functioning as a gate of a plurality of NMOS transistors forming a memory cell transistor. And the timing can be adjusted independently of process variations, and the characteristics of the third wiring can be matched with the characteristics of the word line.

  In that case, it is preferable that the width and the length of the portion of the third wiring functioning as the gate of the NMOS transistor be the same as the width and the length of the portion of the word line functioning as the gate of the memory cell.

  The sense amplifier activation signal generation circuit includes a portion having the same structure as at least one of the word line selection signal generation circuit, the word line drive signal generation circuit, and the word line drive circuit, and a sense amplifier activation signal. An output delay circuit, wherein the delay circuit has a plurality of delay elements in which a plurality of MOS transistors are connected in series with at least one resistance element interposed between their drains. The delay elements can be sequentially connected so that the gate of the MOS transistor is used as an input unit and the connection between the MOS transistors is used as an output unit.

  This makes it possible to obtain a delay circuit having a delay characteristic with less power supply voltage dependency by using a resistance element having a larger resistance value than the MOS transistor while using a MOS transistor having relatively high power supply voltage dependency.

  In such a case, the number of the resistor elements can be reduced by providing the resistor element only in a portion where a signal of a level for instructing start or stop of the sense amplifier among Hi level and Low level flows. Thus, a simplified semiconductor memory device is obtained.

  Further, the plurality of MOS transistors in each of the delay elements are a first conductivity type MOS transistor and a second conductivity type MOS transistor, and among the plurality of delay elements, the resistive element is the output section of the delay element and the first MOS transistor. A delay element interposed between the MOS transistor and the conductivity type MOS transistor is a first inversion element, and the resistance element is interposed between the output unit of the delay element and the MOS transistor of the second conductivity type. The same effect can be obtained by alternately connecting the first inverting element and the second inverting element to the delay circuit when the sensing element is the second inverting element. can get.

  According to the present invention, the sense amplifier activation signal generation circuit is configured by a circuit having the same structure as at least one of the word line selection signal generation circuit, the word line drive signal generation circuit, and the word line drive circuit. In addition, the output timing of the sense amplifier start signal including the external power supply voltage dependency, the temperature dependency, and the process variation can be easily adjusted to the start and stop timing of the word line.

  Hereinafter, embodiments of the present invention will be described, but the semiconductor memory device in each of the following embodiments specifically functions as a so-called DRAM.

(1st Embodiment)
First, a semiconductor memory device according to a first embodiment of the present invention will be described with reference to the drawings.

−Configuration−
FIG. 1 is a circuit diagram showing a schematic configuration of the semiconductor memory device according to the present embodiment.

  As shown in FIG. 1, the semiconductor memory device according to the first embodiment of the present invention includes a memory cell array in which a large number of memory cells 9 are arranged in a matrix (in FIG. (Only the cell block 19 is shown), a sense amplifier block 10 in which the sense amplifier 5 and the like are disposed, and power supply voltage switching circuits 1A, 1B, and 1C. The sense amplifier block 10 includes a sense amplifier starting circuit 2, a sense amplifier control circuit 3X, sense amplifier driving circuits 4A, 4B, 4C, and sense amplifier arrays 6A, 6B in which a large number of sense amplifiers 5 are arranged. ing. In the present embodiment, the power supply voltage switching circuits 1A, 1B, 1C function as power supply voltage control circuits.

  A number of word lines 7 extending in the row direction and connected to the gate electrode of each memory cell 9 and a number of bit lines 8 extending in the column direction and connected to the drain of each memory cell 9 are provided. I have. The memory cell 9 includes a memory cell transistor and a memory cell capacitor connected to a source of the memory cell transistor. The sense amplifier 5 is connected to the bit line 8 and detects whether data is "0" or "1" according to the charge held by the memory cell capacitor. The sense amplifier drive circuits 4A, 4b, 4C and the sense amplifier control circuit 3X control the operation of each sense amplifier 5. The sense amplifier starting circuit 2 starts and stops the amplifying operation of each of the sense amplifier driving circuits 4A, 4B and 4C. In the memory cell block 19, a large number of memory cells are arranged in a matrix, and a large number of word lines 7 and a large number of bit lines 8 exist. Although connected to the bit lines, this structure is a well-known structure of a memory cell block, and their display is omitted. Further, a large number of memory cell blocks, 19, and sense amplifier blocks are alternately arranged on the left side in the figure, but their display is omitted in FIG.

  Here, a feature of the semiconductor memory device according to the present embodiment is that the power supply voltage switching circuits 1A, 1B, and 1C that receive the external power supply potential VDD and the internal step-down power supply potential VINT lower than the power supply potential VDD are provided for each of the sense amplifier rows 5. For example, each of the provided sense amplifier drive circuits 4A, 4B, and 4C is individually provided, and power is supplied to drive power supply wirings 12a, 12B, and 12C extending in parallel with the bit line 8. The point is that the voltage switching circuits 1A, 1B, and 1C are connected. In other words, the sense amplifier is controlled in units of the sense amplifier block 10 according to general common sense, but in the present embodiment, the sense amplifier drive circuit group arranged along the bit line over the plurality of sense amplifier blocks 10 For example, a power supply voltage switching circuit 1A is provided for each sense amplifier drive circuit group extracted from only the sense amplifier drive circuit 4A in each sense amplifier block 10.

  The power supply voltage switching circuits 1A, 1B, 1C receive the bank selection signal Sbs input via the wiring 11, switch the output signal between the external power supply voltage VDD and the internal step-down power supply potential VPP, and change the output signal. It is supplied to each of the sense amplifier drive circuits 4A, 4B, 4C via drive power supply wirings 12A, 12B, 12C. The drive power supply wirings 12A, 12B, and 12C are connected to each other by a power supply connection wiring 13, but the power supply connection wiring 13 is not necessarily provided.

  When receiving the address selection signal Sas via the wiring 14, the sense amplifier activation circuit 2 outputs a sense amplifier activation signal Ssa for starting and stopping the operation of amplifying the memory cell data at the address. Ssa is sent to the sense amplifier driving circuits 4A, 4B, 4C via the wiring 15.

  FIG. 2 is a circuit diagram showing a connection relationship between the configuration inside the sense amplifier 5 and the sense amplifier control circuit 3X. As shown in the figure, the sense amplifier 5 includes a memory cell data amplifier circuit 24 provided on the bit line 8 and a pair of shared switches provided on the bit line 8 with the memory cell data amplifier circuit 24 interposed therebetween. 25A and 25B (switching MOS transistors). Each gate of each of the shared switches 25A and 25B is connected to the sense amplifier control circuit 3X via wirings 16A and 16B, respectively. That is, although FIG. 1 shows only one wiring 16 for connecting between the sense amplifier control circuit 3X and each sense amplifier 5, it is actually a pair of wirings.

  The sense amplifier control circuit 3X receives the address selection signal Sas, outputs shared switch control signals SctA and SctB for controlling the gate potentials of the shared switches 25A and 25B from the wirings 16A and 16B, and outputs the shared switch control signal SctA. , SctB controls ON / OFF of the shared switches 25A, 25B. That is, when one of the shared switches 25A is opened, the data of the memory cell 9 is taken into the memory cell data amplifier circuit 24 via the bit line 8. When the other shared switch 25B is opened, data of a memory cell (not shown) arranged on the left side in the figure is taken into the memory cell data amplifier 24.

  Each of the sense amplifier driving circuits 4A, 4B, and 4C receives an external power supply VDD or an internal step-down potential VINT supplied via the driving power supply wirings 12A, 12B, and 12C, and a sense amplifier start signal Ssa, and drives the sense amplifier. A signal Ssd is output, and this sense amplifier drive signal Ssd is supplied to the sense amplifier 5 in each of the sense amplifier rows 6A and 6B via the sense amplifier power supply potential wiring 17.

  Note that the bank selection signal Sbs may be a signal for distinguishing activation between a low power consumption mode such as a CBR refresh operation and a self-fresh operation and an external access operation mode.

-Circuit operation-
Next, the operation of the semiconductor memory device having the above configuration will be described.
First, at the time of the selection operation of a certain memory cell 9, the outputs of the power supply voltage switching circuits 1A, 1B, 1C are switched from the internal step-down power supply potential VINT during standby to the external power supply potential VDD by the bank selection signal Sbs. In parallel with this, in the sense amplifier block 10 selected across the memory cell block 19, the shared switch control signal SctA (or SctB) for controlling the gate potential of the shared switch 25A (or 25B) is activated. , The memory cell data read onto the bit line 8 is taken into the sense amplifier 5. After the memory cell data is fetched, the sense amplifier start signal Ssa is activated, and the sense amplifier driving circuits 4A, 4B, 4C start operating. Then, the potential of the sense amplifier power supply potential line 17 is switched from the bit line precharge level to the external power supply potential VDD, and the sense amplifier 5 performs an operation of amplifying the memory cell data.

  The supply path of the power supply voltage of the sense amplifier 5 at the time of amplifying the memory cell data differs depending on the location. That is, a path through which the power supply voltage is supplied from the power supply voltage switching circuit 1A via the sense amplifier drive circuit 4A and the drive power supply wiring 12A, and a power supply voltage via the sense amplifier drive circuit 4B and the drive power supply wiring 12B. There is a path supplied from the power supply voltage switching circuit 1B, and a path supplied from the power supply voltage switching circuit 1C via the sense amplifier driving circuit 4C and the driving power supply wiring 12C.

  When a predetermined time has elapsed after the amplification of the memory cell data, the power supply voltage switching circuits 1A, 1B, 1C return the potentials of the drive power supply wirings 12A, 12B, 12C from the external power supply potential VDD to the internal step-down power supply potential VINT. When the potential of the shared switch control signal Sct rises in accordance with this timing and the gate potential of the shared switch 25A (or 25B) is boosted to the word line boosted potential VPP, a rewrite operation is started. This timing can be adjusted using, for example, a delay circuit for the wiring 11 through which the above-described bank selection signal Sbs flows.

  Here, the bank selection signal Sbs is divided into a low power consumption mode such as a CBR refresh and a self refresh operation and an external access operation mode, and the power supply voltage switching operation by the power supply voltage switching circuits 1A, 1B and 1C is performed in a low power consumption operation. It is preferable to adopt a configuration that is not performed in the mode. The reason is that the supply voltage is increased when the sense amplifier 5 is accessed. The reason is that in order to shorten the time required for the access, it is necessary to take out the data from the sense amplifier 5 immediately after receiving the address selection signal from the column decoder. This is because, for this, data must be rapidly amplified in the sense amplifier 5 before the address selection signal Sas from the column decoder is input. However, since the CBR refresh operation, the self-refresh operation, and the like are performed independently of external access, it is not necessary to increase the speed as described above. Therefore, a control irrelevant to external access such as CBR refresh and self-refresh is set to the low power consumption mode, and only in the external access operation mode, the supply voltage to the sense amplifier is switched from the internal step-down potential VINT to the external power supply voltage VDD. May be performed.

-Effect-
As described above, in the semiconductor memory device of the present embodiment, the power supply voltage switching circuits 1A, 1B, and 1C are arranged along the bit lines 8 as the power supply voltage sources of the sense amplifiers. Are separately provided for each of the above, it is possible to supply charges required for data amplification by the sense amplifier 5 from these voltage switching circuits 1A, 1B, 1C when amplifying memory cell data. Insufficient supply of charges required for Hi-side data amplification, which has occurred when the sense amplifiers 5 in the sense amplifier arrays 6A and 6B are simultaneously activated, can be prevented, and the data amplification speed of the sense amplifier can be increased.

  In particular, since the sense amplifier driving circuits 4A, 4B, 4C are connected by the driving power supply wirings 12A, 12B, 12C extending from the power supply voltage switching circuits 1A, 1B, 1C along the bit lines 8, the supply of electric charge is performed. The effect of improving the ability is increased. The reason is that the number of sense amplifiers connected to the wiring connecting each of the sense amplifier drive circuits 4A, AB, and AC along the direction of the word line 7 is, for example, about 1,000, whereas the drive power supply When the sense amplifier circuits 4A, 4B, 4C are connected along the bit line 8 direction by the supply lines 12A, 12B, 12C, the number of sense amplifiers connected to the drive power supply lines 12A, 12B, 12C is This is because the load is reduced to about 1/9 to 1/8, and the load on the drive power supply wirings 12A, 12B, and 12C is significantly reduced.

  Further, in a low power consumption mode such as CBR refresh or self refresh operation, that is, when relatively high speed data amplification operation of the sense amplifier is not relatively required, a control structure in which the bank selection signal Sbs is not generated in this operation mode is adopted. Therefore, only in this operation mode, the power supply voltage switching circuits 1A, 1B, 1C do not control the switching of the power supply voltage, so that the drive power supply wirings 12A, 12B, 12C to the sense amplifier drive circuits 4A, 4B, 4C are In addition, it is possible to eliminate the charge / discharge of the wiring due to the potential change with the sense amplifier power supply potential wiring 17, and to reduce the CBR current, the self-refresh current, and the like.

(Second embodiment)
Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to the drawings.

−Configuration−
This embodiment also employs the configuration of the sense amplifier 5 and the sense amplifier control circuit 3X shown in FIG. 2 described in the first embodiment.

  FIG. 3 is a circuit diagram showing a specific configuration of the sense amplifier control circuit 3X according to the present embodiment. As shown in FIG. 3, the sense amplifier control circuit 3X includes a PMOS transistor 28 for supplying the word line boosted potential VPP to the gates of the shared switches 25A and 25B, a ground potential VSS and an external power supply potential VDD (VDDmax = VPP-Vtn). , An NMOS transistor 30 receiving the output of the inverter 29 at the drain, and an inverter 31 of a power supply voltage VPP for supplying the gate (node 2) potential of the NMOS transistor 30. Here, node 1 is a node between the output side of the inverter 29 and the drain of the NMOS transistor 30, node 2 is a node between the output side of the inverter 31 and the gate of the NMOS transistor 30, and node 3 is This is a node connected to the gate of the PMOS transistor 28.

-Circuit operation-
FIG. 4 is a timing chart showing the sequence of the shared switch control signals SctA and SctB and the operation sequence of the sense amplifier control circuit 3X for generating the control signals SctA and SctB during the read operation of the semiconductor memory device according to the present embodiment. .

  As shown in the figure, when the word line of the memory cell block 19 is selected (timing tws in the figure), the inverter 29 is driven by the rise of the address selection signal Sas. The shared switch control signal SctA to the shared switch 25A on the selected word line side is boosted from the node 1 via the NMOS transistor 30 to a value determined by the potential of the node 1 by the external power supply (potential VDD). At this time, since the potential of the node 3 is still the word line boosted potential VPP, the PMOS transistor 28 is off. Since the potential of the node 2 is the standby word line boosted potential VPP, the NMOS transistor 30 is on. Therefore, the shared switch control signal SctA of the shared switch 25A is set to the external power supply potential VDD when VDD ≦ VPP−Vtn (Vtn is the threshold voltage of the NMOS transistor 30), and to the potential when VDD> VPP−Vtn. (VPP-Vtn). That is, when the external power supply potential VDD is at a low voltage, the voltage is raised to the potential VDD, and when the external power supply potential VDD is at a high voltage, the voltage is raised to the potential (VPP-Vtn).

  Subsequently, when the sense amplifier activation signal Ssa transitions from the ground potential VSS to the external power supply potential VDD (timing trw in the figure), the potential of the node 2 becomes the ground potential VSS, and then the potential of the node 3 becomes the ground potential VSS. Transition. At this time, the NMOS transistor 30 is turned off and the PMOS transistor 28 is turned on. Then, the shared switch control signal SctA to the shared switch 25A is boosted to the word line boosted potential VPP for rewriting data to the memory cell via the PMOS transistor 28.

  On the other hand, when the word line is reset (timing twr in the figure), the potential of the node 3 changes to the word line boosted potential VPP (the PMOS transistor 28 is turned off) due to the fall of the address selection signal Sas, and continues. The reset of the sense amplifier start signal Ssa (fall from the external power supply potential VDD to the ground potential VSS) changes the potential of the node 2 to the word line boosted potential VPP (the NMOS transistor 30 is turned on). The shared switch control signal SctA is reduced to the ground potential VSS which is the potential of the node 1 via the NMOS transistor 30.

  Note that the boost timing of the shared switch control signal SctA for rewriting data to the memory cell (timing trw in the figure) is, as shown by the broken line in FIG. 4, a certain time later than the rise of the sense amplifier start signal Ssa. It may be timing. Alternatively, the boost timing of the shared switch control signal SctA for the rewriting may be set to a timing that is later by a fixed time from the rise of the address selection signal Sas.

  Here, the shared switch control signal SctB of the shared switch 25B of the non-selected memory cell block (not shown in FIG. 2 but existing to the left of the sense amplifier control circuit 3X) is set during the above operation. , And at the ground potential VSS.

-Effect-
As described above, in the semiconductor memory device according to the present embodiment, the gate potential (shared switch control signal SctA) of the shared switch 25A is set to the external power supply potential VDD for a certain period in which the sense amplifier 5 amplifies the memory cell data. Since the voltage is held, the charge (load) for charging / discharging the bit line 22 on the memory cell side from the shared switch 25A by the sense amplifier 5 is reduced particularly when the external power supply potential VDD is low. For this control, it is not necessary to perform the operation of opening the shared switch 25A from the closed state during the operation of taking in the memory cell data into the sense amplifier as in the above-mentioned prior art. It is possible to increase the operation speed including the activation of the sense amplifier 5 without causing such difficulty in timing adjustment.

  During the data rewriting operation (timing trw in FIG. 4), the gate potential (shared switch control signal SctA) of the shared switch 25A, which has already been boosted to the external power supply potential VDD (or VPP-Vtn), is boosted to the word line. Since it is only necessary to raise the potential to the potential VPP, the potential difference that needs to be boosted by the word line boosted potential generating circuit (not shown) is determined by the difference between the word line boosted potential VPP and the external power supply potential VDD (VPP to VDD). ). Therefore, the boosted potential difference can be greatly reduced as compared with the boosted potential difference (VPP to VSS) conventionally required, and the charge supply capability of the word line boosted potential generation circuit can be suppressed. Therefore, it is possible to reduce the power consumption of the word line boosted potential generation circuit and to reduce the chip area by reducing the smoothing capacity by suppressing the charge supply capability.

(Third embodiment)
Next, a semiconductor memory device according to a third embodiment of the present invention will be described with reference to the drawings.

−Configuration−
FIG. 5 is a circuit diagram illustrating a schematic configuration of the semiconductor memory device according to the present embodiment.

  As shown in the figure, the semiconductor memory device according to the present embodiment includes, in addition to the configuration of the semiconductor memory device according to the first embodiment, an output signal (drive power source) of power supply voltage switching circuits 1A, 1B, and 1C. A voltage switching timing generation circuit 18 for controlling the timing of switching the power supplied to the sense amplifier driving circuits 4A, 4B, 4C via the supply lines 12A, 12B, 12C to the external power supply potential VDD and the internal step-down potential VINT. It has. In the present embodiment, a power supply voltage control circuit is configured by the power supply voltage switching circuits 1A, 1B, 1C and the voltage switching timing generation circuit 18. Further, a shared switch control signal Sct (shared switch control signals SctA, SctB), which is an output signal of the sense amplifier control circuit 3, is supplied to the internal step-down power supply potential VINT for a certain period when the memory cell data is amplified by the sense amplifier 5. It is configured to hold the potential (VINT + Vtn) obtained by adding the potential of the threshold voltage (Vtn) of the NMOS transistor 30 (see FIG. 3). Other configurations are the same as those of the semiconductor memory device according to the first embodiment.

  Further, in the present embodiment, the voltage switching timing generation circuit 18 is connected to the wiring 11 and receives the bank selection signal Sbs as an input signal. However, in the first embodiment, the voltage switching timing generation circuit 18 outputs the sense amplifier activation signal Ssa. It has the same circuit configuration as the sense amplifier starting circuit 2.

  FIG. 6 is a circuit diagram showing a configuration of the sense amplifier control circuit 3Y in the present embodiment.

  As shown in the figure, the sense amplifier control circuit 3Y in the present embodiment is different from the sense amplifier control circuit 3X in the second embodiment in that an inverter 44 provided at a stage preceding the node 6 and an inverter 44 are provided. An NMOS transistor 46 provided between the NMOS transistor 31 and the NMOS transistor 30, and two NMOS transistors 47 and 48 provided on a power supply line connected to the node 5 between the NMOS transistor 46 and the NMOS transistor 30. And a circuit 49 for determining a potential when the power is turned on. However, nodes 1, 2, and 3 in FIG. 3 are displayed as nodes 4, 5, and 6 in FIG. The drain of the NMOS transistor 47 is connected to a power supply for supplying the internal step-down power supply potential VINT.

−Operation−
In the semiconductor memory device according to the present embodiment, the power supply potential switching operation of the power supply voltage switching circuits 1A, 1B, 1C is controlled by the voltage switching timing generation circuit 18 during the memory cell selection operation. That is, the voltage of the drive power supply lines 12A, 12B, and 12C is switched from the internal step-down potential VINT to the external power supply potential VDD, and the drive power supply lines 12A, 12B, and 12C after a predetermined time has elapsed from the amplification of the memory cell data. Is switched from the external power supply potential VDD to the internal step-down power supply potential VINT in accordance with the data amplification operation of the sense amplifier 5.

  The shared switch control signal Sct is changed from the potential (VINT + Vtn) to the word line boosted potential VPP in accordance with the voltage switching timing of the sense amplifier power supply lines 12A, 12B, and 12C from the external power supply voltage VDD to the internal step-down power supply potential VINT. The voltage is boosted, and a data rewrite operation is performed.

  FIG. 7 is a timing chart showing the sequence of the shared switch control signal Sct and the operation sequence of the sense amplifier control circuit 3Y that generates the signal Sct during the read operation of the semiconductor memory device according to the present embodiment.

  As shown in the figure, when the word line of the memory cell block 19 is selected (timing tws in the figure), the inverter 29 is driven by the rise of the address selection signal Sas. The shared switch control signal Sct is driven and boosted by an external power supply. At this time, the node 5 is boosted by the self-boot effect of the NMOS transistor 30 from the potential (VPP-Vtn) of the difference between the standby word line boosted potential VPP and the threshold voltage Vtn of the NMOS transistor 30. However, the maximum value of the potential of the node 5 is determined by the NMOS transistor 47 and the NMOS transistor 48 by the potential (VINT + 2) obtained by adding the internal step-down potential VINT and the threshold voltages of the NMOS transistors 47 and 48 (both are assumed to be Vtn). × Vtn). At this time, the PMOS transistor 28 is off and the NMOS transistor 30 is on. Therefore, the voltage value of the shared switch control signal Sct is set to the maximum value potential (VINT + Vtn) by the nodes 4 and 5 and the NMOS transistor 29. However, this maximum value varies depending on the value of the external power supply potential VDD of the node 4. When the external power supply potential VDD is lower than the potential (VINT + Vtn), the maximum value becomes the external power supply potential VDD, and the external power supply voltage VDD is higher than the potential (VINT + Vtn). In this case, the potential becomes (VINT + Vtn).

  Subsequently, when the sense amplifier activation signal Ssa transitions from the ground potential VSS to the external power supply potential VDD (timing trw in FIG. 4), the potential of the node 5 becomes the ground potential VSS, and then the potential of the node 6 becomes the ground potential VSS. Transition. At this time, the NMOS transistor 30 is turned off and the PMOS transistor 28 is turned on. Then, the shared switch control signal SctA to the shared switch 25A is boosted to the word line boosted potential VPP for rewriting data to the memory cell via the PMOS transistor 28.

  On the other hand, when the word line is reset (timing twr in the figure), the potential of the node 6 transitions to the word line boosted potential VPP (the PMOS transistor 28 is turned on) due to the fall of the address selection signal Sas, and continues. The reset of the sense amplifier start signal Ssa (fall from the external power supply potential VDD to the ground potential VSS) changes the potential of the node 5 to the potential (VPP-Vtn) (the NMOS transistor 30 is turned on), so the shared switch 25A The shared switch control signal SctA is lowered to the ground potential VSS which is the potential of the node 4 via the NMOS transistor 30.

  Note that the boost timing of the shared switch control signal Sct for rewriting data to the memory cell (timing trw in the figure) is later by a certain time than the rise of the sense amplifier start signal Ssa as shown by the broken line in FIG. It may be timing. Alternatively, the boost timing of the shared switch control signal Sct for the rewriting may be set to a timing that is later than the rising edge of the address selection signal Sas by a certain time.

-Effect-
As described above, the semiconductor memory device of the present embodiment holds the potential (VDD + Vtn) obtained by adding the internal step-down power supply potential VINT and the threshold voltage Vtn of the NMOS transistor to the shared switch control signal Sct for a certain period. By providing the control circuit 3Y, the gate potentials of the shared switches 25A and 25B can be suppressed to the potential (VINT + Vtn) or less when the read data is amplified by the sense amplifier 5. As a result, as in the first and second embodiments, the bit line load on the sense amplifier 5 is reduced for a certain period during the data amplification. For the above-described reason, the data amplification operation at the time of low voltage is performed. Higher speed can be achieved.

  In addition, in the present embodiment, even if the potential of the sense amplifier power supply potential wiring 17 is switched to the external power supply voltage VDD by the power supply voltage switching circuits 1A, 1B, and 1C, the connection to the sense amplifier 5 is performed with the shared switches 25A and 25B interposed therebetween. Therefore, the potential of the bit line 8 on the memory cell side can be suppressed to an internal step-down power supply potential VINT or less without excessively raising the potential to the external power supply voltage VDD, and the reliability of the memory cell transistor 9 can be improved.

  In this case, by making the configuration of the voltage switching timing generation circuit 18 the same as that of the sense amplifier activation circuit 2, when the data is amplified by the sense amplifier 5, the drive in accordance with the amplification timing of the memory cell data by the sense amplifier 5 The potential of the power supply wirings 12A, 12B, and 12C can be switched from the external power supply voltage VDD to the internal step-down power supply potential VINT. As a result, the timing of switching the potentials of the drive power supply lines 12A, 12B and 12C from the external power supply voltage VDD to the internal step-down power supply potential VINT, and the potential of the shared switch control signal Sct from the potential (VINT + Vtn) to the word line boost potential Since the timing of switching to VPP can be relatively matched, the speed of the rewrite operation can be increased while ensuring the reliability of the memory cell transistor 9.

(Fourth embodiment)
Next, a semiconductor memory device according to a fourth embodiment of the present invention will be described with reference to the drawings.

−Configuration−
FIG. 8 is a circuit diagram illustrating a schematic configuration of the semiconductor memory device according to the present embodiment. The semiconductor memory device according to the present embodiment is different from the semiconductor memory device according to the third embodiment in that the power supply voltage switching circuit and the voltage switching timing generation circuit are paired with a memory cell array, a sense amplifier, etc. interposed therebetween. The difference is that they are provided.

  That is, as shown in FIG. 8, the memory cell array & sense amplifier unit 41 including the memory cell array and the sense amplifier block 10 (a part of the memory cell block 19 and the sense amplifier block 10 are shown in FIG. 5). A pair of voltage switching units 52T and 52B are provided with the power supply voltage switching circuits 1AT, 1BT, 1CT and 1AB, 1BB and 1CB and the voltage switching timing generation circuits 18T and 18B, respectively. . However, the detailed structure of the memory cell array & sense amplifier unit 41 can be easily understood from FIG. Then, between the power supply voltage switching circuit 1AT and the power supply voltage switching circuit 1AB, between the power supply voltage switching circuit 1BT and the power supply voltage switching circuit 1BB, and between the power supply voltage switching circuit 1CT and the power supply voltage switching circuit 1CB, respectively. They are connected by drive power supply wirings 12A, 12B and 12C for supplying output signals to the sense amplifier drive circuits 4A, 4B and 4C.

  Here, although not shown in FIG. 8, the voltage switching timing generation circuits 18T and 18B adjust the difference between the times when the bank selection signal Sbs reaches the voltage switching timing generation circuits 18T and 18B from the source. A circuit for performing the operation is provided.

−Operation−
Also in this embodiment, the voltage switching operation of the drive power supply wirings 12A, 12B, and 12C is the same as the operation described in the third embodiment. However, in the voltage switching units 52T and 52B provided with the memory cell array interposed, the difference in the arrival time of the bank selection signal Sbs, which is the activation signal, to each circuit is adjusted by the voltage switching timing circuits 18T and 18B, and the driving is performed. The operation of switching the potentials of the power supply wirings 12A, 12B, 12C is performed at the same timing.

  In addition, also in the present embodiment, since the voltage switching timing circuits 18T and 18B have the same configuration as the sense amplifier starting circuit 2, the switching operation is performed in synchronization with the start and stop operations of the sense amplifier 5. Done.

-Effect-
As described above, in the semiconductor memory device of the present embodiment, the voltage switching timing circuits 18T and 18B and the power supply voltage switching circuits 1AT to 1CT and 1AB to 1CB are provided on both sides of the memory cell array & sense amplifier unit 41. Therefore, even when the number of simultaneously selected word lines per memory cell array increases with an increase in storage capacity, by maintaining a high charge supply capability during data amplification by the sense amplifier, the data amplification speed of the sense amplifier can be reduced. Higher speed can be achieved.

(Fifth embodiment)
Next, a semiconductor memory device according to a fifth embodiment of the present invention will be described with reference to the drawings.

−Configuration−
FIG. 9 is a circuit diagram illustrating a schematic configuration of the semiconductor memory device according to the present embodiment.

  The semiconductor memory device according to the present embodiment is based on the premise that the semiconductor memory device has the same configuration as the semiconductor memory device described in the first embodiment. However, the power supply voltage switching circuits 1A, 1B, 1C shown in FIG. 1 need not always be provided, or the power supply voltage switching circuits may be provided at the positions shown in FIG. Although a sense amplifier control circuit and a sense amplifier drive circuit are not shown, these circuits are generally also provided.

  As shown in FIG. 9, the semiconductor memory device according to the present embodiment includes a word line selection signal generation circuit 61, a word line drive signal generation circuit 62, a word line drive circuit 63, and a sense amplifier activation circuit 2X. ing. The sense amplifier activation circuit 2X according to this embodiment has the same circuit configuration as the word line selection signal generation circuit 61 and the dummy word line selection signal generation circuit 67 having the same circuit configuration as the word line selection signal generation circuit 61. It is characterized in that a dummy word line drive signal generation circuit 68, a dummy word line drive circuit 69 having the same circuit configuration as the word line drive circuit 63, and a delay circuit 70 for timing adjustment are provided. Note that the word line selection signal generation circuit 61, word line drive signal generation circuit 62, and word line drive circuit 63 shown in FIG. 9 are also provided in the semiconductor memory devices according to the above embodiments. The memory cell 9 in which the memory cell transistor 64 and the memory cell capacitor 65 are arranged is arranged in the memory cell block 19 shown in FIG. 1, and the sense amplifier 5 is the sense amplifier array 6A shown in FIG. 6B, but are shown here in an isolated state to facilitate understanding of the operation.

  Reference numeral 74 denotes a wiring to which a row address signal (row block selection signal) Srb, which is a start signal of the word line selection signal generating circuit 61, is input, and reference numeral 75 denotes a wiring to which a word line start signal Swa is input. Further, similarly to the configuration shown in FIG. Wiring such as the wiring 15 through which the signal Ssa flows is provided.

−Operation−
First, the word line setting operation will be described.

  The word line drive signal generation circuit 62 operates in response to the word line activation signal Swa, and then the word line selection signal generation circuit 61 operates in response to the row address signal Srb, and the output signal of the word line drive signal generation circuit 62 and the word line The word line drive circuit 63 is driven by the output signal of the selection signal generation circuit 61, and the memory cell selection word line 7 is activated. By the activation of the memory cell selecting word line 7, charges are read from the memory cell 9 to the bit line 8 through the memory cell transistor 64. The charge read from the memory cell 9 is amplified by the sense amplifier 5 activated by the sense amplifier activation signal Ssa. After the completion of the operation of setting the word line 7 (the operation of taking the charge read from the memory cell into the sense amplifier 5), the operation of setting the sense amplifier activation signal Ssa is started.

  Next, a word line reset operation will be described.

  First, the word line drive signal generation circuit 62 is reset by resetting the word line start signal Swa. Thus, the reset of the potential of the word line 7 to the ground potential VSS via the word line drive circuit 63 starts. Subsequently, the word line selection signal generating circuit 61 is reset by resetting the word line activation signal Swa. After the reset operation of the word line 7 is completed, the reset operation of the sense amplifier start signal Ssa is started.

  Next, a set operation by the sense amplifier start signal Ssa will be described.

  First, similarly to the activation of the memory cell selection word line 7, the dummy word line drive signal generation circuit 68 is operated by the word line activation signal Swa, and subsequently, the dummy word line selection signal generation circuit 67 is activated by the row address signal Srb. Operates, and the dummy word line drive circuit 69 is activated by the output signal of the dummy word line drive signal generation circuit 68 and the output signal of the dummy word line selection signal generation circuit 67. The output signal of the dummy word line drive circuit 69 is output as a sense amplifier start signal Ssa via the delay circuit 70. At this time, the delay circuit 70 has a delay value such that the timing shift of the sense amplifier activation signal Ssa with respect to the rising timing of the memory cell selection word line 7 is optimized. That is, when the potential of the word line 7 rises and data comes out of the memory cell 9, the timings of both are adjusted so that the sense amplifier 5 is operated to start the data amplification operation.

  Next, a reset operation of the sense amplifier activation signal Ssa will be described.

  After the reset operation of the word line 7 is completed, the dummy word line drive signal generation circuit 68 is reset by resetting the word line activation signal Swa. Thus, the reset operation by the sense amplifier start signal Ssa starts via the dummy word line drive circuit 69 and the delay circuit 70. Subsequently, the word line selection signal generation circuit 67 is reset by resetting the row address signal Srb. The delay circuit 70 has such a delay value that the deviation of the fall timing of the sense amplifier activation signal Ssa with respect to the fall timing of the memory cell selection word line 72 is optimized.

-Effect-
As described above, the semiconductor memory device according to the present embodiment includes a circuit (the word line selection signal circuit 61, the word line selection signal circuit 61, the word line selection signal circuit 61) for controlling the operation from generation of the memory cell selection word line 7 to selection and reset. (A line drive signal generation circuit 62, a word line drive circuit 63), and a circuit (dummy word line selection signal circuit 67, dummy word line drive signal generation circuit 68) for controlling generation of the sense amplifier start signal Ssa and operations up to reset. , The dummy word line driving circuit 69) have the same circuit configuration, so that the potential of the memory cell selecting word line 7 depends on the power supply voltage, the temperature, and the process variation (for example, the variation in the gate length of the transistor). And the power supply voltage dependency, temperature dependency, and process variation dependency of the start / stop timing of the sense amplifier 5 Door can be. That is, since the potential of the word line 7 and the sense amplifier start-up signal Ssa have almost the same direction and the degree of change in the timing according to the change of the power supply voltage, temperature, etc., the influence of the change of these parameters is obtained. Therefore, it is possible to minimize the margin of the expected timing, and as a result, the speed of data amplification by the sense amplifier can be increased.

  However, since the timing as a whole does not need to be largely disrupted by the change of each parameter, for example, only the dummy word line selection signal generation circuit 67 may have the same layout as the word line selection signal generation circuit 61. Further, the dummy word line drive signal generation circuit 68 does not have to have the same layout as the word line drive signal generation circuit 62. Furthermore, the dummy word line drive circuit 69 does not have to have the same layout as the word line drive circuit 63.

  Next, FIG. 10 is a circuit diagram showing a configuration of a semiconductor memory device according to a modification of the present embodiment. As shown in the figure, the sense amplifier activation circuit 2Y does not include the dummy word line drive signal generation circuit 68 as shown in FIG. It is configured to output the sense amplifier start signal Ssa in response to the output and the word line boosted potential VPP. According to the configuration of this modified example, the circuit configuration can be simplified while exhibiting the same effects as those of the semiconductor memory device of the present embodiment as described above.

  Here, as the activation signal of the word line selection signal generation circuit 61 and the word line activation signal Swa, for example, a normal word line selection signal, which is an output signal of a redundancy judgment circuit, or a redundancy word line selection signal, is used. If the stop timing is shared, the circuit configuration can be further simplified. In other words, since the potential of the word line 7 and the sense amplifier start-up signal Ssa have a common direction and the degree of change in the timing according to the change of the power supply voltage, temperature, etc., the influence of the change of these parameters is not affected. The margin of the expected timing can be minimized, and as a result, the speed of data amplification by the sense amplifier can be increased.

(Sixth embodiment)
Next, a semiconductor memory device according to a sixth embodiment of the present invention will be described with reference to the drawings.

−Configuration−
FIG. 11 is a circuit diagram showing a part of the memory cell array of the semiconductor memory device according to the present embodiment, and FIG. 12 is a cross-sectional view showing the structure of the memory cell of the semiconductor memory device according to the present embodiment. This embodiment also assumes the configuration of the semiconductor memory device shown in FIG. However, the power supply voltage switching circuits 1A, 1B, 1C shown in FIG. 1 are not provided. The word line selection signal generation circuit 61, word line drive signal generation circuit 62, word line drive circuit 63, and sense amplifier activation circuit 2 shown in FIG. 9 or FIG. It is assumed that you have.

  As shown in FIG. 11, the semiconductor memory device according to the present embodiment includes a memory cell 9 used for reading and writing data, and a memory cell selecting word line that also functions as a gate of a memory cell transistor of each memory cell 9. 7 is provided. Further, a dummy memory cell 82 comprising a memory cell transistor and a memory cell capacitor having the same structure as the memory cell 9 and not usually used for data read / write, and the same material as the memory cell selecting word line 7 is used. A dummy wiring 81 provided to alleviate a step between the region and the sense amplifier unit and not used for normal memory cell selection; and a level detection circuit 83 for detecting the level of the dummy wiring 81, The delay circuit 70 shown in FIG. 9 or FIG. 10 is constituted by 81 and the level detection circuit 83. The level detecting circuit 83 is characterized in that the logical threshold is set by changing the ratio of the transistor size and the like. Note that a separating word line 84 connected to the ground is provided to separate the bit line 8 from the dummy bit line 86.

  Next, a cross-sectional structure of the memory cell portion of the semiconductor memory device according to the embodiment will be described. As shown in FIG. 12, the semiconductor memory device according to the present embodiment includes a memory cell selecting word line 7 serving as a gate electrode of a memory cell transistor of a memory cell 9, a separating word line 84, and a memory cell of a dummy cell 82. Dummy wirings 81 serving as word lines of transistors are arranged in order. At this time, the dummy wiring 81 is provided at the end of the memory cell array, that is, at the boundary between the memory cell section and the sense amplifier section, and reduces the step between the memory cell section and the sense amplifier section on the substrate. It is configured as follows.

−Operation−
The sense amplifier start signal Ssa, which is an output signal of the dummy word line drive circuit 69 in the sense amplifier start circuit 2X (or 2Y) shown in FIG. 9 or FIG. When input to the detection circuit 83, the following operation is performed. That is, the signal is transmitted to the level detection circuit 83 via the dummy wiring 81 having the same load 82 as the word line 7 used for memory selection, and the level detection circuit 83 outputs the sense amplifier start signal Ssa. At this time, the RC characteristic that determines the delay time of the dummy wiring 81 has the same characteristic as that of the memory cell selecting word line 7. The level detection circuit 83 is provided with a hysteresis characteristic, and the logic threshold is set to (bit line precharge potential) + (threshold voltage Vtn of memory cell transistor) + (back bias) when the dummy wiring 81 rises. At the time of falling, the threshold voltage is set to (the threshold voltage VtnLow of the memory cell transistor). Here, VtnLow is a threshold voltage when the source-substrate voltage is small. As a result, the level detection circuit 83 outputs the sense amplifier start signal Ssa whose rising and falling timings respectively correspond to the timing when the gate of the memory cell transistor opens and closes.

-Effect-
As described above, the semiconductor memory device according to the present embodiment includes the dummy wiring 81 having the same load as the memory cell selection word line 7 used for reading and writing data, and the level detection circuit 83 having hysteresis characteristics. Since the delay circuit 70 in the sense amplifier activation circuit 2 is configured, the output timing of the sense amplifier activation signal Ssa is adjusted according to the RC characteristics of the memory cell selecting word line 7, the reading of memory cell data, and the memory cell transistor. Can be adjusted to the gate opening / closing timing, and the amplification operation of the sense amplifier 5 can be accelerated (especially at a low voltage) by optimizing the operation timing of the sense amplifier 5.

Further, in the cross-sectional structure of the semiconductor memory device, there is generally a step between the memory cell portion and the sense amplifier portion. This is because a memory cell has members necessary for forming a memory cell capacitor such as a storage node, a capacitance film, and a cell plate, whereas a member corresponding to such a memory cell capacitor is provided in a sense amplifier portion. Is not present. Here, in the memory cell of the present embodiment, as shown in FIG. 12, the dummy wiring 81 and the dummy bit line 86 are arranged at the end of the memory cell portion, so that the step can be reduced as much as possible. . (Note: Is there any effect of providing the separating word line 84?)
(Seventh embodiment)
Next, a semiconductor memory device according to a seventh embodiment of the present invention will be described with reference to the drawings.

−Configuration−
FIG. 13 is a plan view showing a wiring structure forming a delay circuit in the semiconductor memory device according to the present embodiment. The semiconductor memory device of the present embodiment has the same circuit configuration as a circuit having a dummy wiring 81, a dummy cell 82, a level detection circuit 83, and a separating word line 84 as shown in FIG.

  That is, as shown in FIG. 13, in the semiconductor memory device according to the present embodiment, a dummy wiring 91 made of the same material (for example, polysilicon) as the memory cell selecting word line 7 and the dummy wiring 91 are used as gates. An NMOS transistor 92, a level detection circuit 93 which receives the signal of the dummy wiring 91 as an input and detects the level thereof, and a wiring 94 which is made of the same material as the memory cell selecting word line 7 and whose level is fixed to the ground potential VSS. 95 and a sense amplifier starter circuit having a delay circuit consisting of 95. Reference numeral 95 denotes a wiring for supplying a potential to the source / drain of the NMOS transistor 92, and reference numeral 96 denotes a contact hole connecting the wiring 95 and the source / drain of the NMOS transistor 92. The wiring 95 is made of the same material as the bit line (for example, aluminum alloy, polycide, etc.), and the contact hole 96 has the same opening area and the same opening area as the contact hole connecting the bit line and the source / drain of the memory cell transistor. It has a depth.

  Dummy wiring 91 has substantially the same thickness, width (gate length) and length as memory selection word line 7, and NMOS transistor 92 uses one common memory cell selection word line 7 as a gate. It is formed in a meandering manner so as to have almost the same channel region as the entire channel region of the NMOS transistors of many memory cells 9. Further, the dummy wiring 91 has an interlayer insulating film interposed between the wiring 94 and the wiring 95, and has the same capacity as the capacitance between adjacent wirings that the actual memory cell selecting word line 7 receives from the unselected word line 7. They are formed adjacent to each other at a distance so as to have a capacity. As in the sixth embodiment, the logical threshold value of the level detection circuit 93 is (bit line precharge potential) + (threshold voltage Vtn of memory cell transistor) + (back bias effect). Is set to

−Operation−
A sense amplifier start signal Ssa, which is an output signal of the dummy word line drive circuit 69 in the sense amplifier start circuit 2X (or 2Y) shown in FIG. 9 or FIG. When input to the detection circuit 93, the following operation is performed. That is, the dummy wiring 91 is sandwiched between the wirings 94 and 95 whose potential is fixed to the ground potential VSS and has the same transistor gate capacitance as that of the memory cell selecting word line 7, so that the memory cell It has substantially the same wiring load as the selection word line 7. Then, the sense amplifier activation signal Ssa is transmitted to the level detection circuit 93 via the dummy wiring 91. Thus, the time (delay time) required from the input to the output to the dummy wiring 91 to the output has the same RC characteristic as that of the actual memory cell selecting word line 7. As in the sixth embodiment, the logical threshold value of the level detection circuit 93 is (bit line precharge potential) + (threshold voltage Vtn of memory cell transistor) + (back bias effect). The sense amplifier activation signal Ssa is output in synchronization with the data read timing from the memory cell in addition to the characteristics of the memory cell selection word line 7. Further, the level detection circuit 93 is provided with a hysteresis characteristic, and the logical threshold value is set at the time of rising of the dummy wiring 91 (bit line precharge potential) + (threshold voltage Vtn of the memory cell transistor) + (back bias effect component). At the time of falling, the threshold voltage VtnLow of the memory cell transistor is set at the time of falling so that the sense amplifier activation signal 73 is output in synchronization with both rising and falling. Here, VtnLow is a threshold voltage when the source-substrate voltage is small.

-Effect-
As described above, in the semiconductor memory device of the present embodiment, the dummy wiring having the same wiring load as the gate capacity of the memory cell selection word line 7 for reading and writing data and the capacity between adjacent wirings is provided. A sense amplifier starter circuit having a delay circuit having the circuit 91 is arranged. This makes it possible to match the output timing of the sense amplifier start signal Ssa with the RC characteristics of the memory cell selecting word line 7 and the read timing of the memory cell data, and the operation of the sense amplifier 5 (particularly at low voltage). The speed of the amplification operation of the sense amplifier 5 can be increased by optimizing the timing of (1).

(Eighth embodiment)
Next, a semiconductor memory device according to an eighth embodiment of the present invention will be described with reference to the drawings.

−Configuration−
FIG. 14 is a circuit diagram showing a configuration of a delay circuit in a sense amplifier starting circuit of the semiconductor memory device according to the present embodiment.

  As shown in the figure, the delay circuit in the sense amplifier starting circuit of the semiconductor memory device according to the present embodiment is configured by inserting a resistor R1 into a drain of a PMOS transistor and a resistor R2 into a drain of an NMOS transistor. A delay element array 100 is provided in which a plurality of sets of inverter elements 101 and gate capacitance load elements 102 each formed by connecting the gates of a PMOS transistor and an NMOS transistor whose source and drain are short-circuited are alternately connected in series. ing. However, the output signal of the dummy word line drive circuit 69 in the start-up circuit 2 shown in FIGS. Further, a level detection circuit 103 for detecting the output level of the delay element array 100 is provided. The delay element array 100 and the level detection circuit 103 correspond to the delay circuit 70 shown in FIG. 9 or FIG. A delay circuit is configured. Here, as a power supply voltage of the inverter element 101 and the gate capacitive load element 102 in the delay element array 100, an internal step-down potential VINT which is a power supply voltage having the same VDD dependency as the external power supply voltage VDD of the word line boosted potential VPP. Is used. The logical threshold value of the level detection circuit 103 is set by changing a ratio such as a transistor size.

−Operation−
The output signal of the dummy word line 91 in the sense amplifier activation circuit is transmitted from the wiring 104 to the level detection circuit 103 via the delay element 100. At this time, the resistance values of the resistance elements R1 and R2 inserted into the drains of the PMOS transistor and the NMOS transistor are sufficiently larger than the resistances of the PMOS transistor and the NMOS transistor, and can take a constant value. Since the time T (= RC) is kept constant, the power supply voltage dependency of the charge / discharge capability is small. In other words, regarding the electrical resistance of the portion formed by connecting a transistor and a resistive element that also function as a resistor in series, if the resistance of the resistive element is much larger than the resistance of the transistor, the resistance of the transistor Does not significantly contribute to the overall resistance value. Since the resistance elements R1 and R2 are made of polysilicon and have low temperature dependence of the resistance value, the resistance of the inverter element 101 including the transistor has low temperature dependence. This suppresses a change in the delay time due to the power supply voltage dependency and the temperature dependency of the performance of the PMOS transistor and the NMOS transistor, and changes the characteristics of the inverter element 101 to the power supply voltage dependency and the small temperature dependency. The selection word line 72 is adapted to the RC delay characteristic. In order to change the delay time of the delay element array 100 between the rise and fall of the potential of the memory cell selection word line 72, the odd-numbered inverter elements 101 and the even-numbered inverter elements 101 having opposite logics to each other are required. What is necessary is just to change the ratio of the resistance values of the resistance element R1 and the resistance element R2 according to the ratio of the rise / fall time of the memory cell selection word line 72.

  Further, the level detection circuit 103 has a change of a logical threshold value and a hysteresis characteristic as in the sixth and seventh embodiments.

-Effect-
As described above, in the semiconductor memory device of the present embodiment, similarly to the sixth and seventh embodiments, the output timing of the sense amplifier activation signal Ssa is changed to the memory cell selecting word line 7 used for reading and writing data. Of the sense amplifier 5 and the read timing of the memory cell data, and the amplification operation of the sense amplifier 5 can be speeded up by optimizing the operation timing of the sense amplifier 5 (particularly at a low voltage). it can.

(Ninth embodiment)
Next, a semiconductor memory device according to a ninth embodiment of the present invention will be described with reference to the drawings.

−Configuration−
FIG. 15 is a circuit diagram showing a schematic configuration of a delay circuit (corresponding to the delay circuit 70 in FIGS. 9 and 10) in the sense amplifier starting circuit of the semiconductor memory device according to the present embodiment. As shown in the figure, the delay circuit according to the present embodiment includes delay element arrays 113 and 114 in which a number of inverter elements are arranged, and delay element arrays 113 and 114 for rising edges and falling edges of an input signal, respectively. , 114, and a level shifter 116 for changing the output level from the internal step-down potential VINT to the external power supply potential VDD. However, the output signal of the dummy word line drive circuit 69 in the start-up circuit 2 shown in FIGS. Each of the delay element arrays 113 and 114 includes an inverter element 111 including a PMOS transistor and an NMOS transistor having a drain inserted with a resistance element R3, and a PMOS transistor and an NMOS transistor having a drain inserted with a resistance element R4. Are alternately and serially arranged.

−Operation−
As described in the sixth embodiment, the output signals of the dummy word line drive circuit 69 in the sense amplifier activation circuit 2 are set to Hi level and Low level in accordance with the rise and fall of the memory cell selecting word line 7, respectively. Transition. At this time, the timing delay characteristics including the power supply voltage dependency are different between the rise and fall of the word line.

  When the sense amplifier is activated, the output signal of the dummy word line driving circuit 69 needs to make the transition timing to the Hi level coincide with the rise of the word line 7, so that the delay element array 114 does not operate as a delay circuit, Only the column 113 is operated as a delay circuit.

  The delay element array 113 outputs the connection between the first-stage PMOS transistor and the resistance element R3, and outputs the connection between the opposite NMOS transistor and the resistance element R4 in the next stage. Here, in the delay element array 113, it is sufficient that the resistance element R3 is inserted into the drain of the NMOS transistor that is turned on among the first-stage inverter elements 111 to which a Hi-level signal is input at the time of rising, and that the off state is set. Since no current flows through the drain of the PMOS transistor, there is no need to insert a resistance element. Similarly, in the second-stage inverter element 112 to which a low-level signal is input at the time of rising, the resistance element R4 may be inserted only into the drain of the PMOS transistor that is turned on. With such a configuration, charge and discharge are performed through the resistance elements R3 and R4 of the delay element array 113 to delay a signal.

  When the sense amplifier is stopped, the output signal of the dummy word line drive circuit 69 input from the wiring 104 needs to make the transition timing to the Low level coincide with the fall of the word line 7. Instead of operating as a delay circuit, only the delay element array 114 is operated as a delay circuit.

  In the delay element array 114, similarly to the delay element array 113, in the first-stage inverter element 111, the resistance element R3 is inserted only into the drain of the NMOS transistor, and in the next-stage inverter element 112, the resistance element is connected only to the drain of the PMOS transistor. It is configured with an element R4 inserted. Like the delay element array 113 already described, at the time of falling, the NMOS transistor of the first-stage inverter element 111 to which the Hi-level signal is input and the second-stage PMOS transistor to which the Low-level signal is input are connected. This is because it is sufficient that a resistance element is inserted. That is, charge and discharge are performed through the resistance elements R3 and R4 of the delay element row 114 to delay a signal.

  Here, the delay element array 114 when the sense amplifier is activated and the delay element array 113 when the sense amplifier is stopped transfer an input signal without passing through the resistance elements R3 and R4. There is no effect on the operation of.

-Effect-
As described above, in the semiconductor memory device according to the present embodiment, in the inverter element forming the delay element row, the resistance element is inserted only into the drain of the PMOS transistor and the NMOS transistor which are turned on at the time of a signal transition among the transistors. , A delay circuit having delay element arrays 113 and 114 formed by combining inverter elements that alternately switch the output node between the drain of the NMOS transistor and the drain of the PMOS transistor is formed. A configuration is adopted in which the start and stop timings of the sense amplifier are individually set. Thus, as in the sixth to eighth embodiments, the output timing of the sense amplifier activation signal Ssa can be adjusted to the RC characteristics of the memory cell selection word line 7 used for reading and writing data. By optimizing the operation timing of the sense amplifier (especially at low voltage), the speed of the sense amplifier amplification operation can be increased. In addition, the number of resistive elements required to obtain the same delay time can be reduced, and the individual timing of rising and falling of the memory cell selecting word line 7 can be easily set.

  The present invention can be used as a DRAM or a system LSI including a DRAM and a logic circuit.

1 is a circuit diagram illustrating a configuration of a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a configuration of a sense amplifier according to the first and second embodiments of the present invention. FIG. 9 is a circuit diagram illustrating a configuration of a sense amplifier control circuit according to a second embodiment of the present invention. FIG. 11 is a timing chart illustrating an operation sequence of the sense amplifier control circuit according to the second embodiment of the present invention. FIG. 11 is a circuit diagram illustrating a configuration of a semiconductor memory device according to a third embodiment of the present invention. FIG. 11 is a circuit diagram illustrating a configuration of a sense amplifier control circuit according to a third embodiment of the present invention. FIG. 11 is a timing chart illustrating an operation sequence of the sense amplifier control circuit according to the third embodiment of the present invention. FIG. 11 is a circuit diagram illustrating a configuration of a semiconductor memory device according to a fourth embodiment of the present invention. FIG. 15 is a circuit diagram illustrating a configuration of a semiconductor memory device according to a fifth embodiment of the present invention. FIG. 21 is a circuit diagram illustrating a configuration of a modification of the semiconductor memory device according to the fifth embodiment of the present invention. FIG. 15 is a circuit diagram illustrating a part of a dummy cell and a memory cell array that constitute a delay circuit according to a sixth embodiment of the present invention. FIG. 14 is a sectional view of a memory cell part of a semiconductor memory device according to a sixth embodiment of the present invention. FIG. 21 is a plan view showing a wiring structure forming a delay circuit arranged in a sense amplifier starting circuit according to a seventh embodiment of the present invention. FIG. 15 is a circuit diagram illustrating a configuration of a delay circuit arranged in a sense amplifier activation circuit according to an eighth embodiment of the present invention. FIG. 21 is a circuit diagram illustrating a configuration of a delay circuit arranged in a sense amplifier activation circuit according to a ninth embodiment of the present invention. FIG. 14 is a circuit diagram showing a configuration of a conventional semiconductor memory device provided with means for switching a power supply potential of a sense amplifier. FIG. 4 is a timing chart showing an operation sequence of a conventional sense amplifier control circuit for performing an operation of turning on and off a shade switch during a read operation, and another conventional sense amplifier control circuit for controlling a gate potential of the shade switch to a low potential during a read operation. It is a timing chart which shows an operation sequence. FIG. 11 is a circuit diagram showing a configuration of a conventional sense amplifier start signal generation delay circuit using an invar and a chain.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Power supply voltage switching circuit 2 Sense amplifier starting circuit 3 Sense amplifier control circuit 4 Sense amplifier drive circuit 5 Sense amplifier 6 Sense amplifier row 7 Word line 8 Bit line 9 Memory cell 10 Sense amplifier block 11 Bank selection signal 12 Drive power supply wiring 13 Power supply connection lines 14 to 18 Wiring 17 Sense amplifier power supply potential wiring 19 Memory cell block Sas Address select signal Sbs Bank select signal Ssa Sense amplifier start signal Sct Shared switch control signal

Claims (12)

A memory cell for storing information;
A word line and a bit line connected to the memory cell;
A sense amplifier for amplifying information stored in the memory cell;
A word line selection signal generation circuit for generating a word line selection signal;
A word signal drive signal generation circuit for generating a word line drive signal;
A word line drive circuit for inputting the word line selection signal and the word line drive signal and driving a word line;
A sense amplifier start signal generation circuit that outputs a start signal of the sense amplifier,
The sense amplifier activation signal generation circuit is configured by a circuit having the same structure as at least one of the word line selection signal generation circuit, the word line drive signal generation circuit, and the word line drive circuit. A semiconductor memory device characterized by the following. 2. The semiconductor memory device according to claim 1,
The word line selection signal generation circuit, the word line drive signal generation circuit, and the sense amplifier activation signal generation circuit are configured to be activated by a normal word line selection signal or a redundancy selection signal that is an output signal of a redundancy judgment circuit. A semiconductor memory device characterized in that: 2. The semiconductor memory device according to claim 1,
First voltage generating means for generating a voltage having little dependency on the external power supply potential within the range of the external power supply potential in accordance with the external power supply potential and applying the voltage to the word line;
A second voltage generating means for generating a voltage having little dependency on the external power supply potential within the range of the external power supply potential and supplying the voltage to at least a part of the sense amplifier start signal generation circuit. A semiconductor memory device comprising: 2. The semiconductor memory device according to claim 1,
A voltage with little dependency on the external power supply potential within the range of the external power supply potential is input to the word line,
A semiconductor memory device characterized in that at least a part of the sense amplifier start signal generation circuit is supplied with a voltage having little dependency on the external power supply potential within a range of the external power supply potential. . 2. The semiconductor memory device according to claim 1,
The sense amplifier start signal generation circuit includes a portion having the same structure as at least one of the word line selection signal generation circuit, the word line drive signal generation circuit, and the word line drive circuit, and a start signal of the sense amplifier. Output delay circuit,
The semiconductor memory device, wherein the delay circuit is formed of a conductor having the same layout structure as the word line. The semiconductor memory device according to claim 5,
A semiconductor memory device, wherein the delay circuit has the same layout structure as a memory cell transistor, and is configured by arranging dummy memory cells not used for storing information. 7. The semiconductor memory device according to claim 6,
A semiconductor memory device, wherein the dummy memory cell is provided at an end of a memory cell region. 2. The semiconductor memory device according to claim 1,
The sense amplifier start signal generation circuit includes a portion having the same structure as at least one of the word line selection signal generation circuit, the word line drive signal generation circuit, and the word line drive circuit, and a start signal of the sense amplifier. Output delay circuit,
The delay circuit includes a third wiring extending opposite to the first and second wirings connected to the ground potential with the insulating film interposed therebetween.
The semiconductor memory device, wherein the third wiring is formed as a gate of a plurality of NMOS transistors. 9. The semiconductor memory device according to claim 8,
A semiconductor memory device, wherein a width and a length of a portion of the third wiring functioning as a gate of an NMOS transistor are the same as a width and a length of a portion of the word line functioning as a gate of the memory cell. . The semiconductor memory device according to claim 9,
The sense amplifier start signal generation circuit includes a portion having the same structure as at least one of the word line selection signal generation circuit, the word line drive signal generation circuit, and the word line drive circuit, and a start signal of the sense amplifier. Output delay circuit,
The delay circuit has a plurality of delay elements in which a plurality of MOS transistors are connected in series with at least one resistance element interposed between their drains, and a gate of each MOS transistor is used as an input unit; A semiconductor memory device comprising the delay elements connected in order so that a connection section between the MOS transistors is used as an output section. The semiconductor memory device according to claim 10,
The semiconductor memory device according to claim 1, wherein the resistance element is interposed only in a portion of the Hi level and the Low level where a signal of a level for instructing start or stop of the sense amplifier flows. The semiconductor memory device according to claim 10,
The plurality of MOS transistors in each of the delay elements are a first conductivity type MOS transistor and a second conductivity type MOS transistor,
Among the plurality of delay elements, a delay element in which the resistance element is interposed between the output section of the delay element and the first conductivity type MOS transistor is a first inversion element, and the resistance element is the first inversion element. When an element interposed between the output part of the delay element and the second conductivity type MOS transistor is used as a second inversion element,
The semiconductor memory device, wherein the delay circuit is configured by alternately connecting the first inversion elements and the second inversion elements.

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