JP2004265021A - Controller and electronic apparatus provided with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a controller which can meet even the replacement of a CPU or a substrate having the CPU mounted thereon by a simple constitution and achieves power saving. <P>SOLUTION: Since it is necessary for a CPU to acquire a processing result after the end of processing in a processing part in order to obtain an accurate processing result from the processing part, a counter part 22 is provided which measures a processing time required for the fixed number of times of delay processing in the CPU 2. A processing speed ratio calculation part 23 is provided which compares the processing time measured by the counter part 22 with a prescribed reference time. A delay value change part 12 is provided which changes the number of times of delay processing (delay value) to be performed by the CPU 2, on the basis of a result obtained by the processing speed ratio calculation part 23. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a control device provided in an electronic device or the like. More specifically, the present invention relates to control of delay processing of an arithmetic operation in an arithmetic processing unit in a control device.
[0002]
[Prior art]
In general, various electronic devices include a control device inside the device. Various processes are executed by the control device. In addition, the control device generally includes a central processing unit (hereinafter, referred to as a CPU).
[0003]
Here, as an example of the above process, a process for determining the remaining battery level of the electronic device will be described with reference to FIGS. FIG. 7 is a circuit diagram showing a battery remaining power detection circuit for detecting the remaining battery power. FIG. 8 is a flowchart when the remaining battery level is detected.
[0004]
As shown in FIG. 7, the battery remaining amount detection circuit includes a first register 51, a battery circuit 52, a reference voltage generation circuit 53, a comparator 54, and a second register 55. The first register 51 receives a command from the CPU and issues a command to the battery circuit 52 to detect the battery voltage. The battery circuit 52 is a circuit for measuring a battery voltage of an electronic device.
[0005]
The reference voltage generation circuit 53 is a circuit that generates a predetermined voltage. The comparator 54 compares the battery voltage detected by the battery circuit 52 with a predetermined voltage generated by the reference voltage generation circuit 53. Then, the comparator 54 transmits the comparison result to the second register 55. Further, the comparison result stored in the second register 55 is read when the CPU accesses the second register 55.
[0006]
Here, after the CPU issues an instruction to the first register 51, it takes time for the battery remaining amount detection circuit to process the comparison result from the second register 55 until the comparison result can be read out. Requires a certain amount of time. That is, there is a time difference between the time when the CPU issues a command to the first register 51 and the time when the CPU can obtain the comparison result from the second register 55. This time difference is hereinafter referred to as a delay time (delay time).
[0007]
Next, the flow at the time of detecting the remaining battery level will be described with reference to FIG.
[0008]
First, the CPU issues a remaining amount detection instruction to the first register 51 (S11). Specifically, for example, a signal “1” is sent to the first register 51. Then, after S11, the battery remaining amount detection process is started (S12).
[0009]
After the battery remaining amount detection process is started in S12, the CPU repeats the delay process until the comparison result is stored in the second register 55 (S13). Here, the delay processing refers to, for example, processing in which a CPU executes a dummy program (hereinafter, referred to as a delay processing program) to delay predetermined arithmetic processing by the CPU. In other words, this is a process of delaying the access timing of the CPU to the comparison result stored in the second register 55.
[0010]
As described above, the reason for performing the delay processing is that, when the CPU issues a command to the first register 51 and immediately accesses the second register 55, the comparison result is still stored in the second register 55 at the time of access. This is because accurate detection of the remaining battery level is not possible. The time required for one delay processing is a time determined according to the dummy program or the like.
[0011]
Therefore, in order for the CPU to obtain an accurate comparison result from the second register 55, it is necessary to repeat the delay processing at least over the delay time when the battery is detected.
[0012]
Therefore, after S13, it is determined whether or not the delay processing has been performed a predetermined number of times (N times) (S14). Note that the predetermined number (N times) is a predetermined value determined in advance according to the processing content. That is, in the battery remaining amount detection process, it is determined in advance that accurate comparison results can be obtained in the second register 55 if the delay process is performed at least N times, and the value is set as a result. The predetermined number (N times) is referred to as a delay value.
[0013]
If the delay process has not been performed N times in S14, the process returns to S13 and repeats the delay process. On the other hand, if the delay processing has been executed N times, the CPU reads the comparison result from the second register 55 and then performs the arithmetic processing. Thus, a series of processing ends.
[0014]
As described above, when detecting the remaining battery level, the CPU reads out the comparison result from the second register 55 after performing the delay processing a predetermined number of times (N times).
[0015]
In the above description, the process of detecting the remaining battery level has been described, but the same applies to the process of returning from the energy saving mode such as the so-called sleep mode to the normal mode. Hereinafter, the return process will be described with reference to FIG. FIG. 9 is a flowchart illustrating a process of returning from the energy saving mode to the normal mode.
[0016]
In the energy saving mode as described above, for example, the memory power supply is turned off (S21). Then, after S21, it is determined whether there is an instruction to return to the normal mode (S22). The instruction to return to the normal mode is issued by, for example, pressing any button provided on the electronic device.
[0017]
If there is an instruction to return to the normal mode in S22, the memory power is turned on and the initialization of the memory is started (S23). On the other hand, when there is no instruction to return to the normal mode, the process returns to S22 again and waits for the instruction to return. After S23, the CPU performs a delay process (S24). This delay processing is the same processing as the above-described delay processing in battery remaining amount detection.
[0018]
After S24, it is determined whether the delay processing has been performed a predetermined number of times (M times) (S25). The predetermined number of times (M times) is a predetermined value determined in advance according to the processing content. That is, in the memory initialization processing, it is determined in advance that the memory initialization is completed if the delay processing is performed at least M times, and the value is set as a result. The predetermined number (M times) is also referred to as a delay value.
[0019]
If the delay process has not been executed M times in S25, the process returns to S24 and repeats the delay process. On the other hand, if the delay process has been executed M times, the CPU starts accessing the memory, and the operation in the normal mode is performed (S26).
[0020]
As described above, when switching from the energy saving mode to the normal mode, the delay processing is performed a predetermined number of times (M times), and the CPU accesses the memory.
[0021]
Here, in an electronic device that performs various processes such as the battery remaining amount detection process and the return process from the energy saving mode as described above, the CPU or a board on which the CPU is mounted may be, for example, a faster process speed. If replaced with a new one, the following problems occur.
[0022]
That is, in the processing shown in FIGS. 8 and 9, the CPU performs the delay processing N or M times to delay the desired processing for a predetermined time, but for example, the CPU is upgraded to a high-speed CPU. In this case, even if the delay processing is performed N times or M times, there is a problem that it is not possible to obtain an accurate comparison result of the remaining battery level or access the memory in a state where the memory has been initialized. .
[0023]
Since the delay processing is performed using a high-speed CPU, even if the delay processing is performed N times or M times, the comparison result of the CPU can be obtained before the predetermined delay time elapses. It is because it starts.
[0024]
Further, even if the number of clocks of the CPU is doubled, for example, the processing speed is not doubled. Therefore, even if the delay value is simply doubled, an accurate result cannot be obtained.
[0025]
Therefore, conventionally, in order to change the delay processing program in accordance with the replacement of the CPU or the like, the ROM itself storing the program has to be replaced with a new ROM.
[0026]
On the other hand, in recent years, a control device that does not require replacement of the ROM or the like has been developed. For example, Japanese Patent Laying-Open No. 1-152554 discloses a control device in which hardware is newly provided and access timing of a CPU can be adjusted without changing a program. According to this control device, the timing of access when the CPU acquires the comparison result from the second register 55, the timing of accessing the memory, and the like can be adjusted.
[0027]
[Patent Document 1]
JP-A-1-152554 (Published date: June 15, 2001)
[0028]
[Problems to be solved by the invention]
However, in the control device described in the above publication, when a plurality of different delay processes need to be performed as described above, it is necessary to provide a delay processing circuit for each process. That is, when there are processes with different delay times, such as the battery remaining amount detection process and the return process from the energy saving mode, separate delay processing circuits corresponding to these processes must be provided.
[0029]
Therefore, there arises a problem that the size of the control device is increased and the cost of the control device is increased.
[0030]
In the control device described in the above publication, it is necessary to operate the delay processing circuit in real time. That is, in various processes, it is necessary to always calculate the access timing of the CPU by the delay processing circuit. For this reason, power is consumed, and it is difficult for the control device to achieve energy saving.
[0031]
The present invention has been made in view of the above problems, and a purpose thereof is to provide a control device capable of coping with the above-described replacement with a simple configuration and achieving energy saving even when a CPU or the like is replaced. Another object of the present invention is to provide an electronic device including the control device.
[0032]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the control device of the present invention includes an arithmetic unit for performing arithmetic processing on digital data, the arithmetic unit performs a predetermined delay process a predetermined number of times, and performs a predetermined time by the arithmetic unit for a predetermined time. In the control device for delaying the arithmetic processing, a measuring means for measuring a processing time required for a predetermined number of delay processings by the arithmetic means, and a comparison for comparing the processing time measured by the measuring means with the predetermined reference time Means, and changing means for changing the number of times of the delay processing performed by the arithmetic means based on the result obtained by the comparing means.
[0033]
In the control device having the above-described configuration, or in a device including the control device (hereinafter, referred to as a control device or the like), the arithmetic unit performs processing with respect to a process performed by the control device or the like (hereinafter, referred to as a predetermined process). After issuing the processing start command, each unit such as the control device executes the above-described predetermined processing. Then, after the above-mentioned predetermined processing is completed, the calculation means obtains the processing result and performs the predetermined calculation processing.
[0034]
That is, in the control device and the like, it takes a predetermined time until the predetermined processing is completed. Therefore, the arithmetic unit obtains the processing result for the first time after the predetermined time has elapsed from the processing start command and performs the predetermined processing. It is configured to perform arithmetic processing.
[0035]
Then, in order to obtain a processing result after a lapse of a predetermined time, in the control device, after the calculation means issues a processing start instruction, the calculation means executes a predetermined delay processing a predetermined number of times.
[0036]
Here, for example, in order to increase the speed of processing in a control device or the like, when the arithmetic means and a board on which the arithmetic means are mounted (hereinafter referred to as arithmetic means and the like) are replaced with new arithmetic means and the like, the same predetermined If the delay processing is performed the same number of times for the processing described above, the following problem occurs. That is, since the processing speed of the arithmetic unit and the like is improved, the arithmetic unit obtains the processing result before the processing performed by the control device and the like ends. For this reason, an accurate processing result cannot be obtained.
[0037]
However, in the configuration of the present invention, first, the processing time required for the delay processing for a fixed number of times is measured by the measuring means. This makes it possible to measure the processing time required for a certain number of delay processes when the arithmetic unit or the like is replaced.
[0038]
Further, the processing time measured by the measuring means and the predetermined reference time, for example, the processing time required by the calculating means and the like for the predetermined number of delay processes before replacing the calculating means and the like, by the comparing means. Can be compared. This makes it possible to compare the processing speed before and after replacing the arithmetic means and the like.
[0039]
Then, the number of times of the predetermined delay processing can be changed by the changing means based on the result obtained by the comparing means. Accordingly, the number of times of the delay processing can be increased by the increase in the processing speed of the arithmetic unit or the like. Therefore, the processing means can acquire the processing result after the same time as before the replacement of the calculation means or the like (that is, after the predetermined time). Therefore, in the above control device, the calculation means can obtain an accurate processing result.
[0040]
Further, even if the predetermined processing performed by the control device or the like is a plurality of different processes, the control device does not perform delay processing for the plurality of different processes when the arithmetic means or the like is replaced. The number of times of processing can be changed. For this reason, in the above-described control device, for example, the configuration of the device can be reduced as compared with a device having a configuration in which a delay circuit is provided for each of a plurality of different processes.
[0041]
Further, as described above, since it is sufficient to change the number of times of the delay processing, it is not necessary to exchange the ROM or the like in which the delay processing program is stored every time the arithmetic means is replaced.
[0042]
Further, as will be described later, if the processing time is measured when the arithmetic unit or the like is replaced, power consumption can be suppressed.
[0043]
Therefore, even when the arithmetic means and the like are replaced, it is possible to provide a control device that can respond to the replacement of the arithmetic means and the like with a simple configuration and achieve energy saving.
[0044]
Further, the control device of the present invention is characterized in that, in the above control device, the comparison by the comparing means is performed by obtaining a ratio between a processing time measured by the measuring means and a predetermined reference time. I have.
[0045]
According to the above configuration, the comparison unit determines the ratio between the processing time measured by the measurement unit and the predetermined reference time. Thus, when the arithmetic means is replaced, the ratio between the processing time required by the replaced arithmetic means for a certain number of delay processes and the reference time can be determined.
[0046]
Therefore, it is possible to compare the processing speed before and after replacing the arithmetic means. This makes it possible to determine the number of times of the delay processing after the replacement of the arithmetic means or the like.
[0047]
Further, in the control device according to the present invention, in the above control device, the measuring means measures a processing time when the calculating means is replaced with a new calculating means.
[0048]
According to the arrangement, the measuring means measures the processing time when the calculating means is replaced with a new calculating means.
[0049]
Therefore, it is only necessary to perform the measurement when the calculation means is replaced, so that power consumption can be suppressed.
[0050]
In the control device according to the present invention, in the control device described above, the predetermined reference time is a processing time required for the arithmetic unit to perform the predetermined number of delay processes.
[0051]
According to the above configuration, when the arithmetic unit or the like is replaced, the comparing unit compares the processing time measured by the measuring unit after the exchange with the processing time required by the arithmetic unit before the replacement for a certain number of delay processes. Will compare.
[0052]
Therefore, the number of delay processes after replacement can be determined based on the number of delay processes before replacement.
[0053]
Further, the control device according to the present invention is characterized in that, in the above control device, the number of times of the predetermined delay processing performed by the calculation means is set for each predetermined calculation processing performed by the calculation means.
[0054]
According to the above configuration, the number of times of the predetermined delay processing performed by the arithmetic means is set for each predetermined arithmetic processing performed by the arithmetic means.
[0055]
Therefore, even when the arithmetic processings having different delay times are performed, the number of times of the delay processing can be changed according to each arithmetic processing after replacing the arithmetic means.
[0056]
Further, the control device according to the present invention is characterized in that, in the above control device, the predetermined number of times is one.
[0057]
According to the above configuration, the measuring unit measures the processing time required for one delay processing.
[0058]
Therefore, it is possible to reduce the time required for the measurement by the measuring means.
[0059]
According to another aspect of the invention, there is provided an electronic apparatus including the above-described control device.
[0060]
According to the above configuration, it is possible to provide an electronic device including a control device capable of responding to the replacement of the arithmetic unit and the like with a simple configuration and achieving energy saving even when the arithmetic unit and the like are replaced. Becomes possible.
[0061]
BEST MODE FOR CARRYING OUT THE INVENTION
One embodiment of the present invention will be described below with reference to FIGS.
[0062]
FIG. 2 is a block diagram showing a schematic configuration of the control device according to the present embodiment. The control device 1 includes a CPU (arithmetic means) 2, a system controller 3, a flash ROM 4, a memory 5, an energy saving circuit 6, a power supply 7, a battery remaining amount detection circuit 8, an EEPROM (electrically erasable / programmable read only memory) 9, and a reference clock. The apparatus includes a generation unit 10, a processing speed comparison unit 11, and a delay value change unit (change unit) 12.
[0063]
The control device 1 is a device mounted on various electronic devices, and controls the operation of the electronic devices.
[0064]
The CPU 2 performs arithmetic processing on digital data. More specifically, it is a central processing unit that performs calculations of various processes performed by the control device. The system controller 3 is a controller for controlling the system of the control device 1. The flash ROM 4 is a storage device that stores a program for a battery remaining amount detection process, a program for a return process from the energy saving mode to the normal mode, and the like. The remaining battery level detection processing and the return processing from the energy saving mode to the normal mode are basically the same as the processing described in FIGS. 8 and 9 in the related art, except for a part of the processing. The differences from the conventional processing will be described later. Further, programs and the like stored in the flash ROM 4 will be described later.
[0065]
The energy saving circuit 6 is a circuit for switching between an energy saving mode such as a so-called sleep mode and a normal mode. For example, when a certain signal is not input to the control device 1 for a certain period of time, the electronic device including the control device 1 is brought into a standby state in which power consumption is reduced more than in a normal standby state. The energy saving circuit 6 performs the process of returning from the energy saving mode to the normal mode as described in the related art.
[0066]
The energy saving circuit 6 turns off the power of the memory 5 when switching from the normal mode to the energy saving mode, and turns on the power of the memory 5 when switching from the energy saving mode to the normal mode. Further, when switching from the energy saving mode to the normal mode, the energy saving circuit 6 executes a recovery processing program stored in the flash ROM 4 (hereinafter referred to as an energy saving recovery processing program).
[0067]
The power supply 7 supplies power to the CPU 2, the system controller 3, the energy saving circuit 6, the remaining battery level detection circuit 8, the reference clock generation unit 10, the processing speed comparison unit 11, and the delay value change unit in the control device 1. I do.
[0068]
The battery remaining amount detection circuit 8 is the same circuit as the circuit shown in FIG. 7 in the related art. The battery remaining amount detecting circuit 8 executes a remaining amount detecting program (hereinafter referred to as a battery remaining amount detecting program) stored in the flash ROM 4 when detecting the remaining battery amount.
[0069]
The reference clock generator 10 generates a reference clock having a fixed number of clocks, and transmits the reference clock to the processing speed comparator 11.
[0070]
When the CPU 2 is replaced, the processing speed comparison unit 11 determines the delay value (that is, the predetermined number of times represented by N times, M times, and the like) corresponding to the CPUs 2 and the like. It compares the speed before and after replacement. Details of the processing speed comparison unit 11 will be described later.
[0071]
Further, the delay value changing unit 12 changes the delay value of the delay processing program stored in the flash ROM 4 based on the result obtained by the processing speed comparison unit 11. The delay processing program will be described later.
[0072]
Next, a program stored in the flash ROM 4 will be described. FIG. 3 is an explanatory diagram showing a program stored in the flash ROM 4.
[0073]
The flash ROM 4 stores at least a basic program, a battery remaining amount detection program, an energy saving return program, a first delay processing program, a second delay processing program, and a program updating program.
[0074]
The basic program is a program used when the electronic device performs a normal process. A specific example is a program in which processing contents for a copying machine, which is an electronic device, to perform a copying operation are described.
[0075]
The battery remaining amount detection program is a program for detecting the remaining amount of the battery using the battery remaining amount detecting circuit 8. Further, the energy saving return program is a program used when returning from the energy saving mode to the normal mode.
[0076]
Further, the first delay processing program and the second delay processing program are dummy programs used to delay a predetermined arithmetic processing of the CPU for a predetermined time. Here, for convenience of explanation, the first delay processing program is a program used in the remaining battery level detection processing and the energy saving recovery processing. Further, a delay value is set in each of the first delay processing program and the second delay processing program. Further, the processing in which the CPU 2 executes the first delay processing program or the second delay processing program is referred to as a predetermined delay processing.
[0077]
The program updating program is a program for changing the delay value described in the first and second delay processing programs. That is, for example, when the remaining battery level is detected, the program is for changing the number (N times) (delay value) of the delay processing (delay processing) performed by the CPU 2. It is a program executed by a delay value changing unit 12 described later.
[0078]
Next, the processing performed by the processing speed comparison unit 11 will be described with reference to FIG. FIG. 1 is a block diagram mainly showing a schematic configuration of the processing speed comparison unit 11.
[0079]
The processing speed comparing section 11 includes a control register section 21, a counter section (measuring means) 22, and a processing speed ratio calculating section (comparing means) 23. The control register section 21 first receives a command from the CPU 2. The contents of the command from the CPU 2 include the start (start) of the processing in the processing speed comparison unit 11, the stop (stop) of the processing, and the deletion (clear) of the comparison result stored in the control register unit 21. is there.
[0080]
In the control device 1, when the CPU 2 is replaced with a new one, the processing in the processing speed comparison unit 11 is started.
[0081]
At the initial setting stage, a predetermined reference counter value is stored in the control register section 21 in advance. This reference counter value is a counter value when the already mounted CPU 2 executes the delay processing program once before the CPU 2 is replaced. The above-mentioned delay value is determined from the above-mentioned counter value and the above-mentioned delay time (delay time).
[0082]
Further, the delay processing program executed by the CPU 2 is selected according to the processing content. For example, in the remaining battery level detection processing, the first delay processing program is selected.
[0083]
Here, when the CPU 2 is replaced with a new one, the counter unit 22 obtains a counter value (hereinafter referred to as a new counter value) when the new CPU 2 executes the delay processing program once. . When obtaining the counter value, a predetermined reference clock generated by the reference clock generator 10 is used. When setting the reference counter value, it is assumed that the counter value is obtained with the same number of clocks as the reference clock.
[0084]
Next, the processing speed ratio calculator 23 compares the new counter value obtained by the counter 22 with the reference counter value. Specifically, the ratio of the new counter value to the reference counter value is obtained. More specifically, a value obtained by dividing the processing speed of the CPU 2 before replacement by the processing speed of the CPU 2 after replacement (hereinafter, referred to as a processing speed ratio) is obtained. The data of the processing speed ratio is stored in the control register unit 21.
[0085]
Next, the delay value changing section 12 changes the delay value in the delay processing program using the processing speed ratio and the program update program in the flash ROM 4. Specifically, a value obtained by dividing the already set delay value by the processing speed ratio is set as a new delay value.
[0086]
Through the above processing, the setting of the delay value after the replacement of the CPU 2 and the like is completed.
[0087]
Next, the above-described series of delay value changing processing will be specifically described with reference to FIG. Here, the battery remaining amount detection process and the energy saving return process will be described as examples. That is, the case where the first delay processing program is used will be described.
[0088]
FIG. 4A is an explanatory diagram showing each delay value of the battery remaining amount detection program and the energy saving return program before CPU replacement. FIG. 4B is an explanatory diagram showing each delay value of the battery remaining amount detection program and the energy saving return program after the CPU replacement.
[0089]
Further, as shown in FIG. 4A, the delay value before the replacement of the CPU 2 is set to 100 in the battery remaining amount detecting process and to 200 in the energy saving returning process. Further, the reference counter value is set to 1000. When the CPU 2 before replacement is represented as a CPU (A), the number of clocks of the CPU (A) is 400 MHz.
[0090]
Here, when the CPU 2 is changed, the CPU 2 after the change is represented as a CPU (B). The number of clocks of the CPU (B) is 800 MHz.
[0091]
When the CPU 2 is exchanged (upgraded) from the CPU (A) to the CPU (B), the counter value measured by the counter unit 22 is assumed to be 400. The reason why the above counter value is small is that the processing speed of the CPU 2 is increasing.
[0092]
Then, the processing speed ratio calculating section 23 obtains a value of 0.4 obtained by dividing 400 by 1000 as the processing speed ratio. After that, as shown in FIG. 4B, the delay value changing unit 12 adds a new value 250, which is a value obtained by dividing the delay value 100 by the processing speed ratio 0.4, to the new battery remaining amount detection process. Set as delay value. On the other hand, as for the above-mentioned energy saving return processing, as shown in the figure, 500 which is a value obtained by dividing the delay value 200 by the processing speed ratio 0.4 is set as a new delay value.
[0093]
With the above processing, the setting of the delay value after the replacement of the CPU 2 is completed.
[0094]
As described above, in the control device 1, even when the CPU 2 is upgraded, the delay time can be made the same as that before the upgrade by increasing the delay value.
[0095]
On the other hand, when performing processing other than the remaining battery level detection processing and the energy saving recovery processing (hereinafter, referred to as other processing), for example, it may be preferable to execute a delay processing program different from the first delay processing program. is there. In this case, the different delay processing program, for example, the second delay processing program shown in FIG. 3 may be separately stored in the flash ROM 4, and the second delay processing program may be executed. In the following, a program that performs the other processing is referred to as another program.
[0096]
Here, a series of delay value change processing when the second delay processing program is used will be specifically described with reference to FIG. 5 as follows.
[0097]
FIG. 5A is an explanatory diagram showing the delay values of the other programs before the CPU replacement. FIG. 5B is an explanatory diagram showing delay values of the other programs after the CPU replacement.
[0098]
Also, as shown in FIG. 5A, the delay value before the replacement of the CPU 2 is set to 500 in the other processing. Further, the reference counter value is set to 3000.
[0099]
When the CPU 2 is changed from the CPU (A) to the CPU (B), the counter value measured by the counter unit 22 is 1500.
[0100]
Then, the processing speed ratio calculator 23 obtains a value of 0.5 obtained by dividing 1500 by 3000 as the processing speed ratio. After that, as shown in FIG. 5B, the delay value changing unit 12 replaces 1000, which is a value obtained by dividing the delay value 500 by the processing speed ratio 0.5, with the new delay value (for the other processes). L times).
[0101]
FIG. 6 is a flowchart of a delay value changing process in the control device according to the present embodiment. Here, a processing flow of the above series of delay value changes will be described with reference to FIG.
[0102]
First, at the same time as power-on, hardware initialization is performed (S1). Then, after S1, it is determined whether or not the CPU 2 has been replaced (S2). If the CPU 2 has been replaced, the processing speed comparing section 11 compares the processing speed of the delay processing program before and after the replacement of the CPU 2 (S3). On the other hand, if the CPU 2 has not been replaced, the change processing ends without changing the delay value.
[0103]
After S3, the delay value in the delay processing program is changed by the delay value changing unit 12 (S4). Thus, the delay value changing process ends.
[0104]
As described above, the control device 1 according to the present embodiment is configured to have the delay value according to the processing content. Therefore, even when it is necessary to perform a plurality of delay processes having different delay values, there is no need to provide a delay processing circuit for each process as in the related art.
[0105]
Further, in the control device 1, since the delay value is changed only when the CPU 2 is replaced, the power consumption is significantly reduced as compared with the conventional configuration in which the delay processing circuit is operated in real time. Can be suppressed. Therefore, the control device 1 can achieve energy saving.
[0106]
Therefore, even when the CPU or the like is replaced, it is possible to cope with the replacement with a simple configuration and achieve energy saving.
[0107]
After the CPU 2 is replaced, the counter value measured by the replaced CPU 2 is newly set as a reference counter value. That is, the counter value obtained by the counter unit 22 is used as the reference counter value stored in the control register unit 21. Thus, when the CPU is further replaced, a new delay value can be set using the delay value after the previous change.
[0108]
Further, in the above description, the reference counter value is a relative value set based on the processing speed of the CPU before replacement, but is not necessarily limited to this. For example, the reference counter value may be an absolute value that makes the value constant. However, in this case, it is necessary to store an initially set delay value corresponding to the reference counter value. This is because it is necessary to calculate a new delay value based on the initially set delay value when the CPU is replaced.
[0109]
In the above description, the delay value is changed when the CPU 2 is replaced. However, the present invention is not limited to this. For example, even when the board on which the CPU 2 is mounted is changed, it is necessary to make the same delay value change. This is because the processing time of the delay processing program changes even when the substrate is replaced.
[0110]
Also, in the above description, the delay processing program is executed once, and the counter value is obtained by the counter section 22, but the present invention is not necessarily limited to this. For example, the counter value may be obtained by executing the delay processing program a plurality of times. However, in this case, the reference count value also needs to be a value corresponding to the plurality of times.
[0111]
In the above description, the energy saving circuit 6 and the remaining battery level detection circuit 8 have been described. However, these are merely examples, and the control device 1 may include various other processing circuits. Good. Further, the configuration including the energy saving circuit 6, the remaining battery level detection circuit 8, and various other processing circuits may be provided not only in the control device 1 but also in a device or the like including the control device.
[0112]
Further, the control method of the delay processing of the CPU 2 performed by the control device 1 includes an arithmetic means for performing arithmetic processing on digital data, and the arithmetic means performs a predetermined delay processing a predetermined number of times, and performs the predetermined processing for a predetermined time. In a delay processing control method for delaying a predetermined arithmetic processing by an arithmetic means, a first step of measuring a processing time required for a predetermined number of delay processings by the arithmetic means, a processing time measured in the measuring step, And a third step of changing the number of times of the delay processing performed by the calculating means based on the result obtained in the second step. It can be said that this is a method of controlling the processing.
[0113]
【The invention's effect】
As described above, the control device of the present invention compares the processing time measured by the measuring means with the processing time required for the delay processing of a fixed number of times by the arithmetic means, and the processing time measured by the measuring means with the predetermined reference time. And a changing means for changing the number of times of the delay processing performed by the calculating means based on the result obtained by the comparing means.
[0114]
Therefore, even when the arithmetic means and the like are replaced, it is possible to provide a control device that can cope with the replacement of the arithmetic means and the like with a simple configuration and can achieve energy saving.
[0115]
Further, in the control device according to the present invention, in the above-mentioned control device, the comparison by the comparing means is performed by obtaining a ratio between the processing time measured by the measuring means and a predetermined reference time.
[0116]
Therefore, it is possible to compare the processing speed before and after replacing the arithmetic means. As a result, there is an effect that the number of times of the delay processing after the replacement of the arithmetic unit or the like can be determined.
[0117]
Further, in the control device according to the present invention, in the control device described above, the measuring means measures a processing time when the arithmetic means is replaced with a new arithmetic means.
[0118]
Therefore, it is only necessary to perform the measurement when the calculation means is replaced, and thus it is possible to suppress power consumption.
[0119]
Further, in the control device according to the present invention, in the control device described above, the predetermined reference time is a processing time required for the arithmetic unit to perform the predetermined number of delay processes.
[0120]
Therefore, there is an effect that the number of delay processes after replacement can be determined based on the number of delay processes before replacement.
[0121]
Further, in the control device according to the present invention, in the above control device, the number of times of the predetermined delay processing performed by the arithmetic means is set for each predetermined arithmetic processing performed by the arithmetic means.
[0122]
Therefore, even when arithmetic operations having different delay times are performed, it is possible to change the number of delay processes according to each arithmetic operation after replacing the arithmetic means.
[0123]
Further, in the control device according to the present invention, in the above control device, the predetermined number of times is one.
[0124]
Therefore, there is an effect that the time required for the measurement by the measuring means can be reduced.
[0125]
As described above, the electronic apparatus of the present invention includes the above-described control device.
[0126]
Therefore, it is possible to provide an electronic device equipped with a control device that can respond to the replacement of the arithmetic means and the like with a simple configuration and achieve energy saving even when the arithmetic means and the like are replaced. This has the effect.
[Brief description of the drawings]
FIG. 1 is a block diagram mainly showing a schematic configuration of a processing speed comparison unit in a control device according to the present embodiment.
FIG. 2 is a block diagram showing a schematic configuration of a control device according to the present embodiment.
FIG. 3 is an explanatory diagram showing a program stored in a flash ROM in the control device.
FIG. 4A is an explanatory diagram showing delay values of a battery remaining amount detection program and an energy saving recovery program before CPU replacement, and FIG. 4B is a battery remaining amount detection program after CPU replacement. FIG. 7 is an explanatory diagram showing delay values of an energy saving return program.
FIG. 5A is an explanatory diagram showing a delay value of the other program before CPU replacement, and FIG. 5B is an explanatory diagram showing a delay value of the other program after CPU replacement. FIG.
FIG. 6 is a flowchart of a delay value changing process in the control device.
FIG. 7 is a circuit diagram showing a battery remaining amount detection circuit for detecting a remaining battery amount.
FIG. 8 is a flowchart for detecting a remaining battery level.
FIG. 9 is a flowchart illustrating a return process from an energy saving mode to a normal mode.
[Explanation of symbols]
1 controller
2 CPU (computing means)
10 Reference clock generator
11 Processing speed comparison unit
12 Delay value change unit (change means)
21 Control register section
22 Counter section (measuring means)
23 Processing speed ratio calculator (comparing means)

Claims (7)

Computing means for computing digital data,
In the control device, wherein the arithmetic unit performs a predetermined delay process a predetermined number of times, and a predetermined time, the predetermined arithmetic process by the arithmetic unit is delayed.
Measuring means for measuring a processing time required for a predetermined number of delay processes by the arithmetic means,
A processing time measured by the measuring means, a comparing means for comparing the predetermined reference time,
A control device, comprising: a change unit that changes the number of times of the delay process performed by the arithmetic unit based on a result obtained by the comparison unit. 2. The control device according to claim 1, wherein the comparison by the comparing unit is performed by calculating a ratio between a processing time measured by the measuring unit and a predetermined reference time. 3. The control device according to claim 1, wherein the measuring unit measures a processing time when the arithmetic unit is replaced with a new arithmetic unit. 4. The control device according to claim 3, wherein the predetermined reference time is a processing time required for the arithmetic unit to perform the predetermined number of delay processes. 5. The control device according to any one of claims 1 to 4, wherein the number of times of the predetermined delay processing performed by the calculation means is set for each predetermined calculation processing performed by the calculation means. The control device according to any one of claims 1 to 5, wherein the predetermined number of times is one. An electronic apparatus comprising the control device according to claim 1.

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