JP2004260805A - Voice decoding apparatus and network telephone set - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a network telephone set in which received packets whose order of arrival is replaced can be relocated in the right order as much as possible before storing the received packets in a FIFO type jitter absorbing buffer. <P>SOLUTION: A voice decoding apparatus is provided with a replacement packet saving means for saving one or a plurality of the received packets, and a packet order replacement control means is provided for outputting, on the basis of the order information of a packet that is received this time and order information of packets saved in the switch packet saving means, a packet in the first transmission order among the received packet and the packets saved in the replacement packet saving means, and saving packets in the replacement packet saving means except for the packet in the first transmission order among the received packet and the packets saved in the replacement packet buffer. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a network telephone using VoIP, such as an Internet telephone, and a voice decoding device.

  For example, an Internet phone for making a voice call using the Internet has already been developed. Internet telephony uses a technology called "VoIP". VoIP (Voice over Internet Protocol) is a technology that enables voice communication on an IP network such as the Internet or an intranet, that is, transmission and reception of voice data.

  Internet telephones are different from conventional telephones in that voice is compressed and then packetized to make a call through an IP network. In this type of communication device, the arrival time of a packet often varies (jitter) depending on the status of the IP network. That is, the interval between packets arriving via the IP network is often not constant. However, in order to output decoded speech continuously on the packet receiving side, it is necessary to pass encoded data to the decoder at regular intervals. Therefore, as shown in FIG. 1, a jitter absorption buffer 101 for absorbing jitter is provided at a stage preceding the decoder 102.

  The jitter absorption buffer 101 includes a plurality of buffer units for storing a plurality of packets. The arriving packets are stored in the buffer section of the jitter absorption buffer 101 in order from the left according to the order information stored in the packets. The packet stored in the leftmost buffer unit is read out at regular intervals and passed to the decoder 102. When one packet is passed to the decoder 102, the other packets in the jitter absorption buffer 101 are shifted one by one to the left. The decoder 102 decodes and outputs the packet (encoded data) passed from the jitter absorption buffer 101.

  In addition to the buffering function for outputting received packets at regular intervals, the jitter absorption buffer is required to have the function of rearranging received packets whose arrival order has been changed to the correct order.To realize these processes simultaneously Has a very complicated configuration.

  By the way, since the buffering function is efficiently implemented in a FIFO (first in first out) format in which received packets can be output at regular intervals in the order of arrival of the received packets, a FIFO type jitter absorbing buffer (FIFO memory) is used as the jitter absorbing buffer. ) May be used. However, when a FIFO type jitter absorption buffer is used as the jitter absorption buffer, the received packets whose arrival order has been changed cannot be rearranged in the FIFO type jitter absorption buffer.

  The present invention relates to a speech decoding apparatus using a FIFO type jitter absorption buffer capable of efficiently realizing a buffering function as a jitter absorption buffer, wherein an audio signal is received before a received packet is stored in the FIFO type jitter absorption buffer. It is an object of the present invention to provide a speech decoding device capable of rearranging received packets whose order has been changed to the correct order as much as possible.

  According to the present invention, in a network telephone using a FIFO type jitter absorbing buffer capable of efficiently realizing a buffering function as a jitter absorbing buffer, the arrival order is stored before the received packet is stored in the FIFO type jitter absorbing buffer. An object of the present invention is to provide a network telephone capable of rearranging received packets in the correct order as much as possible.

  According to a first aspect of the present invention, there is provided a voice decoding apparatus including a FIFO type jitter absorbing buffer as a jitter absorbing buffer, comprising a replacement packet storage unit capable of storing one or a plurality of received packets. Outputs the packet having the earliest transmission order among the received packets and the packets stored in the replacement packet storage unit, based on the order information of the received packets and the packet order information stored in the replacement packet storage unit. A packet order change control means for storing the received packets and the packets stored in each packet replacement buffer except those having the earliest transmission order in the packet replacement means; The packets output from the exchange control means are sequentially stored. A FIFO-type jitter absorption buffer for outputting stored packets in order from the input one, and a decoding means for decoding packets output from the FIFO-type jitter absorption buffer. .

  The packet order change control means includes, for example, a change packet storing means capable of storing one or a plurality of received packets, the order information of the currently received packet and the order information of the packets stored in the change packet storing means. Means for identifying the packet having the earliest transmission order among these packets, means for outputting the packet received this time if the packet having the earliest transmission information is the packet received this time, and transmission information Is the packet stored in the replacement packet storage means, outputs the packet with the earliest transmission order, and outputs the packet with the earliest transmission order among the packets stored in the packet storage. Other packets except the above and the packet received this time are stored in the replacement packet storage means We shall have a means to be used.

  A plurality of the packet order change control means may be provided, each of the packet order change control means may be connected in series, and the packet output from the last packet order change control means may be stored in the FIFO type jitter absorption buffer.

  A second speech decoding apparatus according to the present invention is a speech decoding apparatus having a FIFO type jitter absorption buffer as a jitter absorption buffer, wherein a packet order change control means for controlling the order of received packets, a packet order change control means And a FIFO type buffer for sequentially outputting the stored packets in order from the input one, and for decoding the packets output from the FIFO type jitter absorbing buffer. A packet order changing control means for storing a plurality of received packets, outputting a first received packet after the initialization processing, and outputting order information of the output packets; Means for setting as the order information of the last output packet When the second and subsequent received packets are received after the initialization processing, the currently received packet is stored in the replacement packet storage unit, and the transmission order of the packets stored in the replacement packet storage unit is the lowest. Second means for selecting an earlier packet, third means for determining whether or not the sequence information of the selected packet is the next number after the sequence information of the last output packet, and the order of the packets selected by the third means If the information is the next number after the order information of the last output packet, the packet is output, the output information of the output packet is set as the order information of the last output packet, and the packet is stored. The order information of the packet selected by the fourth means and the third means for setting the replacement packet storing means to the empty state, If the next packet is not the next number in the order information of the packet output and the replacement packet storage means is not full, the packet is stored in the replacement packet storage means as it is, and then the next packet is received. If the sequence information of the packet selected by the fifth means and the third means is not the next number of the sequence information of the last output packet, and the replacement packet storage means is full, And fourth means for setting the order information of the output packet as the order information of the last output packet, and setting the replacement packet storage means in which the packet is stored to an empty state. Alternatively, when the processing is performed by the sixth means, it is determined whether or not the replacement packet storage means is empty, and if the replacement packet storage means is empty. A seventh means is provided for waiting for the next packet to be received in a certain case, and executing the second and subsequent means when the replacement packet storage means is not empty.

  A first network telephone according to the present invention is a network telephone having a FIFO type jitter absorption buffer as a jitter absorption buffer, comprising a replacement packet storage means capable of storing one or a plurality of received packets, On the basis of the order information and the order information of the packets stored in the replacement packet storage means, the received packet and the packet having the earliest transmission order among the packets stored in the replacement packet storage means are output and received. Packet order change control means and packet order change control means for storing, in the packet replacement means, packets except for the packet transmitted and the packet having the earliest transmission order among the packets stored in each packet replacement buffer. Sort the output packets sequentially And a decoding means for decoding the packets output from the FIFO-type jitter absorption buffer, and a FIFO-type jitter absorption buffer for sequentially outputting the stored packets from the input one. Features.

  The packet order change control means includes, for example, a change packet storing means capable of storing one or a plurality of received packets, the order information of the currently received packet and the order information of the packets stored in the change packet storing means. Means for identifying the packet having the earliest transmission order among these packets, means for outputting the packet received this time if the packet having the earliest transmission information is the packet received this time, and transmission information Is the packet stored in the replacement packet storage means, outputs the packet with the earliest transmission order, and outputs the packet with the earliest transmission order among the packets stored in the packet storage. Other packets except the above and the packet received this time are stored in the replacement packet storage means We shall have a means to be used.

  A plurality of the packet order change control means may be provided, each of the packet order change control means may be connected in series, and the packet output from the last packet order change control means may be stored in the FIFO type jitter absorption buffer.

  A second network telephone according to the present invention is a network telephone equipped with a FIFO type jitter absorption buffer as a jitter absorption buffer, wherein packet order rearrangement control means for controlling the order of received packets and output from packet order rearrangement control means are provided. A FIFO type jitter absorbing buffer for sequentially storing packets and outputting the stored packets in order from the input one, and a decoding means for decoding the packets output from the FIFO type jitter absorbing buffer The packet order change control means includes a plurality of replacement packet storage means capable of storing a plurality of received packets, outputs the first received packet after the initialization processing, and finally outputs the output packet order information. Set as the order information of the packet One means, when the second and subsequent received packets are received after the initialization processing, the currently received packet is stored in the replacement packet storage means and transmitted among the packets stored in the replacement packet storage means. The second means for selecting the packet with the earliest order, the third means for judging whether or not the order information of the selected packet is the next number after the order information of the last output packet, and the third means for selecting If the order information of the packet is the next number after the order information of the last output packet, the packet is output, and the order information of the output packet is set as the order information of the last output packet. The fourth means for setting the replacement packet storage means in which the packets have been stored to an empty state, the order of the packets selected by the third means If the information is not the next number in the sequence information of the last output packet and the replacement packet storage means is not full, the packet is stored in the replacement packet storage means as it is, and then the next packet is received. In the case where the sequence information of the packet selected by the fifth means and the third means waiting for the next packet is not the next number of the sequence information of the last output packet and the replacement packet storage means is full. Sixth means for outputting the packet, setting the order information of the output packet as the order information of the last output packet, and setting the replacement packet storage means in which the packet is stored to an empty state; and When the processing is performed by the fourth means or the sixth means, it is determined whether or not the replacement packet storage means is empty. If the stage is empty, a seventh unit is provided for waiting for the next packet to be received, and executing the second and subsequent processes if the replacement packet storage unit is not empty. And

  According to the present invention, in a speech decoding apparatus using a FIFO type jitter absorbing buffer capable of efficiently realizing a buffering function as a jitter absorbing buffer, before storing a received packet in the FIFO type jitter absorbing buffer. Thus, the received packets whose arrival order has been changed can be rearranged in the correct order as much as possible.

  Further, according to the present invention, in a network telephone using a FIFO type jitter absorbing buffer capable of efficiently realizing a buffering function as a jitter absorbing buffer, before storing a received packet in the FIFO type jitter absorbing buffer, Thus, the received packets whose arrival order has been changed can be rearranged in the correct order as much as possible.

  Hereinafter, an embodiment in which the present invention is applied to an Internet telephone will be described with reference to FIGS.

[1] Description of configuration of Internet telephone

  FIG. 2 shows the configuration of the Internet telephone.

  The Internet telephone includes an A / D converter 1, a D / A converter 2, a DSP 3, a microcomputer 4, and a network controller 5.

  The input audio signal is sent to the DSP 3 after being converted into a digital audio signal by the A / D converter 1. In the DSP 3, or in the DSP 3 and the microcomputer 4, the digital audio signal is packetized after being compressed. The obtained packet is sent to the IP network via the network controller 5.

  The packet sent via the IP network is input to the microcomputer 4 via the network controller 5. The packet is decoded in the microcomputer 4 and the DSP 3, or in the DSP 3. The digital audio signal obtained by the decoding is converted into an analog audio signal by the D / A converter 2 and output.

  3, 4, and 5 show first, second, and third configuration examples of the DSP 3 and the microcomputer 4.

  First, a first configuration example shown in FIG. 3 will be described. The DSP 3 includes an encoder 111, a FIFO type jitter absorption buffer (FIFO memory) 122, and a decoder 123. The microcomputer 4 includes an RTP packetizing unit 112, a packet order change control unit 121 including a packet changing buffer (change packet storing means) 120, and the like.

  An input audio signal input to the DSP 3 from the A / D converter 1 (see FIG. 2) is sent to an encoder 111 in the DSP 3. The encoder 111 compresses the input audio signal. The encoded data obtained by the encoder 111 is sent to the RTP packetizer 112 in the microcomputer 4. The RTP packetizer 112 packetizes the encoded data to generate an RTP packet. The generated RTP packet is subjected to predetermined processing by the microcomputer 4 and then transmitted to the IP network via the network controller 5 (see FIG. 2).

  The received RTP packet sent to the microcomputer 4 via the network controller 5 is subjected to predetermined processing by the microcomputer 4 and then sent to the packet order change control unit 121 in the microcomputer 4. After performing a packet order change process described later, the packet order change control unit 121 sends the received packet to the FIFO type jitter absorption buffer 122 in the DSP 3.

  The FIFO type jitter absorption buffer 122 in the DSP 3 holds the input received packets, and outputs the held received packets at regular time intervals in the input order. The decoder 123 in the DSP 3 decodes the received packet sent from the FIFO type jitter absorption buffer 122. The audio signal output from decoder 123 is output to D / A converter 2 (see FIG. 2).

  Next, a second configuration example shown in FIG. 4 will be described. In the configuration example shown in FIG. 4, the RTP packetizer 112 and the packet order change controller 121 provided on the microcomputer 4 side in FIG. 3 are provided on the DSP 3 side. Therefore, the DSP 3 is provided with the encoder 111, the RTP packetizer 112, the packet order rearrangement controller 121 including the packet rearranging buffer 120, the FIFO type jitter absorption buffer (FIFO memory) 122, and the decoder 123.

  Next, a third configuration example shown in FIG. 5 will be described. In the configuration example shown in FIG. 5, the FIFO type jitter absorption buffer (FIFO memory) 122 provided on the DSP 3 side in FIG. 3 is provided on the microcomputer 4 side. That is, the DSP 3 includes the encoder 111 and the decoder 123. The microcomputer 4 includes an RTP packetization unit 112, a packet order change control unit 121 including a packet change buffer 120, a FIFO type jitter absorption buffer 122, and the like. Note that the configuration examples of the DSP 3 and the microcomputer 4 are not limited to those shown in FIGS. 3 to 5, and other configuration examples (for example, in the configuration example of FIG. 3, the RTP packetizing unit 112 is provided on the DSP side, etc.) ) May be used.

[2] Description of Operation of Packet Order Rearrangement Control Unit 121

  The operation of the packet order change control unit 121 will be described with reference to FIGS. Here, it is assumed that only one packet exchange buffer 120 is provided.

  6, Pi (i = 1, 2,..., 6) indicates a received packet, and i indicates order information (sequence number) of the received packet. It is also assumed that P1 is a received packet that has arrived first after an initialization process described later. The order information of the received packet indicates the order in which the encoded data is packetized by the RTP packetizer and then transmitted to the IP network, and is included in the RTP header. The order information is represented by a 16-bit unsigned variable (“0” to “FFFF” in hexadecimal notation), and returns to “0” after reaching “FFFF”.

  As shown in FIG. 6A, when the received packet P1 is first transmitted after the initialization processing, the packet order change control unit 121 stores the received packet P1 in the packet changing buffer 120.

  Next, as shown in FIG. 6B, when the received packet P2 is sent, the packet order change control unit 121 sends the order information N (= 2) of the received packet P2 and the packet changing buffer 120 Is compared with the order information SN (= 1) of the received packet P1 stored in the storage device. Since the received packet P2 received this time (order information N (= 2)) has a later transmission order than the received packet P1 (order information SN (= 1)) stored in the packet swapping buffer 120, the packet swapping buffer After outputting the received packet P1 stored in the buffer 120 to the FIFO type jitter absorption buffer 122, the received packet P2 received this time is stored in the packet replacement buffer 120.

  Next, as shown in FIG. 6C, when the received packet P4 is transmitted, the received packet P4 received this time (order information N (= 4)) is stored in the packet exchange buffer 120. Since the transmission order is later than the packet P2 (order information SN (= 2)), the reception packet P2 stored in the packet exchange buffer 120 is output to the FIFO type jitter absorption buffer 122, and then the reception packet P4 received this time is output. The data is stored in the packet replacement buffer 120.

  Next, as shown in FIG. 6D, when the received packet P3 is sent, the received packet P3 (order information N (= 3)) received this time is stored in the packet exchange buffer 120. Since the transmission order is earlier than the reception packet P4 (order information SN (= 4)), the reception packet P3 received this time is output to the FIFO type jitter absorption buffer 122 while the reception packet P4 is stored in the packet exchange buffer 120. As a result, the packet order is changed.

  Next, as shown in FIG. 6E, when the received packet P5 is sent, the received packet P5 received this time (order information N (= 5)) is stored in the packet replacement buffer 120. Since the transmission order is later than the reception packet P4 (order information SN (= 4)), the reception packet P4 stored in the packet exchange buffer 120 is output to the FIFO type jitter absorption buffer 122, and then the reception packet P5 received this time. Is stored in the packet exchange buffer 120.

  Next, as shown in FIG. 6F, when the received packet P6 is sent, the received packet P6 received this time (order information N (= 6)) is stored in the packet exchange buffer 120. Since the transmission order is later than the reception packet P5 (order information SN (= 5)), the reception packet P5 stored in the packet exchange buffer 120 is output to the FIFO type jitter absorption buffer 122, and then the reception packet P6 received this time is output. Is stored in the packet exchange buffer 120.

  FIG. 7 shows an initialization processing procedure by the packet order change control unit 121.

  The initialization processing shown in FIG. 7 is executed when it is determined that a telephone call can be connected and a telephone call can be made, and when the telephone call processing is broken and reset.

  When it is determined that the call can be connected and the call can be made, or when the call process is broken and reset, the packet exchange buffer 120 is initialized (step 1). Thereafter, the value of the flag F that stores that the initialization process has just been performed is set to 0 (F = 0) (step 2). Then, the current initialization processing ends.

  FIG. 8 shows a packet order change processing procedure by the packet order change control unit 121.

  The packet order change process is executed each time a received packet is sent to the packet order change control unit 121.

  When the received packet is sent to the packet order change control unit 121, the order information N of the received packet is obtained (step 11). N is a 16-bit unsigned variable (binary number).

  Then, it is determined whether or not F = 0 (step 12). If F = 0, it is determined that the received packet received this time is the first received packet after the initialization processing, and the received packet received this time is stored in the packet replacement buffer 120 (step 13). Then, the value of the variable SN indicating the order information of the received packet stored in the packet rearranging buffer 120 is set as the order information N acquired in step 11 (step 14). SN is a 16-bit unsigned variable (binary number). Further, the value of the flag F is set to 1 (F = 1) (step 15). Then, the current packet order change processing ends.

  In step 12, if F = 1, it is determined based on N and SN whether the received packet received this time has a later transmission order than the received packet stored in the packet rearranging buffer 120 or not. (Step 16). Specifically, it is determined whether or not the following expression (1) is satisfied.

  (signed short) ((unsigned short) N− (unsigned short) SN)> 0… (1)

In the above equation (1), signed short means signed 16 bits, and unsigned short means unsigned 16 bits. The operation on the left side of the above equation (1) is performed as follows. First, 16-bit subtraction is performed between unsigned 16-bit N and unsigned 16-bit SN. More specifically, the N unsigned 16bit, the complements for 2 ¹⁶ SN unsigned 16bit (* SN) a binary addition (N + * SN). If the addition results in a carry from the most significant digit, it is ignored. The obtained 16-bit addition result is handled as a signed 16-bit binary number. Then, it is determined whether or not the signed 16-bit binary number, which is the operation result on the left side of the above equation (1), is positive.

The reason why such an operation is performed will be described. Even if the packets are not received in the transmission order, in reality, it rarely occurs that two packets whose transmission orders are very far apart from each other arrive at the receiving device. Here, interchanged transmission order has left 2 ¹⁵ or more packets, it is assumed that there is no such to reach.

Assuming that the transmission order can not ever be reached distant packets exchanged 2 ¹⁵ or more, unsigned short N is the order information of the current received packet, the reception stored in the packet rearranging buffer 120 If it is larger than the unsigned short SN that is the packet order information, the most significant digit of the signed 16-bit binary number, which is the result of the operation on the left side of the above equation (1), is 0, except for the exception described later. It is determined that there is. That is, it is determined that the transmission order of the received packet received this time is later than that of the received packet stored in the packet replacement buffer 120.

The exception is caused by the fact that the order information of the packet transmitted next to the packet whose order information is “FFFF (hexadecimal notation)” returns to “0 (hexadecimal notation)”. When two packets near both sides of the boundary from the point of change from “FFFF (hexadecimal notation)” to “0 (hexadecimal notation)” arrive in the order different from the transmission order, the packet is received this time. The unsigned short N, which is the order information of the packet, becomes a value close to “FFFF (hexadecimal notation)”, and the unsigned short SN, which is the order information of the received packet stored in the packet exchange buffer 120, is “0 (hexadecimal notation). ) "(N> SN), and the difference between them is 2 ¹⁵ or more. In such a case, the most significant value of the signed 16-bit binary number which is the result of operation on the left side of the above equation (1) The digit is 1, and it is determined that the received packet is not positive, that is, it is determined that the transmission order of the received packet received this time is earlier than that of the received packet stored in the packet replacement buffer 120.

Moreover, given that the transmission order can not ever be reached distant packets exchanged 2 ¹⁵ or more, the order information of the packet received this time unsigned short N is stored in the packet rearranging buffer 120 If the received packet is smaller than unsigned short SN, which is the order information of the received packet, the most significant digit of the signed 16-bit binary number that is the result of the operation on the left side of the above equation (1) is 1, except for the exception described later. It is determined that it is not positive. That is, it is determined that the transmission order of the received packet received this time is earlier than that of the received packet stored in the packet replacement buffer 120.

The exception is caused by the fact that the order information of the packet transmitted next to the packet whose order information is “FFFF (hexadecimal notation)” returns to “0 (hexadecimal notation)”. When two packets near both sides of the boundary from the point of change from “FFFF (hexadecimal notation)” to “0 (hexadecimal notation)” arrive in the transmission order, the packet received this time The unsigned short N, which is the order information of the received packet, becomes a value close to "0 (hexadecimal notation)", and the unsigned short SN, which is the order information of the received packet stored in the packet exchange buffer 120, is "FFFF (hexadecimal notation)". (N <SN), and the difference between them is 2 ¹⁵ or more. In such a case, the most significant digit of the signed 16-bit binary number which is the result of the operation on the left side of the above equation (1) is 0, and is determined to be positive. That is, it is determined that the transmission order of the received packet received this time is later than that of the received packet stored in the packet replacement buffer 120.

  If (signed short) ((unsigned short) N− (unsigned short) SN)> 0, the packet received this time has a transmission order later than that of the received packet stored in the packet rearranging buffer 120. After the received packet stored in the replacement buffer 120 is output to the FIFO type jitter absorption buffer 122 (step 17), the received packet received this time is stored in the packet replacement buffer 120 (step 18). Further, the value of the variable SN indicating the order information of the received packet stored in the packet rearranging buffer 120 is set as the order information N acquired in step 11 (step 19). Then, the current packet order change processing ends.

  If it is determined in step 16 that (signed short) ((unsigned short) N− (unsigned short) SN) ≦ 0, the reception packet received this time is stored in the packet replacement buffer 120. Since the transmission order is earlier than that of the packet, the currently received packet is output to the FIFO type jitter absorption buffer 122 (step 20). Then, the current packet order change processing ends.

  In the above embodiment, since the packet order is rearranged only by comparing the sizes, all the packets transmitted from the transmission side to the reception side are not necessarily rearranged in the order from the smallest transmission order to the largest one. Not always. When only one packet rearranging buffer 120 is provided, and packets are received in the order of, for example, P1, P2, P5, P4, P3, and P6, the packet rearrangement controller 121 , P1, P2, P4, P3, P5, and P6 in this order.

  As will be described later, by increasing the number of packet replacement buffers 120, packets can be rearranged in a more accurate order, but for all packets transmitted from the transmission side to the reception side, It is not always possible to rearrange the data in ascending order of transmission.

  By the way, in actual communication, there is no guarantee that a packet transmitted from a transmitting side can always be received by a receiving side, and packet loss may occur. Therefore, if all the packets transmitted from the transmitting side are rearranged in ascending order of transmission order, if packet loss or the like occurs, processing will be stagnated and communication will not be possible. Therefore, in this embodiment, the rearrangement of the packet order is performed only by comparing the magnitudes, thereby preventing the processing from stagnating when a packet loss or the like occurs.

[3] Description of operation of packet order change control section 121 when a plurality of packet change buffers are provided

  Here, as shown in FIG. 9, the operation of the packet order change control unit 121 when the packet order change control unit 121 includes two packet changing buffers 120a and 120b will be described.

  With reference to (a) to (g) of FIG. 10, an operation of the packet order change control unit 121 when two packet changing buffers are provided will be described.

  One of the two packet replacement buffers is referred to as a first packet replacement buffer 120a, and the other is referred to as a second packet replacement buffer 120b.

  In FIG. 10, Pi (i = 1, 2,..., 7) indicates a received packet, and i indicates order information of the received packet. It is also assumed that P1 is a received packet that has arrived first after the above-described initialization processing.

  As shown in FIG. 10A, when the received packet P1 is first transmitted after the initialization processing, the packet order change control unit 121 stores the received packet P1 in the first packet changing buffer 120a. I do.

  As shown in FIG. 10B, when the second received packet P2 is sent after the initialization processing, the packet order change control unit 121 stores the received packet P2 in the second packet changing buffer 120b. save.

  Next, as shown in FIG. 10C, when the received packet P5 is sent, the order information N (= 5) of the received packet P5 received this time and the received packet P5 are stored in the second packet exchange buffer 120b. And compares the received packet P2 with the order information SN2 (= 2).

  Since the received packet P5 received this time (order information N (= 5)) has a later transmission order than the received packet P2 (order information SN2 (= 2)) stored in the second packet exchange buffer 120b, The received packet P1 stored in the first packet replacement buffer 120a is output to the FIFO type jitter absorption buffer 122. Further, after storing the received packet P2 stored in the second packet replacing buffer 120b in the first packet replacing buffer 120a, storing the received packet P5 received this time in the second packet replacing buffer 120b. .

  Next, as shown in FIG. 10D, when the received packet P4 is sent, the order information N (= 4) of the currently received packet P4 and the received packet P4 are stored in the second packet replacement buffer 120b. The received packet P5 is compared with the order information SN2 (= 5).

  The received packet P4 (order information N (= 4)) received this time has a transmission order earlier than the received packet P5 (order information SN2 (= 5)) stored in the second packet exchange buffer 120b. The received packet P5 is stored in the second packet replacement buffer 120b as it is.

  Further, the sequence information N (= 4) of the received packet P4 received this time is compared with the sequence information SN1 (= 2) of the received packet P2 stored in the first packet replacement buffer 120a. Since the received packet P4 received this time (order information N (= 4)) has a later transmission order than the received packet P2 (order information N (= 2)) stored in the first packet replacement buffer 120a, After outputting the received packet P2 stored in the first packet replacement buffer 120a to the FIFO type jitter absorption buffer 122, the received packet P4 received this time is stored in the first packet replacement buffer 120a.

  Next, as shown in FIG. 10E, when the received packet P3 is transmitted, the received packet P3 received this time (order information N (= 3)) is stored in the second packet exchange buffer 120b. Since the transmission order is earlier than the received packet P5 (order information SN2 (= 5)), the received packet P5 is stored in the second packet replacement buffer 120b as it is.

  Since the received packet P3 (order information N (= 3)) received this time has a transmission order earlier than the received packet P4 (order information SN1 (= 4)) stored in the first packet replacement buffer 120a. The received packet P4 is stored in the first packet replacement buffer 120a as it is, and the received packet P3 received this time is output to the FIFO type jitter absorption buffer 122.

  Next, as shown in FIG. 10F, when the received packet P6 is transmitted, the received packet P6 received this time (order information N (= 6)) is stored in the second packet exchange buffer 120b. Since the transmission order is later than the received packet P5 (order information SN2 (= 5)), the received packet P4 stored in the first packet replacement buffer 120a is output to the FIFO type jitter absorption buffer 122. Further, after storing the received packet P5 stored in the second packet rearranging buffer 120b in the first packet rearranging buffer 120a, storing the received packet P6 received this time in the second packet rearranging buffer 120b. .

  Next, as shown in FIG. 10 (g), when the received packet P7 is sent, the received packet P7 received this time (order information N (= 7)) is stored in the second packet exchange buffer 120b. Since the transmission order is later than the received packet P6 (order information SN2 (= 6)), the received packet P5 stored in the first packet replacement buffer 120a is output to the FIFO type jitter absorption buffer 122. Further, after storing the received packet P6 stored in the second packet replacing buffer 120b in the first packet replacing buffer 120a, storing the received packet P7 received this time in the second packet replacing buffer 120b. .

  FIG. 11 shows a packet order change processing procedure performed by the packet order change control unit 121 when two packet changing buffers are provided. The initialization process by the packet order change control unit 121 is the same as that shown in FIG.

  The packet order change process is executed each time a received packet is sent to the packet order change control unit 121.

  When the received packet is sent to the packet order change control unit 121, the order information N of the received packet is obtained (step 31).

  Then, it is determined whether or not the value of the flag F is 2 (step 32). If F = 2, it is determined whether or not the value of the flag F is 1 (step 33). If F = 1 is not satisfied, F = 0, and it is determined that the received packet received this time is the first received packet after the initialization process, and the received packet received this time is stored in the first packet replacement buffer 120a. Save (step 34). Then, the value of the variable SN1 representing the order information of the received packets stored in the first packet exchange buffer 120a is set as the order information N acquired in step 31 (step 35). Further, the value of the flag F is set to 1 (F = 1) (step 36). Then, the current packet order change processing ends.

  If it is determined in step 33 that F = 1, it is determined that the received packet received this time is the second received packet after the initialization processing, and (signed short) ((unsigned short) N It is determined whether-(unsigned short) SN1)> 0 (step 37). If (signed short) ((unsigned short) N− (unsigned short) SN1)> 0, the received packet received this time is stored in the second packet exchange buffer 120b (step 38). Then, the value of the variable SN2 representing the order information of the received packets stored in the second packet exchange buffer 120b is set as the order information N acquired in step 31 (step 39). Further, the value of the flag F is set to 2 (F = 2) (step 43). Then, the current packet order change processing ends.

  If it is determined in step 37 that (signed short) ((unsigned short) N− (unsigned short) SN1) ≦ 0, the received packet stored in the first packet replacement buffer 120a is The data is stored in the second packet exchange buffer 120b (step 40). The received packet received this time is stored in the first packet replacement buffer 120a (step 41). Then, the value of the variable SN2 is set to the value of the variable SN1, and the value of the variable SN1 is set to the order information N acquired in Step 31 (Step 42). Further, the value of the flag F is set to 2 (F = 2) (step 43). Then, the current packet order change processing ends.

  If it is determined in step 32 that F = 2, the received packet received this time is determined to be the third or later received packet after the initialization processing, and (signed short) ((unsigned short) It is determined whether or not N− (unsigned short) SN2)> 0 (step 44). If (signed short) ((unsigned short) N− (unsigned short) SN2)> 0, the received packet stored in the first packet replacement buffer 120a is output to the FIFO type jitter absorption buffer 122 (step 45). After storing the received packet stored in the second packet rearranging buffer 120b in the first packet rearranging buffer 120a (step 46), the received packet received this time is stored in the second packet rearranging buffer 120b. It is stored (step 47).

  Then, the value of the variable SN1 is set to the value of the variable SN2, and the value of the variable SN2 is set to the order information N acquired in Step 31 (Step 48). Then, the current packet order change processing ends.

  If it is determined in step 44 that (signed short) ((unsigned short) N− (unsigned short) SN2) ≦ 0, then (signed short) ((unsigned short) N− (unsigned short) SN1)> 0 Is determined (step 49). If (signed short) ((unsigned short) N− (unsigned short) SN1)> 0, the received packet stored in the first packet replacement buffer 120a is output to the FIFO type jitter absorption buffer 122 (step 50). The received packet received this time is stored in the first packet replacement buffer 120a (step 51). Then, the value of the variable SN1 is set as the order information N acquired in step 31 (step 52). Then, the current packet order change processing ends.

  If it is determined in step 49 that (signed short) ((unsigned short) N− (unsigned short) SN1) ≦ 0, the received packet received this time is output to the FIFO type jitter absorption buffer 122 (step 53). . Then, the current packet order change processing ends.

  In the example illustrated in FIG. 9, two packet replacement buffers are provided in one packet order replacement control unit, but three or more packet replacement buffers may be provided in one packet order replacement control unit.

[4] Description of Embodiment when a plurality of packet order change control units are connected in series

  The configuration of the Internet telephone is the same as that shown in FIG. FIG. 12 shows a configuration example of the DSP 3 and the microcomputer 4. 12, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

  The DSP 3 includes an encoder 111, a FIFO type jitter absorption buffer (FIFO memory) 122, and a decoder 123, similarly to the DSP 3 shown in FIG.

  The microcomputer 4 includes an RTP packetizer 112 and two packet order change controllers 121a and 121b. The two packet order change control units 121a and 121b are connected in series. In this example, the first-stage packet order change control unit 121a is called a first packet order change control unit 121a, and the second-order packet order change control unit 121b is called a second packet order change control unit 121b.

  The first packet order change control unit 121a includes a first packet changing buffer 120a. The second packet order change control unit 121b includes a second packet changing buffer 120b.

  The operation of each of the packet order change control units 121a and 121b will be described with reference to FIGS.

  In FIG. 13, Pi (i = 1, 2,..., 6) indicates a received packet, and i indicates order information of the received packet. It is also assumed that P1 is a received packet that has arrived first after the above-described initialization processing.

  As shown in FIG. 13A, after the initialization processing, when the first received packet P1 is sent to the first packet order change control unit 121a, the first packet order change control unit 121a The received packet P1 is stored in the first packet replacement buffer 120a.

  Next, as shown in FIG. 13B, when the received packet P2 is sent to the first packet order change control unit 121a, the first packet order change control unit 121a checks the order of the received packet P2. The information N (= 2) is compared with the order information SN (= 1) of the received packet P1 stored in the first packet exchange buffer 120a.

  The received packet P2 (order information N (= 2)) received this time has a transmission order later than the received packet P1 (order information SN1 (= 1)) stored in the first packet replacement buffer 120a. The first packet reordering control unit 121a outputs the received packet P1 stored in the first packet reordering buffer 120a to the second packet reordering control unit 121b. No. 1 packet replacement buffer 120a.

  When receiving the received packet P1 from the first packet order change control unit 121a, the second packet order change control unit 121b receives the received packet P1 because it is the first received packet after the initialization processing. P1 is stored in the second packet exchange buffer 120b.

  Next, as shown in FIG. 13C, when the received packet P5 is sent to the first packet order change control unit 121a, the received packet P5 received this time (order information N (= 5)) becomes Since the transmission order is later than the packet P2 (order information SN1 (= 2)) stored in the first packet rearrangement buffer 120a, the first packet rearrangement control unit 121a sets the first packet rearrangement buffer 120a. After outputting the received packet P2 stored in the second packet order rearranging control unit 121b, the received packet P5 received this time is stored in the first packet rearranging buffer 120a.

  When receiving the received packet P2 from the first packet order change control unit 121a, the second packet order change control unit 121b sets the order information N (= 2) of the received packet P2 and the second packet change buffer 120b. Is compared with the order information SN (= 1) of the received packet P1 stored in the storage device.

  The received packet P2 (order information N (= 2)) received from the first packet order change control unit 121a is the received packet P1 (order information SN2 (= 1) stored in the second packet changing buffer 120b. ), The second packet order change control unit 121b outputs the received packet P1 stored in the second packet change buffer 120b to the FIFO type jitter absorption buffer 122, The received packet P2 received from the packet order change control unit 121a is stored in the second packet changing buffer 120b.

  Next, as shown in FIG. 13D, when the received packet P4 is sent to the first packet order change control unit 121a, the received packet P4 received this time (order information N (= 4)) becomes Since the transmission order is earlier than the packet P5 (order information SN1 (= 5)) stored in the first packet rearrangement buffer 120a, the first packet rearrangement control unit 121a sets the first packet rearrangement buffer 120a. The received packet P4 received this time is output to the second packet order rearrangement control unit 121b while the received packet P5 is stored.

  Upon receiving the received packet P4 from the first packet order change control unit 121a, the second packet order change control unit 121b stores the received packet P4 (order information N (= 4)) in the second packet change buffer. Since the transmission order is later than the reception packet P2 (order information SN2 (= 2)) stored in the buffer 120b, the reception packet P2 stored in the second packet exchange buffer 120b is transferred to the FIFO type jitter absorption buffer 122. After the output, the received packet P4 received from the first packet order change control unit 121a is stored in the second packet changing buffer 120b.

  Next, as shown in FIG. 13E, when the received packet P3 is sent to the first packet order change control unit 121a, the received packet P3 received this time (order information N (= 3)) becomes Since the transmission order is earlier than the packet P5 (order information SN1 (= 5)) stored in the first packet rearrangement buffer 120a, the first packet rearrangement control unit 121a sets the first packet rearrangement buffer 120a. The received packet P3 received this time is output to the second packet order rearrangement control unit 121b while the received packet P5 is stored.

  When receiving the received packet P3 from the first packet order change control unit 121a, the second packet order change control unit 121b stores the received packet P3 (order information N (= 3)) in the second packet change buffer. Since the transmission order is earlier than the received packet P4 (order information SN (= 4)) stored in the second packet replacement buffer 120b, the received packet P3 received this time is FIFO-stored while the received packet P4 is stored in the second packet replacement buffer 120b. To the type jitter absorption buffer 122.

  Next, as shown in FIG. 13F, when the received packet P6 is sent to the first packet order change control unit 121a, the received packet P6 received this time (order information N (= 6)) is Since the transmission order is later than the packet P5 (order information SN1 (= 5)) stored in the first packet rearrangement buffer 120a, the first packet rearrangement controller 121a sets the first packet rearrangement buffer 120a. After the received packet P5 stored in the first packet rearranging control unit 121b is output to the first packet rearranging buffer 120a, the received packet P6 received this time is stored in the first packet rearranging buffer 120a.

  When receiving the received packet P5 from the first packet order change control unit 121a, the second packet order change control unit 121b stores the received packet P5 (order information N (= 5)) in the second packet change buffer. Since the transmission order is later than the reception packet P4 (order information SN2 (= 4)) stored in the buffer 120b, the reception packet P4 stored in the second packet replacement buffer 120b is transferred to the FIFO type jitter absorption buffer 122. After the output, the received packet P5 received from the first packet order change control unit 121a is stored in the second packet changing buffer 120b.

  FIG. 14 shows a packet order change processing procedure by the first packet order change control unit 121a, and FIG. 15 shows a packet order change processing procedure by the second packet order change control unit 121b.

  The initialization processing by the first packet order change control unit 121a and the initialization processing by the second packet order change control unit 121b are the same as the initialization processing shown in FIG. However, in the following description, a flag whose value is set to 0 by the initialization processing by the first packet order change control unit 121a is set to F1, and the value is set to 0 by the initialization processing by the second packet order change control unit 121b. The flag performed is F2.

  With reference to FIG. 14, a description will be given of the packet order changing process performed by the first packet order changing controller 121a.

  The packet order change process by the first packet order change control unit 121a is executed every time a received packet is sent to the first packet order change control unit 121a.

  When the received packet is sent to the first packet order change control unit 121a, the order information N of the received packet is obtained (step 111).

  Then, it is determined whether or not F1 = 0 (step 112). If F1 = 0, it is determined that the received packet received this time is the first received packet after the initialization process, and the received packet received this time is stored in the first packet replacement buffer 120a (step 113). . Then, the value of the variable SN1 representing the order information of the received packets stored in the first packet exchange buffer 120a is set as the order information N acquired in step 111 (step 114). Further, the value of the flag F1 is set to 1 (F1 = 1) (step 115). Then, the current packet order change processing ends.

  In step 112, if F1 = 1, it is determined whether or not (signed short) ((unsigned short) N- (unsigned short) SN1)> 0 (step 116). If (signed short) ((unsigned short) N− (unsigned short) SN1)> 0, the received packet stored in the first packet rearranging buffer 120a is output to the second packet order rearranging controller 121b. After that (step 117), the received packet received this time is stored in the first packet replacement buffer 120a (step 118). Further, the value of the variable SN1 is set as the order information N acquired in step 111 (step 119). Then, the current packet order change processing ends.

  If it is determined in step 116 that (signed short) ((unsigned short) N− (unsigned short) SN1) ≦ 0, the received packet received this time is output to the second packet order change control unit 121b. (Step 120). Then, the current packet order change processing ends.

  With reference to FIG. 15, a description will be given of a packet order change process performed by the second packet order change control unit 121b.

  The packet order change processing by the second packet order change control unit 121b is executed every time a received packet is sent from the first packet order change control unit 121a to the second packet order change control unit 121b.

  When the received packet is sent from the first packet order change control unit 121a to the second packet order change control unit 121b, the order information N of the received packet is obtained (step 211).

  Then, it is determined whether or not F2 = 0 (step 212). If F2 = 0, it is determined that the received packet received this time is the first received packet after the initialization processing, and the received packet received this time is stored in the second packet replacement buffer 120b (step 213). . Then, the value of the variable SN2 representing the order information of the received packet stored in the second packet exchange buffer 120b is set as the order information N acquired in step 211 (step 214). Further, the value of the flag F2 is set to 1 (F2 = 1) (step 215). Then, the current packet order change processing ends.

  In step 212, if F2 = 1, it is determined whether or not (signed short) ((unsigned short) N− (unsigned short) SN2)> 0 (step 216). If (signed short) ((unsigned short) N− (unsigned short) SN2)> 0, the received packet stored in the second packet replacement buffer 120b is output to the FIFO type jitter absorption buffer 122 ( (Step 217), the received packet received this time is stored in the second packet exchange buffer 120b (Step 218). Further, the value of the variable SN2 is set as the order information N acquired in step 211 (step 219). Then, the current packet order change processing ends.

  If it is determined in step 216 that (signed short) ((unsigned short) N− (unsigned short) SN2) ≦ 0, the received packet received this time is output to the FIFO type jitter absorption buffer 122 (step 216). 220). Then, the current packet order change processing ends.

  In the example shown in FIG. 12, two packet order change control units are connected in series, but three or more packet order change control units may be connected in series.

[5] Description of Another Example of Operation of Packet Order Rearrangement Control Unit 121

  Hereinafter, another example of the operation of the packet order change control unit 121 will be described.

[5-1] Description of Operation of Packet Order Rearrangement Control Unit 121 When Two Packet Rearranging Buffers 120 Are Provided

  The operation of the packet order change control unit 121 will be described with reference to (a) to (f) of FIG. Here, as shown in FIG. 16, it is assumed that the packet order change control unit 121 includes two packet changing buffers 120a and 120b.

  In FIG. 16, Pi (i = 1, 2,..., 6) indicates a received packet, and i indicates order information (sequence number) of the received packet. It is also assumed that P1 is a received packet that has arrived first after an initialization process described later. The order information of the received packet indicates the order in which the encoded data is packetized by the RTP packetizer and then transmitted to the IP network, and is included in the RTP header. The order information is represented by a 16-bit unsigned variable (“0” to “FFFF” in hexadecimal notation), and returns to “0” after reaching “FFFF”.

  As shown in FIG. 16A, when a received packet (P1 in this example) is first transmitted after the initialization processing, the packet order change control unit 121 converts the received packet P1 into a FIFO type jitter absorbing buffer. 122. Then, the order information N (= 1) of the received packet P1 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 1.

  Next, as shown in FIG. 16B, when the received packet P2 is sent, the received packet P2 is stored in the first packet replacement buffer 120a. Then, the order information N (= 2) of the received packet having the earliest transmission order N (= P2 in this example) among the packets in the packet exchange buffers 120a and 120b is set next to the order information "1" indicated by LN. It is determined whether it is a number.

  The number next to the LN is, in principle, one number larger than the LN, but when LN = “FFFF”, the next number is “0”.

  Since the order information N (= 2) of the received packet P2 having the earliest transmission order N among the packets in the packet exchange buffers 120a and 120b is the next number after the order information "1" indicated by LN, The packet P2 is output to the FIFO type jitter absorption buffer 122. As described above, when the packet P2 stored in the packet replacement buffer 120a is output to the FIFO type jitter absorption buffer 122, the packet replacement buffer 120a storing the packet P2 is set to an empty state. Then, the order information N (= 2) of the received packet P2 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 2.

  Next, as shown in FIG. 16C, when the received packet P4 is sent, the received packet P4 is stored in the first packet replacement buffer 120a. Then, the order information N (= 4) of the received packet with the earliest transmission order N (= P4 in this example) among the packets in the packet exchange buffers 120a and 120b is set next to the order information "2" indicated by LN. It is determined whether it is a number.

  Since the order information N (= 4) of the received packet P4 having the earliest transmission order N among the packets in the packet exchange buffers 120a and 120b is not the number next to the order information "2" indicated by LN, The packet P4 is kept stored in the first packet replacement buffer 120a.

  Next, as shown in FIG. 16D, when the received packet P3 is transmitted, the received packet P3 is stored in the second packet replacement buffer 120b. Then, the order information N (= 3) of the received packet with the earliest transmission order N (= P3 in this example) among the packets in the packet exchange buffers 120a and 120b is set next to the order information "2" indicated by LN. It is determined whether it is a number.

  Since the order information N (= 3) of the received packet P3 having the earliest transmission order N among the packets in the packet rearranging buffers 120a and 120b is the number next to the order information "2" indicated by LN, The packet P3 is output to the FIFO type jitter absorption buffer 122. Then, the order information N (= 3) of the received packet P3 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 3.

  Since the received packet P4 is stored in the packet replacement buffer 120a, the order information N (=) of the received packet with the earliest transmission order N (P4 in this example) among the packets in the packet replacement buffers 120a and 120b. It is determined whether or not 4) is the number next to the order information “3” indicated by LN.

  Since the order information N (= 4) of the received packet P4 having the earliest transmission order N among the packets in the packet rearranging buffers 120a and 120b is the number next to the order information "3" indicated by LN, the reception is performed. The packet P4 is output to the FIFO type jitter absorption buffer 122. Then, the order information N (= 4) of the received packet P4 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 4.

  Next, as shown in FIG. 16E, when the received packet P5 is sent, the received packet P5 is stored in the first packet replacement buffer 120a. Then, the order information N (= 5) of the received packet having the earliest transmission order N (= P5 in this example) among the packets in the packet exchange buffers 120a and 120b is set next to the order information "4" indicated by LN. It is determined whether it is a number.

  Since the order information N (= 5) of the received packet P5 having the earliest transmission order N among the packets in the packet rearranging buffers 120a and 120b is the next number after the order information "4" indicated by LN, The packet P5 is output to the FIFO type jitter absorption buffer 122. Then, the order information N (= 5) of the received packet P5 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 5.

  Next, as shown in FIG. 16F, when the received packet P6 is sent, the received packet P6 is stored in the first packet replacement buffer 120a. Then, the order information N (= 6) of the received packet having the earliest transmission order N (= P6 in this example) among the packets in the packet exchange buffers 120a and 120b is set next to the order information "5" indicated by LN. It is determined whether it is a number.

  Since the order information N (= 6) of the received packet P6 having the earliest transmission order N among the packets in the packet exchange buffers 120a and 120b is the next number to the order information "5" indicated by LN, The packet P6 is output to the FIFO type jitter absorption buffer 122. Then, the order information N (= 6) of the received packet P6 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 6.

[5-2] Description of Operation of Packet Order Rearrangement Control Unit 121 When Three Packet Rearrangement Buffers 120 Are Provided

  The operation of the packet order change control unit 121 will be described with reference to (a) to (g) of FIG. Here, as shown in FIG. 17, it is assumed that the packet order change control unit 121 includes three packet changing buffers 120a, 120b, and 120c.

  In FIG. 17, Pi (i = 1, 2,..., 6) indicates a received packet, and i indicates order information (sequence number) of the received packet. It is also assumed that P1 is a received packet that has arrived first after an initialization process described later.

  As shown in FIG. 17A, when a received packet (P1 in this example) is first transmitted after the initialization processing, the packet order change control unit 121 converts the received packet P1 into a FIFO type jitter absorption buffer. 122. Then, the order information N (= 1) of the received packet P1 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 1.

  Next, as shown in FIG. 17B, when the received packet P2 is sent, the received packet P2 is stored in the first packet replacement buffer 120a. Then, the order information N (= 2) of the received packet (P2 in this example) having the earliest transmission order N among the packets in the packet exchange buffers 120a, 120b, and 120c is replaced with the order information "1" indicated by LN. It is determined whether it is the next number.

  Since the order information N (= 2) of the received packet P2 having the earliest transmission order N among the packets in the packet exchange buffers 120a, 120b, and 120c is the number next to the order information "1" indicated by LN, The received packet P2 is output to the FIFO type jitter absorption buffer 122. As described above, when the packet P2 stored in the packet replacement buffer 120a is output to the FIFO type jitter absorption buffer 122, the packet replacement buffer 120a storing the packet P2 is set to an empty state. Then, the order information N (= 2) of the received packet P2 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 2.

  Next, as shown in FIG. 17C, when the received packet P5 is sent, the received packet P5 is stored in the first packet replacement buffer 120a. Then, the order information N (= 5) of the received packet having the earliest transmission order N (= P5 in this example) among the packets in the packet rearranging buffers 120a, 120b, and 120c is the same as the order information "2" indicated by LN. It is determined whether it is the next number.

  Since the order information N (= 5) of the received packet P5 having the earliest transmission order N among the packets in the packet exchange buffers 120a, 120b, and 120c is not the number next to the order information "2" indicated by LN, The received packet P5 is kept stored in the first packet replacement buffer 120a.

  Next, as shown in FIG. 17D, when the received packet P4 is sent, the received packet P4 is stored in the second packet replacement buffer 120b. Then, the order information N (= 4) of the received packet having the earliest transmission order N (= P4 in this example) among the packets in the packet rearranging buffers 120a, 120b, and 120c is the same as the order information "2" indicated by LN. It is determined whether it is the next number.

  The order information N (= 4) of the received packet P4 having the earliest transmission order N among the packets in the packet exchange buffers 120a, 120b, and 120c is not the number next to the order information "2" indicated by LN. The received packet P4 is kept stored in the second packet exchange buffer 120b.

  Next, as shown in FIG. 17E, when the received packet P3 is sent, the received packet P3 is stored in the third packet replacement buffer 120c. Then, the order information N (= 3) of the received packet having the earliest transmission order N (= P3 in this example) among the packets in the packet exchange buffers 120a, 120b, and 120c is replaced with the order information “2” indicated by LN. It is determined whether it is the next number.

  Since the order information N (= 3) of the received packet P3 having the earliest transmission order N among the packets in the packet exchange buffers 120a, 120b, and 120c is the number next to the order information "2" indicated by LN, The received packet P3 is output to the FIFO type jitter absorption buffer 122. Then, the order information N (= 3) of the received packet P3 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 3.

  Since the received packets P4 and P5 are stored in the packet replacement buffers 120a and 120b, the received packets having the earliest transmission order N among the packets in the packet replacement buffers 120a, 120b and 120c (P4 in this example). It is determined whether or not the order information N (= 4) is the number next to the order information “3” indicated by LN.

  The order information N (= 4) of the received packet P4 having the earliest transmission order N among the packets in the packet exchange buffers 120a, 120b, and 120c is the number next to the order information "3" indicated by LN. The received packet P4 is output to the FIFO type jitter absorption buffer 122. Then, the order information N (= 4) of the received packet P4 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 4.

  Since the received packet P5 is stored in the packet rearranging buffer 120a, the order information N of the received packet having the earliest transmission order N (P5 in this example) among the packets in the packet rearranging buffers 120a, 120b, and 120c is stored. It is determined whether (= 5) is the number next to the order information “4” indicated by LN.

  Since the order information N (= 5) of the received packet P5 having the earliest transmission order N among the packets in the packet exchange buffers 120a, 120b, and 120c is the number next to the order information "4" indicated by LN, The received packet P5 is output to the FIFO type jitter absorption buffer 122. Then, the order information N (= 5) of the received packet P5 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 5.

  Next, as shown in FIG. 17F, when the received packet P6 is sent, the received packet P6 is stored in the first packet replacement buffer 120a. Then, the order information N (= 6) of the received packet having the earliest transmission order N (= P6 in this example) among the packets in the packet exchange buffers 120a, 120b, and 120c is replaced with the order information "5" indicated by LN. It is determined whether it is the next number.

  Since the order information N (= 6) of the received packet P6 having the earliest transmission order N among the packets in the packet exchange buffers 120a, 120b, and 120c is the number next to the order information "5" indicated by LN, The received packet P6 is output to the FIFO type jitter absorption buffer 122. Then, the order information N (= 6) of the received packet P6 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 6.

  Next, as shown in FIG. 17G, when the received packet P7 is sent, the received packet P7 is stored in the first packet replacement buffer 120a. Then, the order information N (= 7) of the received packet with the earliest transmission order N (= P7 in this example) among the packets in the packet rearranging buffers 120a, 120b, and 120c is the same as the order information "6" indicated by LN. It is determined whether it is the next number.

  Since the order information N (= 7) of the received packet P7 having the earliest transmission order N among the packets in the packet exchange buffers 120a, 120b, and 120c is the number next to the order information "6" indicated by LN, The received packet P7 is output to the FIFO type jitter absorption buffer 122. Then, the order information N (= 7) of the received packet P7 is set as the order information LN of the last packet output to the FIFO type jitter absorption buffer 122. That is, LN = 7.

[5-3] Description of Processing Procedure of Packet Order Rearrangement Control Unit 121 Described in FIGS. 16 and 17

  FIG. 18 shows the procedure of the packet order change processing described with reference to FIGS.

  The packet order change process is executed each time a received packet is sent to the packet order change control unit 121.

  When the received packet is sent to the packet order change control unit 121, it is determined whether or not F = 0 (step 301). If F = 0, it is determined that the received packet received this time is the first received packet after the initialization processing, and the received packet received this time is output to the FIFO type jitter absorption buffer 122 (step 302). Then, the order information N of the received packet is set as a value of a variable LN representing the order information of the received packet output last to the FIFO type jitter absorption buffer 122 (step 303). Also, F = 1 is set (step 304). Then, the current packet order change processing ends.

  In step 301, if F = 1, the received packet received this time is stored in an empty buffer among the packet replacement buffers 120 (a plurality of which are provided) (step 305).

  Then, among the received packets stored in the packet exchange buffer 120, the received packet with the earliest transmission order is selected (step 306), and the order information N of the selected received packet is next to the order information indicated by LN. Is determined (step 307).

  When the order information N of the selected received packet is the next number after the order information indicated by LN, the received packet is output to the FIFO type jitter absorption buffer 122 (step 308). In this case, the packet replacement buffer 120 storing the output received packet is set to an empty state. Then, the order information N of the received packet is set as a value of a variable LN representing the order information of the received packet output last to the FIFO type jitter absorption buffer 122 (step 309).

  Thereafter, it is determined whether or not all the packet replacement buffers 120 are empty (step 310). If all the packet replacement buffers 120 are not empty (the reception buffer is stored in at least one packet replacement buffer 120), the process returns to step 306.

  If it is determined in step 310 that all the packet exchange buffers 120 are empty, the current packet order exchange processing ends.

  When it is determined in step 307 that the order information N of the received packet selected in step 306 is not the next number of the order information indicated by LN, it is determined whether the packet replacement buffer 120 is full ( It is determined whether or not the reception buffer is stored in all of the packet replacement buffers 120 (step 311).

  If the packet replacement buffer 120 is full, the received packet selected in step 306 is output to the FIFO type jitter absorption buffer 122 (step 308). Then, the order information N of the received packet is set as a value of a variable LN representing the order information of the received packet output last to the FIFO type jitter absorption buffer 122 (step 309). Then, the process proceeds to step 310.

  If it is determined in step 311 that the packet rearranging buffer 120 is not full, that is, if at least one packet rearranging buffer 120 is empty, the current packet rearranging process ends.

FIG. 11 is a block diagram showing a conventional technique. FIG. 2 is a block diagram illustrating a configuration of an Internet telephone. FIG. 2 is a block diagram illustrating a first configuration example of a DSP 3 and a microcomputer 4. FIG. 4 is a block diagram illustrating a second configuration example of the DSP 3 and the microcomputer 4. FIG. 9 is a block diagram illustrating a third configuration example of the DSP 3 and the microcomputer 4. FIG. 4 is an explanatory diagram for explaining an operation of a packet order change control unit 121. 9 is a flowchart illustrating an initialization processing procedure performed by a packet order change control unit 121. 9 is a flowchart illustrating a packet order change processing procedure performed by a packet order change control unit 121. FIG. 11 is a block diagram showing an embodiment in which the packet order change control unit 121 includes two packet change buffers 120a and 120b. FIG. 9 is an explanatory diagram for describing an operation of a packet order change control unit 121 when two packet changing buffers are provided. 9 is a flowchart illustrating a packet order change processing procedure performed by a packet order change control unit 121 when two packet changing buffers are provided. It is a block diagram showing an embodiment when two packet order change control parts are connected in series. FIG. 9 is an explanatory diagram for explaining an operation of each of the packet order change control units 121a and 121b when two packet order change control units are connected in series. It is a flowchart which shows the packet order change processing procedure by the 1st packet order change control part 121a. It is a flowchart which shows the packet order change processing procedure by the 2nd packet order change control part 121b. FIG. 11 is an explanatory diagram for describing another operation example of the packet order change control unit 121. FIG. 11 is an explanatory diagram for describing another operation example of the packet order change control unit 121. 18 is a flowchart illustrating a procedure of a packet order rearrangement process described with reference to FIGS. 16 and 17.

Explanation of reference numerals

1 A / D converter 2 D / A converter 3 DSP
4 Microcomputer 5 Network controller 111 Encoder 112 RTP packetizer 120, 120a, 120b, 120c Packet replacement buffer (replacement packet storage means)
121, 121a, 121b Packet order change control unit 122 FIFO type jitter absorption buffer (FIFO memory)
123 decoder

Claims (8)

In an audio decoding device including a FIFO type jitter absorption buffer as a jitter absorption buffer,
A replacement packet storage unit capable of storing one or a plurality of received packets, wherein the received packet and the replacement packet are stored based on the sequence information of the currently received packet and the packet sequence information stored in the replacement packet storage unit. Outputs the packet with the earliest transmission order among the packets stored in the packet storage means, and replaces the received packets and the packets stored in each packet replacement buffer except those with the earliest transmission order. Packet reordering control means for storing the packets output from the packet reordering control means, and a FIFO for sequentially storing the packets output from the packet reordering control means and outputting the stored packets in order from the input one. Jitter Absorption Buffer and FIFO Jitter Absorption It speech decoding apparatus according to claim which comprises a decoding means, for decoding the packets outputted from Ffa. The packet order change control means includes:
Replacement packet storage means for storing one or more received packets;
Means for identifying the packet with the earliest transmission order among these packets based on the order information of the packet received this time and the order information of the packets stored in the replacement packet storage means,
If the packet with the earliest transmission information is the packet received this time, the means for outputting the packet received this time, and if the packet with the earliest transmission information is the packet stored in the replacement packet storage means, Means for outputting a packet having the earliest transmission order, and storing the currently received packet and another packet other than the packet having the earliest transmission order among the packets stored in the packet storage in the replacement packet storage means. ,
The speech decoding device according to claim 1, further comprising: A plurality of the packet order change control means are provided, each of the packet order change control means is connected in series, and a packet output from the last packet order change control means is stored in the FIFO type jitter absorption buffer. The speech decoding device according to claim 1, wherein: In an audio decoding device including a FIFO type jitter absorption buffer as a jitter absorption buffer,
Packet order change control means for controlling the order of received packets,
A FIFO type jitter absorbing buffer for sequentially storing the packets output from the packet order rearranging control means and outputting the stored packets in order from the input one, and a packet output from the FIFO type jitter absorbing buffer. A decryption means for decrypting,
The packet order change control means includes:
A plurality of replacement packet storage means capable of storing a plurality of received packets;
First means for outputting the first received packet after the initialization processing and setting the order information of the output packet as the order information of the last output packet;
When the second and subsequent received packets are received after the initialization processing, the currently received packet is stored in the replacement packet storage unit, and the transmission order of the packets stored in the replacement packet storage unit is the lowest. A second means for selecting an earlier packet,
Third means for determining whether or not the sequence information of the selected packet is the next number after the sequence information of the last output packet;
If the order information of the packet selected by the third means is the next number after the order information of the last output packet, the packet is output, and the order information of the output packet is the order of the last output packet. Fourth means for setting as information, and setting the replacement packet storage means in which the packet is stored to an empty state;
If the order information of the packet selected by the third means is not the number next to the order information of the last output packet and the replacement packet storage means is not full, the packet is stored in the replacement packet storage means as it is. A fifth means for storing and then waiting for the next packet to be received;
If the order information of the packet selected by the third means is not the next number following the order information of the last output packet, and the replacement packet storage means is full, the packet is output and the output packet is output. The sixth means for setting the order information of the last packet as the order information of the last output packet, and setting the replacement packet storing means in which the packet was stored to an empty state, and the processing by the fourth means or the sixth means. If performed, it is determined whether or not the replacement packet storage means is empty. If the replacement packet storage means is empty, it waits for the next packet to be received. A seventh means for executing the processing of the second and subsequent means when the storage means is not empty;
An audio decoding device comprising: In a network telephone having a FIFO type jitter absorbing buffer as a jitter absorbing buffer,
A replacement packet storage unit capable of storing one or a plurality of received packets, wherein the received packet and the replacement packet are stored based on the sequence information of the currently received packet and the packet sequence information stored in the replacement packet storage unit. Outputs the packet with the earliest transmission order among the packets stored in the packet storage means, and replaces the received packets and the packets stored in each packet replacement buffer except those with the earliest transmission order. Packet reordering control means for storing the packets output from the packet reordering control means, and a FIFO for sequentially storing the packets output from the packet reordering control means and outputting the stored packets in order from the input one. Jitter Absorption Buffer and FIFO Jitter Absorption Network telephone, characterized in that it comprises a decoding means, for decoding the packets outputted from Ffa. The packet order change control means includes:
Replacement packet storage means for storing one or more received packets;
Means for identifying the packet with the earliest transmission order among these packets based on the order information of the packet received this time and the order information of the packets stored in the replacement packet storage means,
If the packet with the earliest transmission information is the packet received this time, the means for outputting the packet received this time, and if the packet with the earliest transmission information is the packet stored in the replacement packet storage means, Means for outputting a packet having the earliest transmission order, and storing the currently received packet and another packet other than the packet having the earliest transmission order among the packets stored in the packet storage in the replacement packet storage means. ,
The network telephone according to claim 5, further comprising: A plurality of the packet order change control means are provided, each of the packet order change control means is connected in series, and a packet output from the last packet order change control means is stored in the FIFO type jitter absorption buffer. The network telephone according to any one of claims 5 and 6, wherein In a network telephone having a FIFO type jitter absorbing buffer as a jitter absorbing buffer,
Packet order change control means for controlling the order of received packets,
A FIFO type jitter absorbing buffer for sequentially storing the packets output from the packet order rearranging control means and outputting the stored packets in order from the input one, and a packet output from the FIFO type jitter absorbing buffer. A decryption means for decrypting,
The packet order change control means includes:
A plurality of replacement packet storage means capable of storing a plurality of received packets;
First means for outputting the first received packet after the initialization processing and setting the order information of the output packet as the order information of the last output packet;
When the second and subsequent received packets are received after the initialization processing, the currently received packet is stored in the replacement packet storage unit, and the transmission order of the packets stored in the replacement packet storage unit is the lowest. A second means for selecting an earlier packet,
Third means for determining whether or not the sequence information of the selected packet is the next number after the sequence information of the last output packet;
When the order information of the packet selected by the third means is the next number after the order information of the last output packet, the packet is output, and the order information of the output packet is changed to the order of the last output packet. Fourth means for setting as information, and setting the replacement packet storage means in which the packet is stored to an empty state;
If the order information of the packet selected by the third means is not the number next to the order information of the last output packet and the replacement packet storage means is not full, the packet is stored in the replacement packet storage means as it is. A fifth means for storing and then waiting for the next packet to be received;
If the order information of the packet selected by the third means is not the next number after the order information of the last output packet and the replacement packet storage means is full, the packet is output and the output packet is output. The sixth means for setting the order information of the last packet as the order information of the last output packet and setting the replacement packet storing means in which the packet is stored to be empty, and the processing by the fourth means or the sixth means. If the replacement packet storage means is empty, it is determined whether or not the replacement packet storage means is empty. If the replacement packet storage means is empty, it waits for the next packet to be received. A seventh means for executing the processing of the second and subsequent means when the storage means is not empty;
A network telephone comprising:

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