JP2004260208A - Solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve image quality by eliminating KTC noise caused by the substantial capacitance of a PD portion. <P>SOLUTION: In a solid imaging device having an imaging region formed by arranging unit cells including a photoelectric conversion part and a signal scanning circuit on a semiconductor substrate in a shape of a two dimensional matrix, an impurity concentration Na of an n-type region 81 which is the photoelectric device is set in such a relation that 0<Na-Nb<1×10<SP>17</SP>cm<SP>-3</SP>can be satisfied with an impurity concentration Nb of a p-type region 80 below the photoelectric conversion part. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device in which a reading transistor portion for reading signal charges from a photoelectric conversion unit such as a photodiode is improved.

  2. Description of the Related Art In the field of solid-state imaging devices, many technologies related to an amplification type MOS image sensor having an amplification function inside a pixel have been proposed. This MOS image sensor is expected to be suitable for a reduction in pixel size accompanying an increase in the number of pixels and a reduction in chip size. Further, compared to the CCD image sensor, the power consumption is low, and the use of the same CMOS process makes it easy to integrate the sensor portion and peripheral circuits.

  The MOS image sensor is configured by two-dimensionally arranging unit cells constituting one pixel, and the unit cell is configured by a photoelectric conversion element and a transistor. Then, the potential of a signal accumulation unit (generally, a photodiode serving as a photoelectric conversion element) is modulated by signal charges generated by photoelectric conversion by the photoelectric conversion element, and the amplification transistor inside the pixel is modulated by the potential. Thus, an amplification function is provided inside the pixel.

  One of the most important evaluation items in this type of device is a point (white flaw) that is bright (white in the case of black and white) due to an abnormally high output among pixels output in the dark. One of the causes of the white flaw is a leak current from the photoelectric conversion unit. In order to reduce the leak current, it is necessary to keep the photodiode (PD) as a photoelectric conversion element away from the surface of the semiconductor substrate where many causes of the leak current are present, that is, to form the PD deep from the substrate surface.

  However, if a PD is formed deep in the substrate, even if 3.3 V, which is the maximum applied voltage of a device using a CMOS transistor, is applied to the read gate electrode, the spread of the depletion layer is limited. Does not rise sufficiently, causing a phenomenon that charges cannot be read or cannot be read at all. Another problem is that another noise is generated in the output pixel due to the remaining charge or the influence of the processing.

Further, while a conventional CCD image sensor employs an n-type substrate, a MOS image sensor has an extremely high B concentration (for example, 1 to 3 × 10 ¹⁸ cm ⁻³ ), and a B image is formed on the surface side of the substrate. A p / p ⁺ substrate is used in which epitaxial layers having a low concentration (for example, 1 × 10 ¹⁴ cm ⁻³ ) are stacked on the order of 5 to 10 μm. The reason that the conventional CCD image sensor employs an n-type substrate is that, of the carriers generated by the photoelectric conversion, the carriers that are not collected in the PD, particularly, the carriers generated deep in the substrate or leak from the PD due to the incidence of strong light. The reason for this is to make it easy for the substrate side to discard the carrier that has leaked into the adjacent pixels due to diffusion, thereby preventing blooming and color mixing from occurring. However, discarding the carrier generated by the photoelectric conversion naturally lowers the sensitivity.

  In order to solve the problem of the decrease in sensitivity, the CCD image sensor employs a method of applying a higher read voltage (for example, 5 V), expanding a depletion layer, and collecting carriers from a wider range. However, the MOS image sensor is characterized by low voltage driving compared to the CCD image sensor, and the depletion layer of the PD does not spread as compared with the CCD image sensor due to the low voltage driving, so that the sensitivity is improved by this method. Can not hope.

Therefore, the MOS image sensor employs the above-described p / p ⁺ substrate, and collects the generated carriers in the PD without discarding them to the substrate side to improve the sensitivity. FIG. 13 shows an impurity concentration distribution (a) and a potential distribution (b) below the PD of the MOS image sensor. As shown in the figure, by forming a profile in which the B concentration is high on the deep side of the substrate and lower than the B concentration on the surface side of the substrate, even if carriers generated at a depth deeper than the PD portion try to diffuse further deeply, When the B concentration is high, it is rebounded to the front surface side of the substrate. Then, a part of the bounced electrons collects on the light-irradiated PD due to diffusion or the like, so that an improvement in sensitivity can be expected as compared with a normal p-type Si substrate. Further, by increasing the concentration on the substrate side to shorten the carrier lifetime, it is possible to further suppress leakage of carriers generated in a deep portion of the substrate into adjacent pixels.

However, in the impurity profile under the PD of the amplification type solid-state imaging device using the p / p ⁺ substrate, the B concentration is also high on the substrate surface side because a surface shield layer and the like are provided, and the P (phosphorus) concentration of the PD is high. There is a depth where the B concentration becomes minimum at a depth deeper than the depth where the peak exists. That is, in this profile, the electrons generated in the vicinity of the PD once try to flow in a deeper direction of the substrate, but are rebounded at the above-mentioned high B concentration and diffused in the lateral direction of the substrate. This flow of electrons causes color mixing. In any case, the diffusion of the electrons bounced off at the high B concentration may improve the sensitivity and possibly cause color mixing. For this reason, a technical problem of the MOS image sensor is to provide a PD structure that allows carriers to be more efficiently collected in the PD.

  Further, the MOS image sensor has a problem of noise feedback. This is because the PD portion was not depleted even when operated at 3.3 V with the impurity concentration of the conventional PD. For this reason, there has been a problem that KTC noise is generated due to the capacitance C of the PD portion. This noise is represented by the following equation, where Q is the noise charge.

Q ² = kTC

  As described above, conventionally, in the MOS image sensor, noise is generated in the PD section, and there is a problem that image quality is poor.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to eliminate KTC noise caused by the substantial capacitance of a PD portion and improve image quality. It is to provide a device.

  In order to solve the above problems, the present invention employs the following configuration.

That is, one embodiment of the present invention is the photoelectric conversion unit in a solid-state imaging device including an imaging region in which unit cells each including a photoelectric conversion unit and a signal scanning circuit are arranged in a matrix in a two-dimensional matrix over a semiconductor substrate. The impurity concentration Na of the n-type region is set to satisfy 0 <Na−Nb <1 × 10 ¹⁷ cm ⁻³ with respect to the impurity concentration Nb of the p-type region below the photoelectric conversion unit. And

  Here, preferred embodiments of the present invention include the following.

  (1) The n-type region as a photoelectric conversion unit is located within 0.6 μm from the substrate surface.

  (2) The acceleration of the ion species in the implant used for producing the n-type region as the photoelectric conversion unit is 160 keV or less.

  (3) There is a p-type region as a surface shield layer between the n-type region as the photoelectric conversion unit and the substrate surface.

(4) The boron concentration in the p-type region below the photoelectric conversion unit is in the range of 1 × 10 ¹⁷ cm ⁻³ to 2 × 10 ¹⁷ cm ⁻³ .

(5) The boron concentration in the p-type region below the photoelectric conversion portion is in the range of 1 × 10 ¹⁶ cm ⁻³ to 3 × 10 ¹⁶ cm ⁻³ .

(6) The concentration of boron in the p-type region below the photoelectric conversion portion is in the range of 1 × 10 ¹⁵ cm ⁻³ to 3 × 10 ¹⁵ cm ⁻³ .

(7) The boron concentration in the p-type region below the photoelectric conversion portion is in the range of 1 × 10 ¹⁸ cm ⁻³ to 3 × 10 ¹⁸ cm ⁻³ .

  According to the present invention, by setting the relationship between the impurity concentration Na of the n-type region serving as the photoelectric conversion unit and the impurity concentration Nb of the p-type region below the photoelectric conversion unit optimally, it is possible to reduce the substantial capacitance of the PD portion. KTC noise can be eliminated, and the image quality can be improved.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(1st Embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram showing a MOS image sensor according to the first embodiment of the present invention.

  Photodiode 1 for photoelectric conversion (1-1-1, 1-1-2,..., 1-3-3), and readout transistor 2 (2-1-1, 1-2-2, , 2-3-3), amplifying transistor 3 (3-1-1, 3-1-2,..., 3-3-3) for amplifying read signal charges, and vertical selection for selecting a signal read line Transistor 4 (4-1-1, 4-1-2 to 4-3-3), reset transistor 5 for resetting signal charge (5-1-1, 5-1-2, to 5-3-) The unit cells consisting of 3) are two-dimensionally arranged as 3 × 3. Actually, more unit cells are arranged.

  Horizontal address lines 7 (7-1,..., 7-3) wired in the horizontal direction from the vertical shift register 6 are connected to the gates of the vertical selection transistors 4 and determine lines from which signals are read. The reset line 8 (8-1,..., 8-3) is connected to the gate of the reset transistor 5. The source of the amplification transistor 3 is connected to the vertical signal line 9 (9-1,..., 9-3), and the load transistor 10 (10-1,..., 10-3) is provided at one end. The other end of the vertical signal line 9 is connected to a horizontal signal line 13 via a horizontal selection transistor 11 (11-1,..., 11-3) selected by a selection pulse supplied from a horizontal shift register 12. .

  Although the circuit configuration is basically the same as that of the conventional device, the present embodiment is different from the conventional device in the element structure described below.

  FIG. 2 is a sectional view of an element structure for explaining the present embodiment. This figure shows a photoelectric conversion unit and a signal reading unit in one unit cell portion (one pixel).

  As shown in FIG. 2, in the present embodiment, a photodiode (photoelectric conversion unit) PD21 composed of an n-type diffusion layer for converting light into electric charges and storing the charges is provided inside a p-type Si substrate or a p-well 20. A gate electrode 22 is provided via a gate oxide film on the p-substrate or p-well 20 adjacent to one end of the PD 21. The p-substrate or p-well 20 on the opposite side of the gate electrode 22 from the PD 21 is provided. A drain region 23 made of an n-type diffusion layer is provided on the surface.

A buried gate layer 24 is provided on the upper side of the PD 21 on the side of the gate electrode 22 so as to be in contact with the PD 21 on the substrate surface side and partially overlap the gate electrode 22 in the surface direction of the p-substrate or p-well 20. Is provided on the surface layer of the p-substrate or p-well 20 with a surface shield layer 25 made of ap ⁺ -type diffusion layer. The gate electrode 22, the PD 21, the buried gate layer 24, and the drain region 23 constitute a MOS transistor.

  Next, a simple manufacturing process of the above-described MOS image sensor will be described with reference to FIG. First, as shown in FIG. 3A, after a gate oxide film is formed on a p-type Si substrate or a p-well 20 by thermal oxidation, poly-Si is deposited by a CVD method. Subsequently, after forming the resist pattern 31, the gate electrode 22 is formed by processing into a desired shape by RIE.

  Next, as shown in FIG. 3B, after removing the resist pattern 31 to form a resist pattern 32, the n-type diffusion layer (PD) 21 serving as a photoelectric conversion unit is formed on the substrate by using a high-acceleration ion implanter. Form deeply.

  Next, as shown in FIG. 3C, after removing the resist pattern 32 to form a resist pattern 33, the buried gate layer 24 is formed by gate self-alignment. The depth of the buried gate layer 24 is shallower than that of the PD 21 so as to be in contact with the substrate surface side of the PD 21. Next, as shown in FIG. 3D, after removing the resist pattern 33 to form a resist pattern 34, an n-type diffusion layer (drain region) 23 is formed by gate self-alignment. Here, the order of forming the buried gate layer 24 and the drain region 23 may be reversed.

Finally, as shown in FIG. 3E, after removing the resist pattern 34 to form a resist pattern 35, a p ⁺ -type diffusion layer (surface) is formed on the PD 21 side with respect to the gate electrode 22 by low-acceleration ion implantation. A shield layer 25 is formed.

  As described above, according to the present embodiment, the n-type buried gate layer 24 is provided above the gate side of the n-type PD 21 formed at a deep position inside the p-substrate or the p-well 20, thereby eliminating the barrier potential. A path for electric charges can be formed. Therefore, even at a low power supply voltage of 3.3 V or lower used in CMOS, the signal charges stored in the PD 21 can be sufficiently read, and the sensitivity can be improved and the noise can be reduced.

(Second embodiment)
FIG. 4 is a sectional view showing an element structure of a MOS image sensor according to the second embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The basic structure is the same as that of FIG. 2, but in the present embodiment, the PD 21 extends below the gate electrode 22 as shown in FIG. In order to prevent punch-through from the PD 21 with respect to the drain region 23, a punch-through stopper 26 made of ap ⁺ -type diffusion layer is provided below the drain region 23.

  FIG. 5 shows a manufacturing method of the present embodiment. First, as shown in FIG. 5A, after a resist pattern 51 is formed on a p-type Si substrate or a p-well 20, a PD 21 made of an n-type diffusion layer is formed at a deep position in the substrate by high-acceleration ion implantation. I do.

  Next, as shown in FIG. 5B, after removing the resist pattern 51 to form a resist pattern 52, the buried gate layer 24 is formed by ion implantation at a lower acceleration than when the PD portion is formed. The depth of the buried gate layer 24 is shallower than that of the PD 21 so as to be in contact with the substrate surface side of the PD 21.

  Next, as shown in FIG. 5C, after removing the resist pattern 52, a gate oxide film is formed on the p-substrate or the p-well 20 by thermal oxidation, and then poly-Si is deposited thereon by a CVD method. . Subsequently, after forming a resist pattern 53, the gate electrode 22 is formed by processing into a desired shape by RIE.

Next, as shown in FIG. 5D, after removing the resist pattern 53 to form a resist pattern 54, a punch-through stopper 26 made of ap ⁺ -type diffusion layer is formed by gate self-alignment.

Finally, as shown in FIG. 5E, after removing the resist pattern 54 to form a resist pattern 55, the drain region 23 made of an n-type diffusion layer is formed by gate self-alignment by ion implantation. Subsequently, after removing the resist pattern 55 to form a resist pattern (not shown), a p ⁺ -type diffusion layer (surface shield layer) 25 is formed on the PD 21 side with respect to the gate electrode 22 by low-acceleration ion implantation. I do.

Even with such a configuration, by providing the n-type buried gate layer 24 above the gate side of the n-type PD 21, a path for charges without a barrier potential can be formed. The same effects as in the embodiment can be obtained. Further, in the configuration in which the p ⁺ -type surface shield layer 25 is provided above the n-type PD 21, by providing the p ⁺ -type punch-through stopper 26 below the n-type drain region 23, the p-type substrate or the p-well is formed. Even if the impurity concentration of the transistor 20 is sufficiently reduced, the signal charges stored in the PD 21 can be completely read using a low-voltage driven MOS transistor without causing punch-through.

(Third embodiment)
FIG. 6 is a cross-sectional view showing the element structure of the MOS image sensor according to the third embodiment of the present invention, and particularly shows the configuration near the PD section.

In the drawing, reference numeral 60 denotes a region where the B concentration of the p / p ⁺ substrate is high (region deeper than about 5 μm from the substrate surface), 61 denotes an epitaxial layer laminated region (p well) of the p / p ⁺ substrate, and 62 denotes The n-type diffusion layer region of the photodiode PD that performs photoelectric conversion, and 63 indicates a p-type diffusion layer region (surface shield layer) that shields the PD.

FIG. 7A shows an impurity concentration profile (phosphorus, boron) in the depth direction in the PD portion of the same embodiment. The B concentration is high at a deep position of the substrate (about 5 μm) (2 × 10 ¹⁸ cm ⁻³ ), and B diffuses from the deep position of the substrate to the epitaxial layer on the substrate surface to about 5 μm. I have.

On the other hand, a surface shield layer 63 for shielding the surface is provided near the surface of the substrate, and the B concentration is increased again (1 × 10 ¹⁹ cm ⁻³ ). Therefore, there is a portion where the B concentration is minimum in the epitaxial layer portion of the substrate. In addition, P (phosphorus) is ion-implanted for forming the PD 62. The search for the peak of the P concentration is mainly determined by the energy at the time of P ion implantation. The positional relationship between the depth at which the B ion concentration is minimum and the peak concentration depth of the P concentration is such that the search at which the B ion concentration is minimum is located closer to the substrate surface than the peak concentration depth of the P concentration. I have.

  In the positional relationship between the concentration search where the B concentration becomes the minimum and the concentration depth where the P concentration becomes the maximum, the potential profile of the PD portion becomes as shown in FIG. 7B, and the electrons gather on the surface side of the substrate. It becomes such a profile. As a result, the electrons generated by the photoelectric conversion do not temporarily flow to a deep position of the substrate, but are quickly collected by the PD 62. Therefore, it is possible to eliminate inconveniences such as electrons being rebounded in a deep position of the substrate and being diffused in the lateral direction of the substrate, thereby improving sensitivity and reducing color mixing, and further suppressing blooming. Become.

  Next, a method of forming the impurity profile of FIG. 7 will be specifically described. Here, a method for manufacturing a photodiode portion which is a feature of the present invention will be mainly described.

In order to form the MOS image sensor of the present embodiment, a p / p ⁺ substrate is used. At this time, the B concentration at the deep position 60 of the substrate is 2 × 10 ¹⁸ cm ⁻³ . Then, an epitaxial layer 61 is laminated on the surface of the substrate. The epitaxial film thickness is, for example, 5 μm, and the B concentration of the epitaxial layer 61 is 2 × 10 ¹⁵ cm ⁻³ . Usually, in a p / p ⁺ substrate, since the epitaxial layer 61 is laminated at about 1 μm / min, B hardly diffuses from a deep position of the substrate to the substrate surface side (epitaxial layer). Therefore, near the interface between the epitaxial layer 61 and the substrate 60, there is a steep B concentration profile.

For the purpose of diffusing B to the surface of the substrate by using this p / p ⁺ substrate, B in the area of 60 is thermally diffused at about 1190 ° C. for about 3 hours, for example. As a result, a p-well having a B concentration of about 1 × 10 ¹⁷ cm ⁻³ near the surface of the substrate can be formed. Thereby, a B concentration profile in which the B concentration is minimized near the substrate surface can be formed.

Then, using a p / p ⁺ substrate having such a B concentration profile, a gate, a gate wiring, a drain, and the like for forming a transistor and a capacitor are formed by a normal process.

Thereafter, in order to form the n-type layer 62 of the PD of the photoelectric conversion unit, a resist is applied and patterned, and P ions are implanted. At this time, for example, ion implantation of P is performed at 200 KeV and a dose of 1.5 × 10 ¹³ cm ⁻³ . This makes it possible to form a P concentration profile in which the P concentration peak has a depth of about 0.6 μm from the substrate surface.

Next, in order to form a PD having an S3 structure (Surface shield sensor) (the surface level of the PD surface is shielded with B. A p-type layer of the PD is formed on the surface). B ions are implanted at 35 KeV and a dose of 1 × 10 ¹⁴ cm ⁻² to form ap ⁺ -type layer 63 as a surface shield. As a result, an n-type layer 62 of a PD that performs photoelectric conversion can be embedded in the substrate, and a PD having an S3 structure in which the substrate surface is shielded with B can be formed. Thereafter, an Al-type wiring or the like is formed by a usual method to produce an amplification type MOS image sensor.

  By the above method, the impurity concentration profiles of B and P in the depth direction of the PD portion can be made the impurity profiles as shown in FIG.

(Fourth embodiment)
FIG. 8 is a cross-sectional view showing the element structure of the MOS image sensor according to the fourth embodiment of the present invention, and particularly shows the configuration near the PD portion.

8, an n-type diffusion layer 81 of a photodiode (PD) for converting light into electric charges is formed at a predetermined position from the surface of the p-well 80. On the surface of the p-well 80, a surface shield layer 84 formed of a highly doped p ⁺ diffusion layer above the n-type diffusion layer 81 is provided. Drain regions 83 of the transistors are respectively formed. Further, on the surface of the p-well 80, a gate electrode 82 for reading out the charges accumulated in the n-type diffusion layer 81 of the PD to the drain region 83 is provided.

  The manufacturing process of this MOS image sensor is basically the same as that described in the first embodiment. That is, after forming a gate electrode 82 made of a poly-Si film on the surface of the p-well 80, an n-type diffusion layer 81 as a PD is formed at a predetermined depth from the surface of the p-well 80. A surface shield layer 84 is formed above the type diffusion layer 81, and an n-type diffusion layer 83 as a drain region is formed on the side opposite to the n-type diffusion layer 81 with respect to the gate electrode 82. Note that the surface shield layer 84 is not always necessary and can be omitted.

  A plurality of samples were prepared by changing the doping amount of boron (B) as a p-type impurity and the doping amount of phosphorus (P) as an n-type impurity by the above-described configuration and manufacturing method. Here, in the formation of the n-type diffusion layer 81 as a PD, an acceleration of 100 KeV to 1000 KeV due to single phosphorus is used, and in the formation of the p-type diffusion layer 84 as a surface shield layer, the acceleration of boron is 10 KeV. To 300 KeV.

  Of these samples, those that completely depleted the PD portion during operation under low-voltage driving (3.3 V) were selected. 9 to 11 show examples of the concentration distribution in the cross section direction of the PD portion in the selected sample.

In FIG. 9, the B concentration in the portion corresponding to the p well 80 in FIG. 8 is 3.0 × 10 ¹⁷ cm ⁻³ , and the P concentration in the portion corresponding to the PD 81 in FIG. 8 is 4.0 × 10 ¹⁷ cm ^−. is ^3, B concentration in the part corresponding to the surface shield layer 84 in FIG. 8 is 1.0 × 10 ¹⁸ cm ^-3. Here, the PD portion is completely depleted in the region indicated by hatching in FIG. 9 where the P concentration is higher than the B concentration.

In FIG. 10, the B concentration in the portion corresponding to the p well 80 in FIG. 8 is 9.0 × 10 ¹⁶ cm ⁻³ , and the P concentration in the portion corresponding to the PD 81 in FIG. 8 is 1.3 × 10 ¹⁷ cm ^−. is ^3, B concentration in the part corresponding to the surface shield layer 84 in FIG. 8 is 1.0 × 10 ¹⁸ cm ^-3. Here, the PD portion is completely depleted in the region indicated by hatching in FIG. 10 where the P concentration is higher than the B concentration.

In FIG. 11, the B concentration in the portion corresponding to the p well 80 in FIG. 8 is 2.0 × 10 ¹⁵ cm ⁻³ , and the P concentration in the portion corresponding to the PD 81 in FIG. 8 is 1.0 × 10 ¹⁷ m ⁻ is ^3, the concentration of B part corresponding to the surface shield layer 84 in FIG. 8 is 1.0 × 10 ¹⁸ cm ^-3. Here, the PD portion is completely depleted in a region indicated by hatching in FIG. 11 where the P concentration is higher than the B concentration.

FIG. 12 shows a graph including the above results. This is a correlation diagram regarding the concentration in the p-well 80 and the PD 81 in FIG. Although the concentration of the PD 81 at which the effect of completely depleting the PD portion is obtained varies depending on the concentration of the p-well 80, a MOS image sensor with no noise due to the complete depletion of the PD portion is realized in the range indicated by hatching in FIG. . Here, the range of the hatching is such that the concentration Nb of the p-type impurity B of the p-well 80 is 0 <Na−Nb <1 × 10 ¹⁷ cm ^{−3 with} respect to the concentration Na of the p-type impurity n of the PD 81. Is satisfied, and the above effect is obtained in this range.

  As described above, according to the present embodiment, by optimizing the relationship between the P concentration Na in the PD 81 and the B concentration Nb in the p well 80, it is possible to eliminate KTC noise caused by the substantial capacitance of the PD portion. The image quality can be improved. That is, by optimally setting the relationship between the impurity concentration Na in the n-type region, which is the photoelectric conversion unit, and the impurity concentration Nb in the p-type region below the photoelectric conversion unit, the photoelectric conversion unit is completely depleted and the photoelectric conversion unit is depleted. The capacitance C can be made substantially zero, so that noise generated in the photoelectric conversion unit can be eliminated, and image quality can be improved.

  Note that the present invention is not limited to the above embodiments. In the embodiment, the MOS image sensor has been described as an example. However, the present invention can be applied to a CCD image sensor as long as a signal charge is read from a photoelectric conversion unit such as a photodiode by a reading transistor. In the embodiment, the photoelectric conversion unit also serves as the signal storage unit. However, the present invention can be applied to a configuration in which the photoelectric conversion unit and the signal storage unit are separately provided.

  In addition, various modifications can be made without departing from the scope of the present invention.

FIG. 2 is a circuit configuration diagram showing a MOS image sensor according to the first embodiment. FIG. 2 is an element structure cross-sectional view illustrating a configuration of a photoelectric conversion unit and a signal readout unit of one pixel according to the first embodiment. FIG. 4 is a cross-sectional view illustrating a manufacturing process of the MOS image sensor according to the first embodiment. FIG. 7 is a cross-sectional view illustrating the element structure of a MOS image sensor according to a second embodiment. FIG. 13 is a cross-sectional view illustrating a manufacturing process of the MOS image sensor according to the second embodiment. FIG. 13 is a sectional view showing the element structure of a MOS image sensor according to a third embodiment. FIG. 14 is a diagram illustrating an impurity concentration profile and a potential distribution in a depth direction in a PD unit according to a third embodiment. FIG. 13 is a cross-sectional view illustrating the element structure of a MOS image sensor according to a fourth embodiment. FIG. 14 is a diagram illustrating an example of a concentration distribution in a cross-sectional direction of a PD portion in a sample created in a fourth embodiment. FIG. 14 is a diagram illustrating an example of a concentration distribution in a cross-sectional direction of a PD portion in a sample created in a fourth embodiment. FIG. 14 is a diagram illustrating an example of a concentration distribution in a cross-sectional direction of a PD portion in a sample created in a fourth embodiment. FIG. 12 is a diagram showing the results of FIGS. 9 to 11. The figure which shows the impurity concentration distribution and potential distribution under PD of the conventional MOS image sensor.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 ... Photodiode 2 ... Reading transistor 3 ... Amplification transistor 4 ... Vertical selection transistor 5 ... Reset transistor 6 ... Vertical shift register 7 ... Horizontal address line 8 ... Reset line 9 ... Vertical signal line 10 ... Load transistor 11 ... Horizontal selection transistor 12 ... horizontal shift register 13 ... horizontal signal line 20, 80 ... p substrate or p well 21, 81 ... n-type diffusion layer (PD)
22, 82 gate electrode 23, 83 n-type diffusion layer (drain region)
24 ... n-type diffusion layer (buried gate layer)
25, 84 ... p ⁺ type diffusion layer (surface shield layer)
26 ... p ⁺ type diffusion layer (punch through stopper)
31 to 35, 51 to 55: resist pattern 60: p ⁺ type region 61: p type epitaxial layer (p well)
62 ... n-type region (PD)
63 ... p ⁺ type region (surface shield layer)
80: p-well 81: n-type diffusion layer (PD)
82 ... Gate electrode

Claims (5)

In a solid-state imaging device having an imaging region in which unit cells including a photoelectric conversion unit and a signal scanning circuit are arranged in a two-dimensional matrix on a semiconductor substrate,
The impurity concentration Na of the n-type region serving as the photoelectric conversion unit is smaller than the impurity concentration Nb of the p-type region below the photoelectric conversion unit.
0 <Na-Nb <1 × 10 ¹⁷ cm ⁻³
The solid-state imaging device is set so that the following condition is satisfied.   The semiconductor device according to claim 1, wherein the n-type region serving as the photoelectric conversion unit is located at a position within 0.6 μm from a surface of the substrate.   The semiconductor device according to claim 1, further comprising a p-type region between the n-type region serving as the photoelectric conversion unit and a surface of the substrate. 2. The solid-state imaging device according to claim 1, wherein a boron concentration in a p-type region below the photoelectric conversion unit is in a range of 1 × 10 ¹⁷ cm ⁻³ to 2 × 10 ¹⁷ cm ⁻³ . 2. The solid-state imaging device according to claim 1, wherein a boron concentration in a p-type region below the photoelectric conversion unit is in a range of 1 × 10 ¹⁵ cm ⁻³ to 3 × 10 ¹⁵ cm ⁻³ .

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