JP2004253555A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where the number of wiring layers when wiring different in thickness is installed is reduced and a process is simplified, and to provide a manufacturing method of the device. <P>SOLUTION: In a channel wiring part 354, wiring 339A, etc. whose film thickness is larger than wiring 333, etc. of a general circuit 350 are disposed in a common wiring layer. In a pad 357, wiring 339C whose film thickness is larger than wiring 333 of the general circuit 350 is installed in the common wiring layer. In a sealing part 356, a seal ring 339D, etc. whose film thickness is larger than wiring 333, etc. of the general circuit 350 are arranged in the common wiring layer. In memories 351 to 353, wiring 334, etc. whose film thickness is smaller than wiring 333, etc. of the general circuit 350 are arranged in the common wiring layer. In fuse circuits 351a and 352a of a memory, fuses 360 whose film thickness is smaller than wiring 333 of the general circuit 350 are installed in the common wiring layer. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having an embedded wiring structure and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, after a contact hole and a wiring groove are formed in an insulating film, a metal film is buried in the contact hole and the wiring groove to form a contact and a metal wiring at the same time. It is being developed (for example, see Patent Document 1).
[0003]
FIGS. 5A to 5D are cross-sectional views showing a manufacturing process (particularly, a wiring layer) of a conventional semiconductor device using a dual damascene method.
[0004]
First, in a step shown in FIG. 5A, a lower insulating film 502 is deposited on a base portion 501 having a substrate, an element such as a transistor, a memory cell, and the like, and then a lower wiring groove 503 is formed in the lower insulating film 502. To form Next, a lower barrier film 504 and a lower metal film 505 are sequentially deposited in the lower wiring groove 503 and on the lower insulating film 502. For example, a TiN film is deposited as the lower barrier film 504 and a copper film is deposited as the lower metal film 505, respectively. Then, unnecessary portions of the lower metal film 505 and the lower barrier film 504 are polished and removed by a chemical mechanical polishing (CMP) method, so that the lower barrier film 504 and the lower metal film 505 are formed in the lower wiring groove 503. Is formed.
[0005]
Next, in a step shown in FIG. 5B, a protective insulating film 507 for protecting the lower wiring 506 is deposited on the lower insulating film 502 and the lower wiring 506, and then the upper insulating film 507 is formed on the protective insulating film 507. An insulating film 508 is deposited. For example, a silicon nitride film is deposited as the protective insulating film 507, and a silicon oxide film is deposited as the upper insulating film 508. Thereafter, a resist film 509 having an opening 510 for forming a contact is formed on the upper insulating film 508, and then the upper insulating film 508 is etched using the resist film 509 as a mask to form a protective insulating film. A contact hole 511 reaching 507 is formed.
[0006]
Next, in a step shown in FIG. 5C, after removing the resist film 509, a new resist film 512 having an opening for forming an upper wiring groove is formed on the upper insulating film 508. Thereafter, the upper insulating film 508 is etched using the resist film 512 as a mask to form an upper wiring groove 513 having a depth of about 400 nm in the upper insulating film 508.
[0007]
Next, in the step shown in FIG. 5D, after the resist film 512 is removed, etch back is performed on the entire surface of the substrate. At this time, the protective insulating film 507 exposed in the contact hole 511 is etched using the upper insulating film 508 as a hard mask, and the contact hole 511 is penetrated to the lower wiring 506. Thereafter, an upper-layer barrier film 514 and an upper-layer metal film 515 that fill the contact hole 511 and the upper-layer wiring groove 513 and extend over the upper-layer insulating film 508 are sequentially deposited. For example, a TiN film is deposited as the upper barrier film 514, and a copper film is deposited as the upper metal film 515. After that, unnecessary portions of the upper metal film 515 and the upper barrier film 514 on the upper insulating film 508 are polished and removed by a CMP method, and the upper barrier film 514 is formed in the contact holes 511 and the upper wiring grooves 513. Then, upper wirings 516 and 517 are formed leaving a part of the upper metal film 515. As a result of the above process, the upper wirings 516 and 517 formed are upper wirings 516a and 517a actually functioning as wiring, and contacts for electrically connecting the upper wirings 516a and 517a and the lower wiring 506. Parts 516b, 516b.
[0008]
The above process is a method of forming a wiring by a dual damascene method. In the damascene method, there is also a method called a single damascene method. In the single damascene method, a metal film is deposited and CMP on a contact hole, and a wiring groove is formed. Of the metal film and the CMP are separately performed.
[0009]
By using the above damascene method, it is possible to easily form a wiring using a copper film that is difficult to pattern by etching, and to take advantage of the excellent characteristics of the copper film such as low resistance, migration resistance, and high strength. Becomes possible.
[0010]
[Patent Document 1]
JP-A-11-307636 (abstract)
[0011]
[Problems to be solved by the invention]
However, the semiconductor device having the conventional wiring structure as described above has the following disadvantages.
[0012]
In the manufacturing process of the wiring structure using the damascene method, it is premised that a contact hole or a wiring groove having a certain depth is assumed in one wiring layer. In the example shown in FIG. 5), the dimensions such as the thickness of the upper wiring portions 516a and 517a) and the vertical length of the contact portion (the contact portions 516b and 517b in the example shown in FIG. 5D) are formed to be the same. . As described above, when a plurality of wirings having the same thickness are formed in the same wiring layer, it is difficult to simultaneously reduce the wiring resistance and the capacitance between the wirings. That is, despite the fact that among the plurality of wirings, there is a wiring that emphasizes the reduction of the wiring resistance and a wiring that emphasizes the capacitance between the wirings, all the wirings are formed with the same thickness. It is difficult to reduce the wiring resistance while suppressing the increase.
[0013]
One way to solve this problem is to provide two wirings having different wiring thicknesses, place the wiring for which reduction of wiring resistance is important in a wiring layer made of a conductor film having a large film thickness, and attach importance to the capacitance between wirings. There is a method of arranging the wiring to be formed in a wiring layer made of a conductor film having a small thickness. However, in this case, since it is necessary to provide a number of wiring layers according to the type of the required wiring thickness, the number of wiring layers may increase and the number of manufacturing steps may increase.
[0014]
It is an object of the present invention to simplify the process and provide a plurality of wirings having different thicknesses in a common wiring layer according to the type of wiring as a wiring structure of a semiconductor device using a damascene method. The object is to reduce the number of layers.
[0015]
[Means for Solving the Problems]
The semiconductor device of the present invention comprises a base having a substrate and an element, an insulating film provided above the base, and a conductive material embedded in a first groove formed in the insulating film. A wiring, and a member embedded in the second groove formed in the insulating film, formed of a common film with the wiring, and having a thickness different from that of the wiring.
[0016]
As a result, the wires having different thicknesses and members such as wires, which have been conventionally arranged in different wiring layers, can be arranged in the same wiring layer, thereby simplifying the manufacturing process and reducing the number of wiring layers. Can be planned.
[0017]
When a plurality of circuit blocks and a channel wiring unit for connecting the circuit blocks are provided, one of the plurality of circuit blocks is an arithmetic circuit unit having a signal wiring as the wiring. Since the channel wiring section has a channel wiring having a thickness larger than that of the signal wiring as the member, the manufacturing process can be simplified even if a thick channel wiring layer necessary for avoiding heat generation is provided. And the number of wiring layers can be reduced.
[0018]
The channel wiring preferably penetrates the insulating film, a plurality of interlayer insulating films are provided as the insulating film, and the channel wiring penetrates the plurality of interlayer insulating films. Thereby, a wiring structure suitable for the power supply wiring and the ground wiring can be obtained.
[0019]
In the case of having an arithmetic circuit section and an I / O section, the wiring is arranged in the arithmetic circuit section, the member is a wiring arranged in the I / O section, and the I / O section Is thicker than the wiring of the arithmetic circuit section, so that even if the wiring of the thick I / O section necessary for avoiding heat generation is provided, the manufacturing process can be simplified and the wiring layer can be simplified. The number can be reduced.
[0020]
It is preferable that the wiring of the I / O part penetrates the insulating film, and a plurality of interlayer insulating films are provided as the insulating film. By penetrating the insulating film, a wiring structure suitable for power supply wiring and ground wiring can be obtained.
[0021]
In the case of having an arithmetic circuit section and a memory section, the wiring is arranged in the arithmetic circuit section, the member is a signal wiring arranged in the memory section, and the signal wiring of the memory section is It is preferable that the film thickness of the arithmetic circuit portion is smaller than that of the wiring.
[0022]
When the arithmetic circuit section and the pad area for signal connection to the outside are provided, the wiring is arranged in the arithmetic circuit section, and the member is a pad wiring arranged in the pad area. It is preferable that the pad wiring has a larger film thickness than the wiring of the arithmetic circuit section.
[0023]
In the case where there is an arithmetic circuit portion and a seal ring portion surrounding the periphery of the semiconductor device, the wiring is arranged in the arithmetic circuit portion, the member is arranged in the seal ring portion, It is also possible to be a seal ring penetrating the film, in which case, as the insulating film, a plurality of interlayer insulating films are provided, the seal ring of the seal ring portion, the plurality of interlayer insulating films It is preferably penetrating.
[0024]
When an arithmetic circuit unit and a memory unit having a fuse are provided, the wiring is disposed in the arithmetic circuit unit, the member is the fuse, and the fuse is more than the wiring of the arithmetic circuit unit. Preferably, the film thickness is small.
[0025]
More preferably, the insulating film includes a base protection film and an interlayer insulating film provided on the base protection film.
[0026]
According to the first method of manufacturing a semiconductor device of the present invention, a step (a) of forming an insulating film above a base portion on which elements are formed and a step (b) of forming a plurality of contact holes penetrating the insulating film And c) forming a plurality of wiring grooves having at least two types of depths in the insulating film, the connecting grooves being connected to the contact holes, and filling the contact holes and the wiring grooves to form a plurality of wiring grooves on the insulating film. (D) forming a conductive film extending to the side, and removing a portion of the conductive film located above the insulating film to form a plurality of wirings in which the conductive film is embedded in each of the wiring grooves. (E).
[0027]
With this method, it is possible to realize a semiconductor device in which a plurality of wirings having different thicknesses are arranged in one wiring layer while simplifying the process.
[0028]
In the step (c), a first resist film having an opening in a part of the plurality of contact holes and located above at least one contact hole is formed above the insulating film. A sub-step (c1), and a sub-step (c2) of forming a part of the plurality of wiring grooves by etching the insulating film using the first resist film as a mask; After removing the resist film, a second opening having a portion above the insulating film in a portion of the plurality of contact holes and located above the contact hole excluding the at least one contact hole. And (c3) forming the resist film by etching the insulating film using the second resist film as a mask to form a part of the plurality of wiring grooves. Groove line only needs to include at least a sub-step of forming a (c4).
[0029]
In the above step (c), it is preferable to form the wiring grooves in order from the one having the smaller area, and it is preferable to form the wiring grooves in order from the one having the smaller depth. If a deep groove or a large area groove is formed first, it becomes difficult to form a resist with good uniformity when subsequently forming a shallow groove or a small area groove. Therefore, by forming a shallow groove or a groove having a small area first, the applicability of the resist thereafter can be improved.
[0030]
According to a second method of manufacturing a semiconductor device of the present invention, there are provided a step (a) of forming an insulating film above a base portion on which an element is formed, a step (b) of forming a contact hole in the insulating film, (C) forming a wiring groove connected to each of the contact holes and a through groove penetrating the insulating film in the insulating film; and filling the contact hole, the wiring groove and the through groove with the insulating film. A step (d) of forming a conductive film extending upward, and a step (e) of removing the portion of the conductive film located above the insulating film and embedding the conductive film in each of the wiring grooves and the through grooves. ).
[0031]
According to this method, a member such as a wiring or a seal ring that requires a particularly large film thickness can be formed by a simple process.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
1A to 1E are cross-sectional views illustrating a manufacturing process (particularly, a wiring layer manufacturing process) of the semiconductor device of the first embodiment.
[0033]
First, in a step shown in FIG. 1A, a lower insulating film 102 having a thickness of 400 nm is deposited on a base portion 101 having a substrate, an element such as a transistor, a memory cell, and the like. A lower wiring groove 103 having a thickness of 400 nm is formed. The base portion 101 may be provided with an interlayer insulating film and a wiring layer in addition to the semiconductor substrate and the transistor. Next, a lower barrier film 104 and a lower metal film 105 are sequentially formed in the lower wiring groove 103 and on the lower insulating film 102. For example, a 30-nm-thick TiN film is deposited as the lower-layer barrier film 104, and a 700-nm-thick copper film is deposited as the lower-layer metal film 105, respectively. Thereafter, unnecessary portions of the lower metal film 105 and the lower barrier film 104 on the lower insulating film 102 are polished and removed by chemical mechanical polishing (CMP), and the lower barrier film is formed in the lower wiring groove 103. A lower wiring 106 composed of a part of the metal layer 104 and a part of the lower metal film 105 is formed. Note that a contact hole may be formed below the lower wiring groove 103, and in that case, the lower wiring 106 is composed of a wiring portion and a contact portion.
[0034]
Next, in a step shown in FIG. 1B, after a protective insulating film 107 for protecting the lower wiring 106 is deposited on the lower insulating film 102 and the lower wiring 106, an upper insulating film 107 is formed on the protective insulating film 107. An insulating film 108 is deposited. For example, a 100-nm-thick silicon nitride film is deposited as a protective insulating film, and a 700-nm-thick silicon oxide film is deposited as an upper-layer insulating film. Then, after forming a resist film 150 (first resist film) having openings 151 and 152 for contact formation on the upper insulating film 108, the resist film 150 is used as a mask to form a resist film 150 on the upper insulating film 108. Then, contact holes 111 and 112 reaching protective insulating film 107 are formed.
[0035]
Next, in the step shown in FIG. 1C, after the resist film 150 is removed, an opening 154 for forming a first upper wiring groove is formed in one contact hole 111 and on the upper insulating film 108. A new resist film 153 (second resist film) is formed. Thereafter, the upper insulating film 108 is etched using the resist film 153 as a mask to form a first upper wiring groove 113 having a depth of about 100 nm in the upper insulating film 108.
[0036]
Next, in the step shown in FIG. 1D, after the resist film 153 is removed, an opening 156 for forming a second upper wiring groove is formed in the other contact hole 112 and on the upper insulating film 108. A resist film 155 is formed. Thereafter, the upper insulating film 108 is etched using the resist film 155 as a mask to form a second upper wiring groove 114 having a depth of about 400 nm in the upper insulating film 108.
[0037]
In this embodiment, the case where a plurality of wiring grooves having two types of depths are formed has been described. However, when there are three or more types, the formation of the resist film and the formation of the wiring grooves are repeated by the number of types. Just do it.
[0038]
Next, in the step shown in FIG. 1E, after removing the resist film 155, etch back is performed on the entire surface of the substrate. At this time, the portion of the protective insulating film 107 exposed in the contact holes 111 and 112 is etched using the upper insulating film 108 as a hard mask, and the contact holes 111 and 112 are penetrated to the lower wiring 106. Thereafter, an upper-layer barrier film 116 and an upper-layer metal film 117 that fill the contact holes 111 and 112, the first and second upper-layer wiring grooves 113 and 114, and extend over the upper-layer insulating film 108 are sequentially deposited. For example, a 30-nm-thick TiN film is deposited as the upper-layer barrier film 116, and a 700-nm-thick copper film is deposited as the upper-layer metal film 117, respectively. After that, unnecessary portions of the upper metal film 117 and the upper barrier film 116 on the upper insulating film 108 are removed by a planarization process by the CMP method, and the contact holes 111 and 112 and the first and second upper layers are removed. An upper barrier film 116 and an upper metal film 117 are integrally buried in the wiring grooves 113 and 114 to form first and second upper wirings 118 and 119, respectively.
[0039]
In order to remove unnecessary portions of the upper metal film 117 and the upper barrier film 116 on the upper insulating film 108, an etch-back method other than CMP can be used.
[0040]
As a result of the above steps, the first upper wiring 118 has a wiring part 118a that actually functions as a wiring, and a contact part 118b for electrically connecting the wiring part 118a and the lower wiring 106. . The second upper wiring 119 has a wiring portion 119a that actually functions as a wiring, and a contact portion 119b for electrically connecting the wiring portion 119a and the lower wiring 106.
[0041]
The thickness of the wiring portion 118a of the first upper wiring 118 is about 100 nm, and the thickness of the wiring portion 119a of the second upper wiring 119 is about 400 nm.
[0042]
As described above, the thicknesses of the wiring portions 118a and 119a of the first and second upper wirings 118 and 119 are different from each other, though they belong to the common wiring layer. By providing the wiring portions 118a and 119a having different thicknesses on a common wiring layer (in the present embodiment, the upper wiring layer), compared to forming wiring layers having different wiring thicknesses individually, While simplifying the damascene process and reducing the number of wiring layers, required thicknesses can be secured according to the type of each wiring arranged in one wiring layer.
[0043]
(Second embodiment)
FIGS. 2A to 2D are cross-sectional views illustrating a manufacturing process (particularly, a wiring layer manufacturing process) of the semiconductor device of the second embodiment.
[0044]
First, in a step shown in FIG. 2A, a lower insulating film 202 having a thickness of 400 nm is deposited on a base portion 201 having a substrate, an element such as a transistor, a memory cell, and the like. A lower wiring groove 203 having a thickness of 400 nm is formed. The base portion 201 may be provided with an interlayer insulating film and a wiring layer in addition to the semiconductor substrate and the transistor. Next, a lower barrier film 204 and a lower metal film 205 are sequentially formed in the lower wiring groove 203 and on the lower insulating film 202. For example, a 30-nm-thick TiN film is deposited as the lower-layer barrier film 204, and a 700-nm-thick copper film is deposited as the lower-layer metal film 205, respectively. Thereafter, unnecessary portions of the lower metal film 205 and the lower barrier film 204 on the lower insulating film 202 are polished and removed by a chemical mechanical polishing (CMP) method, so that the lower barrier film is formed in the lower wiring groove 203. A lower wiring 206 including a part of the metal layer 204 and a part of the lower metal film 205 is formed. Note that a contact hole may be formed below the lower wiring groove 203, and in that case, the lower wiring 206 is constituted by a wiring portion and a contact portion.
[0045]
Next, in a step shown in FIG. 2B, after a protective insulating film 207 for protecting the lower wiring 206 is deposited on the lower insulating film 202 and the lower wiring 206, the upper insulating film 207 is formed on the protective insulating film 207. An insulating film 208 is deposited. For example, a 100-nm-thick silicon nitride film is deposited as a protective insulating film, and a 700-nm-thick silicon oxide film is deposited as an upper-layer insulating film. Thereafter, a resist film 250 having an opening 251 for forming a contact and an opening 252 for forming a second upper wiring groove is formed on the upper insulating film 208, and the upper layer is formed using the resist film 250 as a mask. By etching the insulating film for use 208, a contact hole 211 reaching the protective insulating film 207 and a second upper wiring groove 212 having a depth of about 700 nm are formed.
[0046]
Next, in the step shown in FIG. 2C, after the resist film 250 is removed, a new opening 254 for forming a first upper wiring groove is formed in the contact hole 211 and on the upper insulating film 208. A resist film 253 is formed. Thereafter, the upper insulating film 208 is etched using the resist film 253 as a mask to form a first upper wiring groove 213 having a depth of about 400 nm in the upper insulating film 208.
[0047]
Next, in the step shown in FIG. 2D, after the resist film 253 is removed, etch back is performed on the entire surface of the substrate. At this time, the portion of the protective insulating film 207 exposed in the contact hole 211 and the second upper wiring groove 212 is etched using the upper insulating film 208 as a hard mask to form the contact hole 211 and the second upper layer. The wiring groove 212 is penetrated to the lower layer wiring 206. Thereafter, an upper barrier film 216 and an upper metal film 217 are sequentially formed in the contact hole 211, the second upper wiring groove 212, the first upper wiring groove 213, and on the upper insulating film 208. For example, a 30-nm-thick TiN film is formed as the upper-layer barrier film 216, and a 700-nm-thick copper film is formed as the upper-layer metal film 217. Thereafter, unnecessary portions of the upper layer metal film and the upper layer barrier film on the upper layer insulating film 208 are removed by a CMP method, so that the contact holes 211 and the first and second upper layer wiring grooves 213 and 212 are removed. The upper layer barrier film 216 and the upper layer metal film 217 are integrally embedded to form first and second upper layer wirings 218 and 219, respectively.
[0048]
Note that an etch-back method other than CMP can be used to remove an unnecessary portion of the upper-layer metal film 217 and the upper-layer barrier film 216 on the upper-layer insulating film 208.
[0049]
As a result of the above steps, the first upper layer wiring 218 has an upper layer wiring section 218a actually functioning as a wiring, and a contact section 218b (plug) for electrically connecting the upper layer wiring section 218a and the lower layer wiring 206. have. On the other hand, the second upper wiring 219 does not have a portion serving as a plug, and the whole functions as a wiring portion having an extremely large thickness.
[0050]
As described above, the thickness of the wiring portion 218a of the first upper wiring 218 and the thickness of the second upper wiring 219 are different from each other, though they belong to the common wiring layer. By providing the wiring portion 218a and the second upper wiring 219 having different thicknesses on a common wiring layer (the upper wiring layer in the present embodiment), the wiring layers having different wiring thicknesses are individually formed. As compared with the case of forming, the required thickness can be secured according to the type of each wiring arranged in one wiring layer, while simplifying the process and reducing the number of wiring layers.
[0051]
In particular, the process of forming the first upper wiring layer 218 is basically a dual damascene process, but the process of forming the second upper wiring layer 219 can be considered as a part of the single damascene process. It is.
[0052]
The second wiring layer 219 penetrating through the interlayer insulating film and the protective insulating film in this embodiment can be used for a wiring through which a large current flows, such as a power supply wiring (including a ground wiring), a channel wiring, and a ceiling.
[0053]
(Third embodiment)
FIGS. 3A and 3B are enlarged plan views sequentially showing the position of the semiconductor device and the fuse circuit therein according to the third embodiment. In the present embodiment, an example of a wiring structure of a semiconductor device formed using the manufacturing methods of the first and second embodiments will be described.
[0054]
As shown in FIG. 3A, a semiconductor chip 300, which is a semiconductor device of the present embodiment, includes a general circuit section 350 (arithmetic circuit section) for performing various operations and controls as a circuit block, and an SRAM 351 as a memory section. , A ROM 352 and a DRAM 353, and an I / O unit 355 provided near the outer periphery of the chip. Further, a channel wiring section 354 that connects the circuit blocks 350, 351, 352, 353, and 355 is provided. A seal ring portion 356 is provided at the outermost periphery of the semiconductor chip 300 to prevent moisture and moisture from entering transistors and the like in the semiconductor chip 300. Is provided with a pad region 357 for signal connection with the outside.
[0055]
Further, the SRAM 351 and the DRAM 353 each include a redundant circuit (not shown) for relieving a defective memory, and a fuse circuit 351a for switching the connection of the signal line between the memory cell and the redundant memory of the redundant circuit. , 353a are provided. As shown in FIG. 3B, the fuse circuits 351a and 353a include a fuse 360 provided in the uppermost wiring layer.
[0056]
4A and 4B are partial cross-sectional views showing a part of the structure taken along line IVa-IVa and line IVb-IVb shown in FIG. 3A, respectively.
[0057]
As shown in FIGS. 4A and 4B, a first interlayer insulating film 302 made of a silicon oxide film having a thickness of 400 nm is formed on a base 301 having a substrate, elements such as transistors, memory cells, and the like. A first protective insulating film 303 made of a silicon nitride film having a thickness of 100 nm, a second interlayer insulating film 304 made of a silicon oxide film having a thickness of 700 nm, and a second protective insulating film 305 made of a silicon nitride film having a thickness of 100 nm And a third interlayer insulating film 306 made of a silicon oxide film having a thickness of 700 nm, and a passivation film 307 made of a silicon nitride film having a thickness of 200 nm.
[0058]
Then, a first wiring layer 310 formed by embedding a first barrier film 311 and a first metal film 312 made of a TiN film in the first interlayer insulating film 302 is formed, and the second interlayer insulating film 302 or the second interlayer insulating film is formed. A second wiring layer 320 is formed by embedding a second barrier film 321 and a second metal film 322 made of a TiN film in the film 302 and the first protective insulating film 303, and the third interlayer insulating film 306 or the third interlayer In the insulating film 306 and the second protective insulating film 305, a third wiring layer 330 formed by embedding a third barrier film 331 made of a TiN film and a third metal film 332 is formed.
[0059]
Here, as shown in FIG. 4A, in the general circuit portion 350, as a part of the first wiring layer 310, a first barrier film 311 and a first barrier film 311 are formed in a wiring groove penetrating the first interlayer insulating film 302. An interconnect 313 having a thickness t0 (400 nm in the present embodiment) formed by embedding each part of the metal film 312 is provided. In addition, wirings 323 and 324 are provided as a part of the second wiring layer 320. The wiring 323 is formed by embedding a part of each of the second barrier film 321 and the second metal film 322 in a wiring groove formed in the second interlayer insulating film 304, and has a thickness t1 (400 nm in the present embodiment). It has a portion 323a (functioning as a signal wiring) and a contact portion formed in a cross section (not shown). The wiring 324 is a wiring portion 324a (functioning as a signal wiring) having a thickness t1 in which each part of the second barrier film 321 and the second metal film 322 is embedded in a wiring groove formed in the second interlayer insulating film 304. And a contact portion 324b in which a part of each of the second barrier film 321 and the second metal film 322 is embedded in a contact hole penetrating the second interlayer insulating film 304 and the first protective insulating film 303. Further, a wiring 333 is provided as a part of the third wiring layer 330. The wiring 333 is a wiring portion 333a having a thickness t2 (400 nm in the present embodiment) formed by embedding each part of the third barrier film 331 and the third metal film 332 in a wiring groove formed in the third interlayer insulating film 306. (Function as a signal wiring); and a contact portion 333b in which each part of the third barrier film 331 and the third metal film 332 is embedded in a contact hole penetrating the third interlayer insulating film 306 and the second protective insulating film 305. have.
[0060]
In the channel wiring part 354 and the I / O part 355, each part of the first barrier film 311 and the first metal film 312 is formed in a wiring groove penetrating the first interlayer insulating film 302 as a part of the first wiring layer 310. Is provided. Further, as a part of the second wiring layer 320, each part of the second barrier film 321 and the second metal film 322 is embedded in a wiring groove penetrating the second interlayer insulating film 304 and the first protective insulating film 303. A wiring 329A having a thickness t3 (800 nm in the present embodiment) is provided. Further, as part of the third wiring layer 330, wirings 339A and 339B each having a thickness t4 (800 nm in the present embodiment) are provided. Each of the wirings 339A and 339B is formed by burying a part of each of the third barrier film 331 and the third metal film 332 in a wiring groove penetrating the third interlayer insulating film 306 and the second protective insulating film 305. .
[0061]
In the present embodiment, the wiring 339A is used as a signal wiring for transmitting a logic signal, and the entirety of the wirings 314, 329A, and 339B are integrally used as a ground wiring or a power supply wiring.
[0062]
In the pad region 357, as a part of the third wiring layer 330, each part of the third barrier film 331 and the third metal film 332 is formed in a wiring groove penetrating the third interlayer insulating film 306 and the second protective insulating film 305. Are embedded in the wiring 339C having a thickness t4. Although not shown in the cross section shown in FIG. 4A, the wiring 339C is connected to each wiring of the first and second wiring layers 310 and 320, and is connected to an element and a memory cell on the base 301. ing. An opening of the passivation film 307 is formed on the pad 361 of the wiring 339C, and a pad electrode 343 is provided in the opening and on the passivation film 307. The pad electrode 343 is composed of a part of a fourth barrier film 341 made of a 100 nm-thick TiN film and a part of a fourth metal film 342 made of an 800 nm-thick aluminum film or an aluminum alloy film. Then, a connection member such as a bonding wire or a bump is connected to the pad electrode 343 in the pad region 357 during the mounting process of the semiconductor device.
[0063]
In the seal ring portion 356, as a part of the first wiring layer 310, a first groove formed by burying each part of the first barrier film 311 and the first metal film 312 in a wiring groove penetrating the first interlayer insulating film 302. A seal ring 315 is provided. Further, as a part of the second wiring layer 320, each part of the second barrier film 321 and the second metal film 322 is embedded in a wiring groove penetrating the second interlayer insulating film 304 and the first protective insulating film 303. A second seal ring 329B having a thickness t3 (800 nm in the present embodiment) is provided. Further, as a part of the third wiring layer 330, each part of the third barrier film 331 and the third metal film 332 is embedded in a wiring groove penetrating the third interlayer insulating film 306 and the second protective insulating film 305. , A third seal ring 339D having a thickness t4 (800 nm in the present embodiment).
[0064]
Further, as shown in FIG. 4B, in the SRAM 351 (or the ROM 352 and the DRAM 353), as a part of the first wiring layer 310, a first barrier film 311 is formed in a wiring groove formed in the first interlayer insulating film 302. In addition, a wiring 316 (functioning as a signal wiring) having a thickness t5 (400 nm in this embodiment) formed by burying each part of the first metal film 312 is provided. In addition, wirings 325 and 326 are provided as part of the second wiring layer 320. The wiring 325 is formed by burying each part of the second barrier film 321 and the second metal film 322 in a wiring groove formed in the second interlayer insulating film 304, and has a thickness t6 (100 nm in this embodiment). It has a portion 325a (functioning as a signal wiring) and a contact portion formed in a cross section not shown. The wiring 326 is a wiring portion 326a (functioning as a signal wiring) having a thickness t6 in which each part of the second barrier film 321 and the second metal film 322 is embedded in a wiring groove formed in the second interlayer insulating film 304. And a contact portion 326b in which each part of the second barrier film 321 and the second metal film 322 is buried in a contact hole penetrating the second interlayer insulating film 304 and the first protective insulating film 303. Further, a wiring 334 is provided as a part of the third wiring layer 330. The wiring 334 is a wiring portion 334a having a thickness t7 (100 nm in the present embodiment) in which each part of the third barrier film 331 and the third metal film 332 is embedded in a wiring groove formed in the third interlayer insulating film 306. (Function as a signal wiring), and a contact portion 334b in which a part of each of the third barrier film 331 and the third metal film 332 is embedded in a contact hole penetrating the third interlayer insulating film 306 and the second protective insulating film 305. And
[0065]
In the fuse circuit 351a (and 352a), as a part of the first wiring layer 310, each part of the first barrier film 311 and the first metal film 312 is buried in a wiring groove penetrating the first interlayer insulating film 302. Two wirings 317 having a thickness t0 are provided. Further, two wirings 327 are provided as a part of the second wiring layer 320. The wiring 327 is a wiring portion 327b having a thickness t8 (400 nm in the present embodiment) in which each part of the second barrier film 321 and the second metal film 322 is embedded in a wiring groove formed in the second interlayer insulating film 304. (Functions as a signal wiring) and a contact portion 327b in which each part of the second barrier film 321 and the second metal film 322 is embedded in a contact hole penetrating the second interlayer insulating film 304 and the first protective insulating film 303. And Further, a fuse wiring 335 is provided as a part of the third wiring layer 330. The fuse wiring 335 has a thickness t9 (100 nm in this embodiment) formed by embedding a part of each of the third barrier film 331 and the third metal film 332 in a wiring groove formed in the third interlayer insulating film 306. 335a and a contact portion 335b in which each part of the third barrier film 331 and the third metal film 332 is embedded in a contact hole penetrating the third interlayer insulating film 306 and the second protective insulating film 305. . Then, the central part of the fuse part 335a functions as the fuse 360.
[0066]
The structure of the semiconductor device of the present embodiment as described above can be easily realized by using the manufacturing steps of the first and second embodiments. Wirings 313, 323, 333 of the general circuit section 350, wirings 316, 325, 326, 334, 317, 327, 335 of the memory section (SRAM 351, ROM 352, DRAM 353), wirings 327 of the fuse circuits 351a, 353a, and fuse wiring 335 Can be realized easily and without increasing the number of wiring layers by using the manufacturing process of the first embodiment. That is, the first and second wiring grooves having different depths are provided in the interlayer insulating film, and the conductor films (in the above embodiments, the TiN film and the copper film) are embedded in the respective wiring grooves, so that the thicknesses are different. Wiring can be formed in a common wiring layer.
[0067]
Also, the wires 313, 323, 333 of the general circuit portion 350, the channel wires 354, the I / O circuit portion 355, the wires 314, 329A, 339A, 339B, 339C of the pad area 357, and the seal rings of the seal ring portion 356 315, 329B, and 339D can be realized easily and without increasing the number of wiring layers by using the manufacturing process of the second embodiment. That is, while a wiring groove with a bottom is formed in the interlayer insulating film (or the interlayer insulating film and the protective insulating film), a through groove penetrating the interlayer insulating film and the protective insulating film is formed, and then the wiring groove and the through groove are formed. By embedding a conductive film (TiN film and copper film in each of the above embodiments) in the above, wirings having different thicknesses can be formed on a common wiring layer.
[0068]
According to the semiconductor device of the present embodiment, the following effects can be exhibited by the wiring structure of each circuit block.
[0069]
In the present embodiment, in the channel wiring section 354 that connects the circuit blocks, the second wiring layer 320 and the third wiring layer 330 are provided with wirings 329A, 339A, and 339B that all function as channel wiring. The thickness t3 of the wiring 329A is equal to the total thickness of the second interlayer insulating film 304 and the first protective insulating film 303, and the thickness t1 of the wiring portions 323a and 324a of the wirings 323 and 324 of the general circuit portion 350. Significantly larger than. Therefore, problems such as heat generation in the channel wiring connecting the circuit blocks can be avoided. Similarly, the thickness t4 of the wires 339A and 339B is equal to the total thickness of the third interlayer insulating film 306 and the second protective insulating film 305, and is much larger than the thickness t2 of the wiring portion 333a of the general circuit portion 350. Since it is large, it is possible to avoid problems such as heat generation in channel wiring connecting circuit blocks. In the prior art, such a wiring having a thickness larger than that of the signal wiring of the general circuit section had to be provided in a different wiring layer from the signal wiring of the general circuit section. According to the structure, the channel wiring can be arranged in a common wiring layer with the signal wiring of the general circuit while utilizing the damascene method, so that the process can be simplified and the number of wiring layers can be reduced.
[0070]
Like the wirings 329A, 339A, and 339B of the channel wiring part 354 and the I / O part 355 of the present embodiment, the wiring structure penetrating the interlayer insulating film and the protective insulating film basically uses a dual damascene process. These parts can be substantially realized using a single damascene process.
[0071]
Similarly, in the I / O unit 355, the thickness of each of the wirings 329A, 339A, and 339B is larger than the thickness of each of the wiring parts 323a, 324a, and 333 of the wirings 323, 324, and 333 of the general circuit unit 350, respectively. Therefore, it is possible to avoid problems such as heat generation in the I / O section connecting the circuit blocks. Then, with the structure of the semiconductor device of the present embodiment, it is possible to arrange the thick-film wiring of the I / O portion in the common wiring layer with the thin-film wiring while utilizing the damascene method.
[0072]
In particular, as shown in FIG. 2A of the present embodiment, three channel interconnect portions 354 and I / O portions 355 are formed so as to penetrate from the first interlayer insulating film 302 to the third interlayer insulating film 304. Since the wirings 314, 329A, and 339B are provided so as to overlap with each other, it is easy to avoid a problem such as heat generation between the large-integrated circuit blocks, and a significant effect can be obtained.
[0073]
Note that the portion of the channel wiring portion 354 or the I / O portion 355 that functions as the wiring of the wirings 329A, 339A, and 339B does not necessarily need to penetrate the interlayer insulating film and the protective insulating film, and the portion that functions as a wiring (general) The circuit portion 350 may include a portion corresponding to the wiring portions 323a and 333a) and a portion functioning as a contact portion (a portion corresponding to the contact portions 323b and 333b of the general circuit portion 350). For example, a portion functioning as a wiring of the wiring 329A, 339A, 339B of the channel wiring portion 354 or the I / O portion 355 penetrates only the interlayer insulating film, and a contact portion penetrating the protective insulating film is separately provided. Is also good. However, like the channel wiring portion 354 and the wiring 329A, 339A, and 339B of the I / O portion 355 of the present embodiment, the wiring structure penetrates the interlayer insulating film and the protective insulating film, and particularly, such as ground wiring and power supply wiring. There is an advantage that a wiring through which a large current flows can be formed simultaneously with each wiring such as a general circuit using a damascene process.
[0074]
In the pad region 357, the pad wiring 339C can be provided in the wiring layer 330 common to the wiring 333 of the general circuit portion 350. Considering that the pad portion 361 of the pad wiring 339C is a portion to which a large pressure is applied when performing a mounting process for signal connection with the outside, and a portion to which signals from a large number of elements flow in a concentrated manner. Then, since it is required to be thicker than the wiring 333 of the general circuit section 350, in the structure of the conventional semiconductor device, a wiring layer dedicated to pad wiring is provided separately from the wiring of the general circuit section. On the other hand, in the present embodiment, since the pad wiring 339C can be provided in the same wiring layer 330 as the wiring 333 that is a normal signal line of the general circuit section 350, the process is simplified and the number of wiring layers is reduced. be able to.
[0075]
In the seal ring portion 356, the seal rings 315 and 329B which surround the periphery of the semiconductor device and reach the uppermost passivation film 307 from the base portion 301 in order to prevent moisture, moisture, impurities and the like from entering the semiconductor device. , 339D can be formed simultaneously with the wiring of each wiring layer of the general circuit section 350. Therefore, the structure is such that the process can be simplified.
[0076]
In the memory portion (SRAM 351, ROM 352, and DRAM 353), wiring such as a bit line connecting highly integrated memory cells is required to be as thin as possible for the purpose of reducing the capacitance between wirings. . Therefore, the thicknesses t5, t6, and t7 of the wirings 316, 325, 326, and 334 arranged in the memory unit of the semiconductor device of the present embodiment are all the wirings 313 and 324 in the same wiring layer in the general circuit unit 350. , 333 are formed thinner than the thicknesses t0, t1, and t2, respectively. By arranging such wirings having different thicknesses on a common wiring layer, the number of wiring layers can be reduced and the process can be simplified.
[0077]
In the fuse circuits 351a and 353a, the wiring portion 335a of the fuse wiring 335 is required to be thinner than the signal wiring of the general circuit in order to smoothly cut the fuse using laser light. According to the structure of the semiconductor device of the present embodiment, the fuse wiring 335 having the fuse part 335a with a small thickness t9 can be provided in the wiring layer 330 common to the wiring 333 of the general circuit part 350. Particularly, since the material of the fuse wiring 335 is the same as the wiring 333 of the general circuit section 350 (in this embodiment, a TiN film and a copper film), both can be formed simultaneously by the damascene method, and the process can be simplified. And the number of wiring layers can be reduced.
[0078]
In each of the above embodiments, the semiconductor device having three wiring layers has been described. However, the semiconductor device of the present invention is not limited to such an embodiment, but has four or more wiring layers. However, the same effect can be exerted by forming a plurality of wirings having different thicknesses in at least one of the wiring layers by the damascene method.
[0079]
In each of the above embodiments, the formation of the wiring structure using the dual damascene method has been described. However, the wiring structure of the present invention can also be realized by using the single damascene method. In that case, for example, when forming a plug portion penetrating the first insulating film, a lower layer wiring is formed instead of the plug in a part of the region, and an upper layer wiring connected to the plug is formed above the lower wiring. In this case, an upper layer wiring connected to the lower layer wiring may be formed.
[0080]
【The invention's effect】
According to the semiconductor device or the method for manufacturing a semiconductor device of the present invention, by forming wirings having different thicknesses on a common wiring layer, the process can be simplified and the number of wiring layers can be reduced.
[Brief description of the drawings]
FIGS. 1A to 1E are cross-sectional views illustrating manufacturing steps of a semiconductor device according to a first embodiment.
FIGS. 2A to 2D are cross-sectional views illustrating manufacturing steps of a semiconductor device according to a second embodiment.
FIGS. 3A and 3B are plan views showing, in an enlarged scale, a position diagram of a semiconductor device according to a third embodiment and a fuse circuit therein, respectively.
FIGS. 4A and 4B are partial cross-sectional views showing a part of the structure taken along line IVa-IVa and line IVb-IVb shown in FIG. 3A, respectively.
FIGS. 5A to 5D are cross-sectional views showing a conventional semiconductor device manufacturing process using a dual damascene method.
[Explanation of symbols]
101 Base
102 Insulating film for lower layer
103 Lower wiring groove
104 Barrier film for lower layer
105 Metal film for lower layer
106 Lower layer wiring
107 protective insulating film
108 Insulating film for upper layer
111, 112 Contact hole
113 First upper wiring groove
114 Second upper wiring groove
115 Upper layer wiring groove
116 Upper barrier film
117 Upper layer metal film
118 First Upper Layer Wiring
118a Wiring section
118b Contact part
119 Second Upper Layer Wiring
119a Wiring section
119b Contact part
150 resist film
151, 152 opening
153 resist film
154 opening
155 resist film
156 opening
201 Base
202 Insulating film for lower layer
203 Lower wiring groove
204 Lower layer barrier film
205 Metal film for lower layer
206 Lower layer wiring
207 protective insulating film
208 Insulating film for upper layer
211 Contact hole
212 second upper wiring groove
213 First Upper Layer Wiring Groove
216 Upper layer barrier film
217 Metal film for upper layer
218 First Upper Layer Wiring
218a Wiring section
218b Contact part
219 Second Upper Layer Wiring
250 resist film
251, 252 opening
253 resist film
254 opening
255 resist film
256 opening
301 Base
302 First interlayer insulating film
303 first protective insulating film
304 second interlayer insulating film
305 Second protective insulating film
306 Third interlayer insulating film
307 Passivation film
310 first wiring layer
311 First barrier film
312 Second metal film
313,314,316,317 Wiring
315 First seal ring
320 second wiring layer
321 Second barrier film
322 second metal film
323 wiring
323a Wiring section
324 wiring
324a Wiring section
324b contact part
325 wiring
325a Wiring section
326 wiring
326a Wiring section
326b contact part
327 Wiring
327a Wiring section
327b Contact part
329A Wiring
329B Second seal ring
330 Third Wiring Layer
331 Third barrier film
332 third metal film
333 wiring
333a Wiring section
333b Contact part
334 wiring
334a Wiring section
334b Contact part
335 fuse wiring
335a Wiring section
335b Contact part
339A-339C Wiring
339D Third seal ring
341 4th barrier film
342 4th metal film
343 pad electrode
350 General circuit section (arithmetic circuit section)
351 SRAM
351a fuse circuit
352 ROM
353 DRAM
353a fuse circuit
354 channel wiring section
355 I / O section
356 Seal ring part
357 pad area
360 fuse
361 pad part

Claims (18)

A base portion having a substrate and an element,
An insulating film provided above the base portion;
A wiring made of a conductive material embedded in the first groove formed in the insulating film;
A semiconductor device buried in a second groove formed in the insulating film, formed of a common film with the wiring, and having a thickness different from that of the wiring. The semiconductor device according to claim 1,
A plurality of circuit blocks, and a channel wiring unit connecting the circuit blocks to each other,
One of the plurality of circuit blocks is an arithmetic circuit unit having a signal wiring as the wiring,
The semiconductor device, wherein the channel wiring portion has a channel wiring having a thickness larger than that of the signal wiring as the member. The semiconductor device according to claim 2,
The semiconductor device, wherein the channel wiring penetrates the insulating film. The semiconductor device according to claim 2,
A plurality of interlayer insulating films are provided as the insulating film,
The semiconductor device, wherein the channel wiring penetrates the plurality of interlayer insulating films. The semiconductor device according to claim 1,
An arithmetic circuit unit and an I / O unit;
The wiring is arranged in the arithmetic circuit section,
The member is a wiring arranged in the I / O unit,
A semiconductor device, wherein the wiring of the I / O section has a larger film thickness than the wiring of the arithmetic circuit section. The semiconductor device according to claim 5,
A semiconductor device, wherein the wiring of the I / O part penetrates the insulating film. The semiconductor device according to claim 5,
A plurality of interlayer insulating films are provided as the insulating film,
A semiconductor device, wherein the wiring of the I / O part penetrates the plurality of interlayer insulating films. The semiconductor device according to claim 1,
An arithmetic circuit unit and a memory unit,
The wiring is arranged in the arithmetic circuit section,
The member is a signal wiring arranged in the memory unit,
A semiconductor device, wherein the signal wiring of the memory unit has a smaller thickness than the wiring of the arithmetic circuit unit. The semiconductor device according to claim 1,
An arithmetic circuit section and a pad area for signal connection to the outside,
The wiring is arranged in the arithmetic circuit section,
The member is a pad wiring arranged in the pad region,
The semiconductor device according to claim 1, wherein the pad wiring has a larger thickness than a wiring of the arithmetic circuit unit. The semiconductor device according to claim 1,
An arithmetic circuit unit, and a seal ring unit surrounding the periphery of the semiconductor device;
The wiring is arranged in the arithmetic circuit section,
The semiconductor device, wherein the member is a seal ring disposed on the seal ring portion and penetrating the insulating film. The semiconductor device according to claim 10,
A plurality of interlayer insulating films are provided as the insulating film,
A semiconductor device, wherein a seal ring of the seal ring portion penetrates the plurality of interlayer insulating films. The semiconductor device according to claim 1,
An arithmetic circuit unit and a memory unit having a fuse,
The wiring is arranged in the arithmetic circuit section,
The member is the fuse,
The semiconductor device, wherein the fuse has a smaller thickness than a wiring of the arithmetic circuit unit. The semiconductor device according to any one of claims 1 to 12,
A semiconductor device comprising: a base protection film; and an interlayer insulating film provided on the base protection film, as the insulating film. (A) forming an insulating film above a base portion on which the element is formed;
(B) forming a plurality of contact holes penetrating the insulating film;
(C) forming, in the insulating film, a plurality of wiring grooves connected to the contact holes and having at least two types of depths;
(D) forming a conductor film extending over the insulating film by filling the contact holes and the wiring trenches;
Removing a portion of the conductive film located above the insulating film and forming a plurality of wirings in which the conductive film is buried in each of the wiring grooves (e). . The method for manufacturing a semiconductor device according to claim 14,
In the step (c), a first resist film having an opening in a part of the plurality of contact holes and located above at least one contact hole is formed above the insulating film. Sub-step (c1);
A sub-step (c2) of forming a part of the plurality of wiring grooves by etching the insulating film using the first resist film as a mask;
After removing the resist film, a second opening having a portion above the insulating film in a portion of the plurality of contact holes and located above the contact hole excluding the at least one contact hole. A sub-step (c3) of forming a resist film of
A sub-step (c4) of forming a part of the plurality of wiring grooves by etching the insulating film using the second resist film as a mask. A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 14,
In the above step (c), a method for manufacturing a semiconductor device, wherein the wiring grooves are formed in ascending order of area. The method for manufacturing a semiconductor device according to claim 14,
In the above step (c), a method for manufacturing a semiconductor device, wherein the wiring grooves are formed in order from the one having the smallest depth. (A) forming an insulating film above a base portion on which the element is formed;
(B) forming a contact hole in the insulating film;
Forming (c) a wiring groove connected to each of the contact holes and a through groove penetrating the insulating film in the insulating film;
(D) forming a conductive film extending over the insulating film by filling the contact holes, the wiring grooves and the through grooves;
Removing the portion of the conductor film located above the insulating film, and embedding the conductor film in each of the wiring grooves and through-grooves (e).

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