JP2004252728A - Method for compiling, compiler, compilation device, program code creation method, program, calculation method and device for optimum utilization of cache - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for compiling that reduces a total cache miss including a cache line conflict and improves processing speed, a compiler, a compilation device, a program code creation method, a program, a calculation method of optimum utilization of cache and a calculation device for optimum utilization of cache. <P>SOLUTION: Scheduling sequentially carries out each small loop belonging to the same data localizable group (DLG) as much as possible after loop alignment and partitioning, and by executing layout change of array data used by each DLG using a padding, allocates a plurality of partial array data used by each small loop belonging to the same DLG on a cache without them being overlapped. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a compiling method for compiling a source program to generate a target program, a compiler, and a compiling device, a program code generating method for generating codes constituting the program, programs generated or generated by these, and programs for these. For example, the present invention relates to a method for optimally using cache and an arithmetic device for optimally using cache, which can be used, for example, when performing an arithmetic operation by effectively using a cache memory using a shared-memory multiprocessor machine.
[0002]
[Background Art]
In general, many computers include a fast-running processor, a slow-access main memory, and a relatively fast-access, relatively small-capacity cache memory provided to bridge these speed gaps. . A data transfer unit between the main memory and the cache memory (hereinafter, sometimes simply referred to as cache) is called a block. There are three types of methods for deciding which cache line on the cache to place a block transferred from the main memory, a full associative method, a set associative method, and a direct map method.
[0003]
In the direct map method, each of the blocks transferred from the main memory has a certain fixed cache line (for example, the address of the cache line is often determined by the lower bits of the address of the main memory). Therefore, even if the data is placed on the cache line once, if the data contained in the block mapped to the same cache line is referenced, the data placed on the cache line will be At the time of the next reference, it will not be in the cache. This phenomenon is called a cache line conflict, and a cache miss caused by this is called a cache line conflict miss.
[0004]
Further, in the set associative method, each of the blocks transferred from the main memory is mapped to a predetermined plurality of (n in the case of n-way set associative) cache lines, and becomes empty. If there is no empty cache line, a cache line conflict occurs as in the case of the direct map method.
[0005]
Therefore, in a computer having a direct map type or set associative type cache, depending on the program, cache line conflicts frequently occur, and the processing speed may be significantly reduced.
[0006]
Conventionally, as a method of reducing such cache line conflict miss, for example, intra-variable padding for changing the declared size of a variable, and inter-variable padding for inserting a dummy variable between a plurality of variables (intra-variable padding). A method of changing the data layout such as inter-variable padding has been studied (for example, see Patent Document 1).
[0007]
On the other hand, a data localization method has also been studied for coarse-grained task parallel processing of multi-grain parallel processing for improving the effective performance of a multiprocessor system. The applicant of the present invention applies a data localization method to a cache on an SMP machine and executes a coarse-grained task for sharing data continuously on the same processor, thereby effectively utilizing the cache for data transfer between coarse-grained tasks. (See Non-Patent Documents 1 and 2).
[0008]
In this coarse-grained task parallel processing, the source program is divided hierarchically to generate macrotasks, and after analyzing the control flow and data dependence between macrotasks, the parallelism between macrotasks is extracted. Then, a procedure of analyzing the earliest executable condition of each macro task is taken. The earliest execution condition of a macro task is a condition under which the macro task can be executed at the earliest point (see Non-Patent Document 3).
[0009]
[Patent Document 1]
JP-A-8-212081 (paragraphs [0021] to [0024], [0027], [0028], [0094], FIG. 15)
[Non-patent document 1]
Hironori Kasahara, one other, "A-data-localization compilation scheme using partial-static task assignment for fortran course-grain parallel processing (A data-localization) compilation scheme using partial-static task assignment for Fortran course-grain parallel processing ", Parallel Computing (PARALLEL COMPUTING), (Netherlands), Parallel Computing (PARALLEL COLLING) mputing 24 (1998), p. 579-596
[Non-patent document 2]
Ishizaka, Nakano, Yagi, Obata, Kasahara, "Coarse-grained task parallel processing considering cache optimization on shared memory multiprocessor", Transactions of Information Processing Society of Japan, IPSJ, 2002, Vol. 43, no. 4
[Non-Patent Document 3]
Hironori Kasahara, "Parallel Processing Technology," Corona Publishing, June 20, 1991 (first edition), p. 140-148
[0010]
[Problems to be solved by the invention]
As described above, a conflict miss with respect to a single loop or a loop in which a plurality of loops are conventionally fused (this loop fusion is described in detail in p.125-128 of Non-Patent Document 3 described above). Reduction methods are being studied. These techniques are mainly used for padding to reduce line conflict errors between sequences used in the same iteration, and when data used in the outer iteration is used in the next iteration. Is a padding method to prevent data from being evicted from the cache.
[0011]
However, conventional padding can improve locality within a single loop by reducing conflict errors, but cannot reduce global conflict errors for data accessed between multiple loops. There was a problem.
[0012]
In the conventional data localization method, a cache miss can be reduced by allocating a data set accessed between divided loop sets belonging to the same data localizable group to a cache on the same processor, but a line conflict can be reduced. There was a problem that it could not be performed (see the upper right part of FIG. 6 described later, the right parts of FIGS. 14 to 17 and the left part of FIG. 22).
[0013]
An object of the present invention is to reduce a total cache miss including a line conflict and improve a processing speed, a compiling method, a compiler, a compiling device, a program code creating method, a program, a cache optimal use calculation method, and a cache. It is an object of the present invention to provide an optimal utilization arithmetic unit.
[0014]
[Means for Solving the Problems]
The present invention is a compiling method for compiling a source program to generate a target program, wherein each of the plurality of loops having data dependence included in the source program is divided to generate a plurality of small loops for each loop, Of these small loops, small loops using the same partial array data are aggregated to form a plurality of data localizable groups, and at the time of this division / grouping processing, each data localizer Alignment division is performed so that the total size of the partial array data used by each small loop belonging to each small loop falls within the size of the cache memory for each data localizable group. Execution confirmation condition that execution is decided and data required for execution of each small loop Within the range that satisfies the earliest executable condition consisting of the data access condition that can be used, each small loop belonging to the same data localizable group performs scheduling that is executed as continuously as possible, The data layout using padding is performed on each array data so that each array data partially used by each small loop belonging to the localizable group has no overlap on the cache memory. Is what you do.
[0015]
Here, the term "compile" in the present invention means compilation in a broad sense, which means not only conversion processing from a source program to a narrowly-defined object program composed of machine language code (strictly-defined compilation), but also, for example, Fortran or the like. A conversion process from a source program composed of high-level language codes to a program composed of high-level language codes such as Fortran is also included. Furthermore, the conversion process into a program in a state before being made an executable program by a linker (linkage editor) is also included. The same applies to the following inventions.
[0016]
Further, the "object program" in the present invention includes not only an object program in a narrow sense constituted by machine language codes but also a program constituted by high-level language codes such as Fortran. Further, a program in a state before being made an executable program by the linker is also included. The same applies to the following inventions.
[0017]
Further, "partial array data" refers to a part of one array data, and is generated by dividing a loop using the array data. For example, when the array data is A (1: 1024, 1: 1024), A (1: 1024, 1: 256), A (1: 1024, 257: 512), and the like correspond to partial array data. I do.
[0018]
Then, "perform consistent division so that the total size of each partial array data used by each small loop belonging to each data localizable group falls within the cache memory size for each data localizable group." Means that the total size of a plurality of partial array data used by each of the small loops belonging to the same data localizable group is consistently divided so as to be smaller than the cache size. This means that it is established for each localizable group.
[0019]
In addition, the data layout change using padding is performed on each array data so that the partial array data used by each small loop belonging to each data localizable group do not overlap on the cache memory. `` Do '' means that the cache memory does not have an overlap, but the target is a partial array data unit. This means that array data or a set of a plurality of array data is considered as a unit instead of an array data unit.
[0020]
Further, any of "scheduling" and "data layout change" may be performed first.
[0021]
To "perform scheduling" means to change the arrangement order and arrangement position of each small loop belonging to each data localizable group in the target program to determine the execution order, and to set the scheduling information ( For example, this includes inserting information for providing a jump function such as a GOTO statement, etc.) to determine the execution order.
[0022]
In the compiling method of the present invention, loop matching division is performed for a plurality of data-dependent loops included in a source program, and array data used (accessed) by these loops using padding. Make layout changes. Then, scheduling is performed to execute the small loops belonging to the same data localizable group as continuously as possible.
[0023]
For this reason, as a result of performing the scheduling as described above, a plurality of partial array data used by each of the small loops after the matching division belonging to the same data localizable group must be successively placed in one cache. At this time, since the plurality of partial array data are laid out using padding, they are mapped to different lines in the cache, so that there is no overlap in the cache. For example, when the sequence data is A (1: 1024, 1: 1024) and B (1: 1024, 1: 1024), A (1: 1024, 1: 256) which is a partial sequence data of these data is used. ) And B (1: 1024, 1: 256) are used by each small loop belonging to the same data localizable group, and A (1: 1024, 1: 256) and B (1: 1024, 1: 256) 256) is placed in one cache and is mapped to a different line on the cache (see the right part of FIGS. 7 to 10, 18 to 21, and 22 described later).
[0024]
Therefore, a cache line conflict miss is avoided, and the processing speed of the computer (for any purpose, for example, for academic calculation, accounting, game, office work, other arithmetic processing, etc. is arbitrary). It is possible to improve the above, thereby achieving the above object.
[0025]
Further, in the above-mentioned compiling method, when performing scheduling for a multiprocessor for performing parallel processing using a plurality of processors, each of the groups belonging to the same data localizable group within a range satisfying the earliest executable condition. It is desirable to perform scheduling in which small loops are executed continuously on the same processor as much as possible.
[0026]
Here, the number of processors and the number of divisions of the loop matching division may or may not match.
[0027]
In the case where application to a multi-processor machine is performed in this way, loop processing performed in each data localizable group can be performed in a distributed manner by a plurality of processors. For example, each data localizable group Can be assigned to different processors for each data localizable group, and the processing speed can be further increased by utilizing the parallelism of the loop processing performed in each data localizable group. It can be improved.
[0028]
Further, in the above-mentioned compiling method, the padding may be an area secured by data (so-called dummy data) different from an array used by each small loop belonging to each data localizable group (for example, FIG. 18 described later). 21), or the size of at least one of the arrays used by each small loop belonging to each data localizable group may be increased and secured for the non-contiguous access dimension. Good (for example, in the case of FIGS. 7 to 10 and FIG. 22 described later).
[0029]
Further, among the above, in the latter case of performing padding by expanding the array size for the non-contiguous access dimension, the size of the array used by each small loop belonging to each data localizable group is set for each array. The padding may be performed by expanding the non-contiguous access dimension (for example, in the case of FIGS. 7 to 10 and FIG. 22 described later), or a set of a plurality of arrays is used as one unit instead of each array. The padding may be considered (for example, in FIGS. 18 to 21 described later, the arrays E, K, and R are enlarged instead of inserting dummy data after each of the arrays E, K, and R). Case). However, when padding is performed for each array, it is not always necessary to perform padding for the last array.
[0030]
Note that the “non-contiguous access dimension” is the dimension having the largest access stride at the time of memory storage among the declared dimensions of the array. For example, in the case of Fortran, the dimension declared at the right end is the column major order, That is, if it is A (i, j, k), the declaration size of the dimension of k is enlarged and changed. In other words, the “non-contiguous access dimension” is a dimension in which a state fixed in each iteration continues in a loop process in the case of a multi-dimensional array. This is a dimension that changes in a loop (a loop to be placed outside from the viewpoint of processing efficiency). Specifically, for example, A (1,1), A (2,1), A (3,1),..., A (1,2), A (2,2), A (3,2) , ..., the size of the second dimension is enlarged and changed.
[0031]
Further, a compiler according to the present invention is characterized in that compilation is performed using the compilation method described above.
[0032]
In such a compiler of the present invention, the operation and effect obtained by the above-described compiling method of the present invention can be obtained as it is, thereby achieving the above object.
[0033]
Further, the present invention is a compiler for compiling a source program to generate a target program, wherein the macro task generating means for generating a plurality of macro tasks by dividing the source program into blocks is provided. Parallelism analysis means for analyzing the earliest executable condition consisting of the execution determination condition to be determined and the data access condition that makes the data necessary for the execution of each macro task usable, and the data dependency included in the source program as each macro task Target loop group selecting means for selecting, as a target loop group for cache optimization, a plurality of loops capable of performing loop matching division for effectively using a cache memory from among the loops having Selected by group selection means Target loop group storage means for storing the target loop group in the target loop group table, and a target for selecting each array data used by each of a plurality of loops constituting the target loop group as target array data for cache optimization An array data selection unit, a target array data storage unit that stores each target array data selected by the target array data selection unit in a target array data table, and a total size of each target array data and a size of a cache memory. Division number determining means for determining the number of divisions of the plurality of loops constituting the target loop group, and a plurality of division numbers for constituting the target loop group stored in the target loop group table based on the division number determined by the division number determining means. Le Each of the loops is divided into a plurality of small loops, and each of the small loops using the same partial target sequence data is aggregated to form a plurality of data localizable groups. Within a range that satisfies an earliest executable condition including a loop matching division unit to be formed, an execution determination condition for determining execution of each small loop, and a data access condition for enabling data necessary for execution of each small loop to be usable. Scheduling means for performing scheduling in which small loops belonging to the same data localizable group are executed as continuously as possible, and partial target arrays used by small loops belonging to each data localizable group Each target array data is stored so that the data do not overlap in the cache memory. Padding size determining means for determining the size of padding data to be inserted to shift the storage position of the data in the main memory, and padding data corresponding to the size determined by the padding size determining means are stored in the target array data table. The present invention is characterized by causing a computer to function as data layout changing means for changing a data layout using padding by inserting it into the stored target sequence data or between target sequence data.
[0034]
Here, "based on the total size of each target array data and the size of the cache memory" in the "division number determining means" means that the division is based on a value obtained by dividing the total size of all the target array data by the size of the cache memory. It means determining the number.
[0035]
Further, "inserting inside the target array data or between target array data" means that the size of the target array is expanded for the non-contiguous access dimension, or so-called dummy data is inserted between the target array data.
[0036]
In such a compiler of the present invention, the operation and effect obtained by the above-described compiling method of the present invention can be obtained as it is, thereby achieving the above object.
[0037]
The present invention relates to a compiling apparatus for compiling a source program to generate a target program, the macro task generating means for generating a plurality of macro tasks by dividing the source program into blocks, and executing each macro task. Parallel analysis means for analyzing the earliest executable condition consisting of an execution finalizing condition to be determined and a data access condition in which data necessary for the execution of each macro task become usable, and data included in the source program as each macro task A target loop group selecting unit for selecting, as a target loop group for cache optimization, a plurality of loops capable of performing loop matching division for effectively using the cache memory from among the loops having dependencies; Selected by the loop group selection means A target loop group table for storing the target loop group, and target array data selecting means for selecting each array data used by each of a plurality of loops constituting the target loop group as target array data for cache optimization, A target array data table for storing each target array data selected by the target array data selecting means, and the number of divisions of a plurality of loops constituting a target loop group based on the total size of each target array data and the size of the cache memory A plurality of loops constituting the target loop group stored in the target loop group table based on the number of divisions determined by the number of divisions determined by the number of divisions determining means. small Loop matching dividing means for generating a plurality of data localizable groups by collecting small loops using the same partial target sequence data among these small loops, and forming a plurality of data localizable groups. Each small loop belonging to the same data localizable group within a range that satisfies the earliest executable condition consisting of the execution determination condition that execution is determined and the data access condition that makes data necessary for execution of each small loop available. However, scheduling means for performing scheduling that is executed as continuously as possible and partial target array data used by each small loop belonging to each data localizable group do not overlap each other on the cache memory. The pad inserted to shift the storage location of each target sequence data in the main memory Padding size determining means for determining the size of the padding data, and padding data corresponding to the size determined by the padding size determining means, inside the target array data stored in the target array data table or between the target array data. Data layout changing means for performing a data layout change using padding by insertion.
[0038]
In such a compiling device of the present invention, the operation and effect obtained by the above-described compiling method of the present invention can be obtained as it is, thereby achieving the above object.
[0039]
Further, the present invention is a program code creating method for creating a code constituting a program, wherein a plurality of loops having data dependence to be executed are respectively divided to create a plurality of small loops for each loop, Of these small loops, small loops using the same partial array data are aggregated to form a plurality of data localizable groups, and at the time of this division / grouping work, each data localizer Alignment division is performed so that the total size of the partial array data used by each small loop belonging to each small loop falls within the size of the cache memory for each data localizable group. The execution confirmation condition that the execution is confirmed and the data necessary to execute each small loop are available. The scheduling is performed so that the small loops belonging to the same data localizable group are executed as continuously as possible within a range that satisfies the earliest executable condition consisting of the data access conditions. Each array data is laid out using padding so that partial array data used by each small loop belonging to the group do not overlap on the cache memory.
[0040]
In such a program code creating method of the present invention, the operation and effect obtained by the above-described compiling method of the present invention can be obtained as it is, thereby achieving the above object.
[0041]
Furthermore, in the above-described method of creating a program code, when performing scheduling for a multiprocessor for performing parallel processing using a plurality of processors, the same data localizable group is set within a range satisfying the earliest executable condition. It is desirable to perform scheduling so that the small loops belonging to each other are executed continuously on the same processor as much as possible.
[0042]
In the case where application to a multi-processor machine is performed in this way, loop processing performed in each data localizable group can be performed in a distributed manner by a plurality of processors. For example, each data localizable group Can be assigned to different processors for each data localizable group, and the processing speed can be further increased by utilizing the parallelism of the loop processing performed in each data localizable group. It can be improved.
[0043]
A program according to the present invention is characterized by being generated or created by using the compile method or the program code creating method described above.
[0044]
Furthermore, a program of the present invention is characterized by being generated by the compiler described above.
[0045]
The above-described program or a part thereof is, for example, a magneto-optical disk (MO), a read-only memory (CD-ROM) using a compact disk (CD), a CD recordable (CD-R), a CD rewritable disk. (CD-RW), read-only memory (DVD-ROM) using digital versatile disk (DVD), random access memory (DVD-RAM) using DVD, flexible disk (FD), magnetic tape, It can be recorded on a recording medium such as a hard disk, a read-only memory (ROM), an electrically erasable and rewritable read-only memory (EEPROM), a flash memory, a random access memory (RAM), and stored or distributed. Possible and, for example, local area networks LAN, a metropolitan area network (MAN), a wide area network (WAN), a wired network such as the Internet, an intranet, an extranet, or a wireless communication network, or a transmission medium such as a combination thereof. It is also possible to carry on a carrier wave. Furthermore, the program described above may be a part of another program, or may be recorded on a recording medium together with a separate program.
[0046]
In addition, the method for optimally using cache according to the present invention executes the above-described program by using an arithmetic unit having a processor, a main memory, and a cache memory provided therebetween, and It is characterized in that arithmetic processing is performed using a cache memory while suppressing the occurrence of line conflict miss.
[0047]
Furthermore, the cache optimal use operation device of the present invention includes a processor, a main memory, and a cache memory provided therebetween, and the above-described program is mounted thereon, and by executing this program, It is characterized in that arithmetic processing is performed using a cache memory while suppressing the occurrence of a cache line conflict miss.
[0048]
The application of the cache optimum utilization arithmetic device of the present invention is arbitrary, for example, for academic calculation, accounting, game, office work, and other arithmetic processing.
[0049]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration of a compiling device 10 and a cache optimum use arithmetic device 20 of the present embodiment. FIG. 2 is a configuration diagram functionally showing the compiling device 10.
[0050]
The compiling device 10 is a device that compiles the source program 1 and generates the target program 2. The cache optimal use operation device 20 is a device in which the target program 2 generated by the compiling device 10 or a program obtained by further compiling the target program 2 is mounted as a program 3 in an executable state. Although the compiling device 10 and the cache optimal use computing device 20 are described as separate devices for the sake of convenience of description, they may be realized by using physically the same device (computer).
[0051]
In FIG. 1, a compiling device 10 is constituted by a computer having a CPU (Central Processing Unit) 11, and has a compiler 12 which is a language processing program for compiling a source program 1 and generating a target program 2. ing.
[0052]
The cache optimal use arithmetic unit 20 is a shared main memory multiprocessor machine, and operates at high speed to perform various arithmetic processes (in the present embodiment, four processors by way of example). 33, a main memory 40 that is accessed in a shared state by the processors 30 to 33, and a plurality of memory units provided between the processors 30 to 33 and the main memory 40. ) L2 caches 50, 51, 52, and 53, and an external storage device 60 connected to the main memory 40.
[0053]
Each of the L2 caches 50 to 53 is a level 2 cache memory that can be accessed at a higher speed than the main memory 40 that has a slower access speed, and has a relatively small capacity.
[0054]
The external storage device 60 is, for example, a large-capacity memory such as a hard disk, and stores the program 3 executed by the cache optimal use operation device 20. The use of the program 3, that is, the use of the cache optimal use arithmetic device 20 is arbitrary, for example, for academic calculation, accounting, game, office work, and other arithmetic processing.
[0055]
The processors 30, 31, 32, and 33 have L1 caches 70, 71, 72, and 73, respectively. These L1 caches 70 to 73 are cache memories that can be accessed at a higher speed than the L2 caches 50 to 53, but have a smaller memory capacity than the L2 caches 50 to 53. In the present embodiment, it is assumed that the L2 caches 50 to 53 are selected as cache optimization targets. However, the cache optimization target according to the present invention may be not only the L2 caches 50 to 53 but also the L1 caches 70 to 73. If there are L3 caches or L4 or higher caches, those caches can also be targeted for optimization according to the present invention.
[0056]
Although not shown in the drawings, the compiling device 10 and the cache optimal use calculating device 20 may be, for example, a mouse, a keyboard, a trackball, a light pen, a trackpad, a trackpoint, a tablet and a stylus, a joystick, Input means such as a combination, display means such as a liquid crystal display, a CRT display, an organic EL display, an ECL display, a projector and a screen, or a combination thereof, and output means such as a printer, a plotter, or a combination thereof Are provided as appropriate.
[0057]
2, a compiling device 10 includes a processing unit 13 for performing various processes required for compiling, and a target loop group table 14 and a target array data table 15 for storing data necessary for the processing by the processing unit 13. It is configured to include a table.
[0058]
The processing unit 13 includes a macro task generation unit 13A, a parallelism analysis unit 13B, a target loop group selection unit 13C, a target loop group storage unit 13D, a target array data selection unit 13E, and a target array data storage unit 13F. , A division number determining unit 13G, a loop matching dividing unit 13H, a scheduling unit 13J, a padding size determining unit 13K, and a data layout changing unit 13L.
[0059]
Each of the units 13A to 13L constituting the processing unit 13 is realized by the CPU 11 and the compiler 12 that specifies the operation procedure of the CPU 11. Various tables such as the target loop group table 14 and the target sequence data table 15 are held in a main memory (not shown) of the compiling device 10 or, if necessary, provided on an external device such as a hard disk provided in the compiling device 10. It is stored in a storage device (not shown).
[0060]
The macro task generating means 13A performs a process of dividing the source program 1 into blocks to generate a plurality of macro tasks.
[0061]
The parallelism analysis unit 13B is configured to execute the earliest execution condition (also referred to as the earliest execution start condition) including an execution determination condition for determining execution of each macrotask and a data access condition for enabling data necessary for the execution of each macrotask. ) Is analyzed.
[0062]
Here, the earliest executable condition of a certain macro task X is simply expressed as follows. The former execution determination condition defines the flow of a program (control flow). In a macrotask graph expressing parallelism between coarse-grained tasks, a macrotask including a conditional branch in which macrotask X depends on control is defined as: This is a condition for branching in a direction to determine the execution of the macro task X. The latter data access condition determines that the execution of the preceding task (data-dependent preceding macro task) that defines or uses the data before the macro task X ends, or that the data-dependent preceding macro task is not executed, This is a condition that data required by the macro task X can be used. The earliest executable condition is described in p. Since it is described in detail near 145, detailed description is omitted here.
[0063]
The target loop group selecting means 13C is for making effective use of the cache memory (in the present embodiment, the L2 caches 50 to 53) among the loops having data dependence included in the source program 1 as macro tasks. A process of selecting a plurality of loops that can be subjected to loop matching division as a target loop group (TLG: Target Loop Group) for cache optimization is performed.
[0064]
The target loop group storage unit 13D stores the plurality of loops selected by the target loop group selection unit 13C in the target loop group table 14.
[0065]
The target array data selecting means 13E performs a process of selecting each array data used (accessed) by a plurality of loops constituting the target loop group as target array data for cache optimization.
[0066]
The target sequence data storage unit 13F performs a process of storing each target sequence data selected by the target sequence data selection unit 13E in the target sequence data table 15.
[0067]
The number-of-divisions determining unit 13G performs a process of determining the number of divisions of a plurality of loops constituting the target loop group (the number of divisions when each of the plurality of loops is divided) based on the total size and cache size of each target sequence data. Is what you do. Specifically, when the total size of each target array data is larger than the cache size, the number of divisions of each loop is set so that the value obtained by dividing the total size of each target array data by the number of divisions is equal to or smaller than the cache size. To determine. That is, the number of divisions is equal to or larger than a value obtained by dividing the total size of each target array data by the cache size. If the total size of each target array data is equal to or smaller than the cache size, padding is not performed.
[0068]
The loop matching division unit 13H divides a plurality of loops constituting the target loop group stored in the target loop group table 14 based on the number of divisions determined by the number-of-divisions determination unit 13G, and divides each of the plurality of loops into a plurality of small loops. A process of generating loops and collecting small loops using the same partial target sequence data among the small loops to form a plurality of data localizable groups (DLGs); It is. Since the loop matching division is described in detail in Non-Patent Document 1, the detailed description is omitted here.
[0069]
The scheduling means 13J outputs the same data within a range that satisfies the earliest executable condition including the execution determination condition for determining the execution of each small loop and the data access condition for enabling the data necessary for the execution of each small loop to become usable. Each small loop belonging to the localizable group performs a scheduling process that is executed as continuously as possible.
[0070]
When a program to be executed by a device having a plurality of processors, such as the cache optimal use operation device 20 of the present embodiment, is to be compiled, the scheduling means 13J performs the following processing. That is, when performing scheduling for a multiprocessor for performing parallel processing using a plurality of processors, each small loop belonging to the same data localizable group can be set within a range that satisfies the earliest executable condition. A scheduling process executed continuously on the same processor is performed as much as possible.
[0071]
The padding size determining unit 13K stores the target array data in the main memory 40 so that the partial target array data used by each small loop belonging to each data localizable group do not overlap each other on the cache. The processing for determining the size of padding data to be inserted to shift the storage position is performed.
[0072]
The data layout changing unit 13L inserts padding data corresponding to the size determined by the padding size determining unit 13K into the target array data stored in the target array data table 15 or between the target array data, thereby performing padding. The data layout changing process is performed by using.
[0073]
The target loop group table 14 stores the target loop groups selected by the target loop group selection unit 13C.
[0074]
The target sequence data table 15 stores each target sequence data selected by the target sequence data selecting means 13E.
[0075]
In this embodiment, compilation is performed using the compilation device 10 as follows. FIG. 3 is a flowchart illustrating the flow of the compile process performed by the compile device 10.
[0076]
First, a source program 1 to be compiled is prepared. Here, in order to facilitate understanding, description will be made using a program 100 as shown in FIG. 4 as a specific example. In addition, the size of each of the L2 caches 50 to 53 of the cache optimal use arithmetic unit 20 is set to 4 megabytes (see FIG. 4). Further, the data transfer from the main memory 40 to each of the L2 caches 50 to 53 is based on the direct map method (association is 1). However, the present invention is not limited to the direct map method, and is also effective when applied to a set associative method (associability of 2 or more). Note that the transfer block length (cache line length) is not particularly assumed, and is arbitrary, for example, 32 bytes or 64 bytes.
[0077]
In FIG. 4, the program 100 is described in a high-level language such as Fortran. The program 100 includes an array declaration unit 101 and a plurality of (here, two) loops 102 and 103 having data dependency with each other.
[0078]
In the array declaration unit 101, four two-dimensional arrays are declared. Each array is A (1024, 1024), B (1024, 1024), C (1024, 1024), D (1024, 1024), and one element of each array is an integer (integer type) of 4 bytes. It is. Therefore, the size of the array A is 1024 × 1024 × 4 = 4 megabytes. The same applies to the other arrays B, C, and D. The total size of each array A, B, C, D is 16 megabytes. The right part of FIG. 4 shows an image when the 4-megabyte arrays A, B, C, and D are allocated on a 4-megabyte cache. In this example, the sizes of the arrays A, B, C, and D are all the same, but the present invention can be applied to a case where the sizes of the arrays are different.
[0079]
Then, the power of the compiling device 10 is turned on, the compiler 12 (see FIG. 1) is started, and the compiling process for the prepared source program 1 is started (step S1 in FIG. 3).
[0080]
Next, preprocessing is performed by the macro task generating means 13A and the parallelism analyzing means 13B (step S2). In this preprocessing, the source code is converted into an intermediate language, and a variable table is created. Then, the macro task generating means 13A divides the program 100 to be compiled into blocks such as loops, subroutines, and basic blocks to generate a plurality of macro tasks.
[0081]
Subsequently, the parallelism analysis unit 13B performs data dependency analysis and control flow analysis on each macro task generated by the macro task generation unit 13, and then analyzes the earliest executable condition including the execution determination condition and the data access condition. To analyze the parallelism between macro tasks such as loops, subroutines, and basic blocks included in the program 100.
[0082]
Then, the target loop group selecting unit 13C can perform a loop division for the cache optimization among the loops with data dependence included in the program 100, that is, a plurality of loops that can be subjected to the coherent division to the cache optimization. Is selected as a target loop group (TLG) (step S3 in FIG. 3). In the example of FIG. 4, it is assumed that two loops 102 and 103 are selected as a target loop group (hereinafter, referred to as TLG1).
[0083]
Then, the loops 102 and 103 constituting the TLG1 selected by the target loop group selection unit 13C are stored in the target loop group table 14 by the target loop group storage unit 13D.
[0084]
Subsequently, the arrays A, B, C, and D used (accessed) by the plurality of loops 102 and 103 constituting the TLG 1 are selected as target arrays for cache optimization by the target array data selection unit 13E. (Step S4 in FIG. 3).
[0085]
Then, the target arrays A, B, C, and D selected by the target array data selection unit 13E are stored in the target array data table 15 by the target array data storage unit 13F.
[0086]
Then, based on the total size and the cache size of each of the target arrays A, B, C, and D, the number of divisions of the plurality of loops 102 and 103 constituting the TLG 1 (the plurality of loops 102 and 103 The number of divisions at the time of division is determined (step S5 in FIG. 3).
[0087]
In the example of FIG. 4, since the total size of each target array A, B, C, and D is 16 megabytes and the cache size is 4 megabytes, the total size of each target array data is larger than the cache size. Therefore, the number of divisions of each of the loops 102 and 103 is determined so that the value obtained by dividing the total size of each of the target array data A, B, C, and D by the number of divisions is equal to or smaller than the cache size. That is, when the total size of the target arrays A, B, C, and D is divided by the cache size, 16 megabytes / 4 megabytes = 4. Here, it is assumed to be divided into four as an example.
[0088]
After the division number is determined by the division number determining means 13G, as shown in FIG. 5, based on the determined number of divisions (here, four divisions), the data is stored in the target loop group table 14 by the loop matching division means 13H. Each of the plurality of loops 102 and 103 constituting the TLG1 is divided (here, divided into four), and a plurality of (here, four) small loops 102A, 102B, 102C, 102D are generated for the loop 102, and With respect to 103, a plurality (here, four) of small loops 103A, 103B, 103C, and 103D are generated (step S6 in FIG. 3).
[0089]
In the example of FIG. 4, each element A (i, j) of the array A, where i = 1 to 1024 and j = 1 to 1024, is arranged in the order of A (1,1), A (2,1). ), A (3,1),..., The first dimension i is a continuous access dimension, and the second dimension j is a discontinuous access dimension. The same applies to the other arrays B, C, and D. In the loops 102 and 103, as shown in FIG. 4, since the outer loop has j = 1 to 1024, the second dimension j which is the discontinuous access dimension is divided into four, and j = 1 to Let 256 be small loops 102A and 103A, j = 257 to 512 be small loops 102B and 103B, j = 513 to 768 be small loops 102C and 103C, and j = 769 to 1024 be small loops 102D and 103D.
[0090]
Arrays A, B, C, and D are also divided into four according to j = 1 to 256, j = 257 to 512, j = 513 to 768, and j = 769 to 1024, so that each array A, B, C , D, each generate four partial arrays. For example, regarding the sequence data A (1: 1024, 1: 1024), A (1: 1024, 1: 256), A (1: 1024, 257: 512), A (1: 1024, 513: 768), A (1: 1024, 769: 1024) of four partial array data is generated. The same applies to the other arrays B, C, and D.
[0091]
Here, as shown in FIG. 5, the two small loops 102A and 103A are composed of A (1: 1024, 1: 256), B (1: 1024, 1: 256), and C (1: 1024, 1: 256). ) And D (1: 1024, 1: 256). Therefore, a data localizable group (hereinafter, referred to as DLG10) is formed by a set of the two small loops 102A and 103A. Similarly, a set of two small loops 102B and 103B forms a data localizable group (hereinafter referred to as DLG11), and a set of two small loops 102C and 103C forms a data localizable group (hereinafter referred to as DLG12). .) Are formed, and a set of two small loops 102D and 103D forms a data localizable group (hereinafter, referred to as DLG13).
[0092]
Each of the small loops 102A, 102B, 102C, 102D, 103A, 103B, 103C, and 103D obtained by performing the loop matching division as shown in FIG. 5 by the loop matching division unit 13H is also treated as a macro task. .
[0093]
Subsequently, after performing the loop matching division, the parallelism analysis unit 13B again includes the small loops 102A, 102B, 102C, 102D, 103A, 103B, 103C, and 103D, which are newly generated macro tasks. The analysis of the earliest executable condition including the execution determination condition and the data access condition is performed, and the parallelism between the macro tasks including the small loops 102A, 102B, 102C, 102D, 103A, 103B, 103C, and 103D is analyzed.
[0094]
Then, the scheduling unit 13J sets the same execution condition within the range that satisfies the earliest execution condition including the execution determination condition for determining execution of each small loop and the data access condition for making data necessary for execution of each small loop available. Is performed such that the small loops belonging to the data localizable group are continuously executed as much as possible on the same processor (step S7 in FIG. 3).
[0095]
In the example of FIG. 4, 102A and 103A belonging to the DLG 10 are continuously executed on the same processor, 102B and 103B belonging to the DLG 11 are continuously executed on the same processor, and 102C and 103C belonging to the DLG 12 are continuously executed on the same processor. , DLD13, 102D and 103D are continuously executed on the same processor.
[0096]
FIG. 11 shows an execution image when scheduling for allocating different data localizable groups to the four processors 30 to 33 is performed. In FIG. 11, the DLG 10, DLG 11, DLG 12, and DLG 13 are processed in parallel by the processors 30 to 33.
[0097]
FIG. 12 shows an execution image when the scheduling for allocating all the data localizable groups to one processor (here, the processor 30) is performed. In FIG. 12, processing is performed in the order of DLG10, DLG11, DLG12, and DLG13. This case is similar to that of a single processor machine.
[0098]
After scheduling is performed by the scheduling unit 13J, the padding size determination unit 13 causes the partial target array data used by each of the small loops belonging to the DLG10, DLG11, DLG12, and DLG13 to have no overlap in the cache. Thus, the size of the padding data to be inserted to shift the storage position of each target array data in the main memory 40 is determined (step S8 in FIG. 3).
[0099]
As shown in FIG. 5, in the DLG 10, A (1: 1024, 1: 256), B (1: 1024, 1: 256), C (1: 1024, 1: 256), D (1: 1024, 1) : 256), the padding amount is determined so that they do not overlap on the cache. The same applies to DLG11, DLG12, and DLG13.
[0100]
FIG. 6 is an explanatory diagram of a line conflict occurring when the DLG 10 is executed and a padding amount for avoiding the line conflict. As shown in the upper right part of FIG. 6, if no padding is performed, all of the partial array data accessed by the small loops 102A and 103A belonging to the DLG 10 are all allocated to the same area on the cache, so that the cache line Conflicts occur.
[0101]
Therefore, if a data layout as shown in the lower right part of FIG. 6 is used, partial array data is allocated to different areas on the cache, and there is no overlap, so that line conflict is reduced. Therefore, the padding amount for one array data of 4 megabytes (for example, A (1: 1024, 1: 1024), etc.) is determined by one partial array data (for example, A (1 : 1024, 1: 256)) and 1 megabyte.
[0102]
Subsequently, the padding data corresponding to the size determined by the padding size determining unit 13K is stored in the target array A, B, C, or D stored in the target array data table 15 or by the data layout changing unit 13L. The data layout is changed using padding by inserting data between the target arrays A, B, C, and D (step S9 in FIG. 3).
[0103]
FIGS. 7 to 10 are explanatory diagrams illustrating a state in which padding is performed to avoid a line conflict when the DLG 10, DLG 11, DLG 12, or DLG 13 is executed. The upper right part of FIGS. 7 to 10 shows a state in which padding data (the shaded area in the drawing) is inserted into each of the target arrays A, B, C, and D. The size of each of the target arrays A, B, C, and D is enlarged for the second dimension j (the dimension in which the numerical value in the figure is underlined), which is a discontinuous access dimension. For array A, A (1: 1024, 1025: 1280) is inserted as 1 megabyte of padding data. Similarly, for array B, B (1: 1024, 1025: 1280) is inserted for array C, and for array C, C (1: 1024, 1025: 1280) is inserted as 1 Mbytes of padding data. . No padding data is inserted for the last array D.
[0104]
As shown in the lower right part of FIG. 7, when the DLG 10 is executed, the allocation area of the partial array data on the cache is A (1: 1024) from the top of the cache as indicated by the dotted arrow in the figure. , 1: 256), B (1: 1024, 1: 256), C (1: 1024, 1: 256), D (1: 1024, 1: 256), and do not overlap. Therefore, it can be seen that line conflict is avoided.
[0105]
As shown in the lower right part of FIG. 8, when the DLG 11 is executed, a partial allocation area of array data on the cache is D (1: 1024) from the top of the cache as indicated by a dotted arrow in the figure. , 257: 512), A (1: 1024, 257: 512), B (1: 1024, 257: 512), and C (1: 1024, 257: 512), and do not overlap. Therefore, it can be seen that line conflict is avoided.
[0106]
As shown in the lower right part of FIG. 9, when the DLG 12 is executed, an area where partial array data is partially allocated on the cache is, as indicated by a dotted arrow in the figure, C (1: 1024) from the top of the cache. , 513: 768), D (1: 1024, 513: 768), A (1: 1024, 513: 768), and B (1: 1024, 513: 768), and do not overlap. Therefore, it can be seen that line conflict is avoided.
[0107]
As shown in the lower right part of FIG. 10, when the DLG 13 is executed, a partial allocation area of array data on the cache is B (1: 1024) from the head of the cache as indicated by a dotted arrow in the figure. , 769: 1024), C (1: 1024, 769: 1024), D (1: 1024, 769: 1024), and A (1: 1024, 769: 1024), which do not overlap. Therefore, it can be seen that line conflict is avoided.
[0108]
When the data layout change using the padding by the data layout changing means 13L is completed, the target program 2 is generated. The target program 2 may be in the state of a high-level language code such as Fortran, or may be in the state of a narrowly defined object code composed of machine language codes. If the target program 2 generated by compiling is in a state of a high-level language code such as Fortran, further compiling is performed. The compilation at this time is performed by a normal compiler (not the compiler of the present invention) prepared for translating a high-level language such as Fortran, and the hardware implements the compiling device 10 of the present embodiment. The processing may be performed by one computer or another computer.
[0109]
Thus, the compile processing by the compiler 12 is completed (step S10 in FIG. 3). It should be noted that it is also possible for a person to manually create a program code similar to the compile processing by the compiler 12 described above.
[0110]
After that, as shown in FIG. 1, the target program 2 or a program obtained by further compiling the target program 2 is mounted on the cache optimum utilization arithmetic unit 20 as an executable program 3. Then, when the program 3 is executed by the cache optimum use arithmetic unit 20, the processing of the program including the DLG10, DLG11, DLG12, and DLG13 is executed according to the flow shown in FIG. 11 or FIG. Efficient arithmetic processing is performed while suppressing occurrence.
[0111]
Further, in the above description, the program 100 as shown in FIG. 4 has been described as a specific example, but in the following, description will be made using the program 200 as shown in FIG. 13 as a specific example.
[0112]
In FIG. 13, the program 200 is described in a high-level language such as Fortran. The program 200 includes a constant value setting unit 201 in which a parameter statement is described, an array declaration unit 202, and a plurality (here, three) of loops 203, 204, and 205 having data dependency with each other. I have.
[0113]
In the constant value setting unit 201, values of constants N1 and N2 for specifying the size of each array declared by the array declaration unit 202 are determined. Here, N1 = 513 and N2 = 513.
[0114]
In the array declaration section 202, thirteen two-dimensional arrays are declared. Each array has U (N1, N2), V (N1, N2), T (N1, N2), E (N1, N2), F (N1, N2), G (N1, N2), H (N1, N2). N2), K (N1, N2), N (N1, N2), P (N1, N2), Q (N1, N2), R (N1, N2), and S (N1, N2). One element is real (real number type) and is 4 bytes. Therefore, the size of the array U is 513 × 513 × 4 = about 1 megabyte. The same applies to the other arrays V, T, E, F, G, H, K, N, P, Q, R, and S. The total size of each of the 13 pieces of array data is about 13 megabytes. The right part of FIG. 13 shows an image when 13 array data of about 1 megabyte are allocated to a 4 megabyte cache during the processing of each of the loops 203, 204 and 205. Note that, in this example, the size of each of the thirteen arrays is all the same, but the present invention can also be applied to the case where the sizes of the arrays are different.
[0115]
In the case of the example of FIG. 13, the target loop group selected by the target loop group selection unit 13C is a target loop group (hereinafter, referred to as TLG2) including three loops 203, 204, and 205. Each of the loops 203, 204, 205 constituting the TLG2 is stored in the target loop group table 14 by the target loop group storage unit 13D.
[0116]
The target arrays selected by the target array data selecting means 13E are thirteen arrays U, V, T, E, F, G, H, K, N, P, Q, R, and S. Each of the 13 array data is stored in the target array data table 15 by the target array data storage unit 13F.
[0117]
Further, the determination of the number of divisions by the division number determining means 13G is performed as follows. When the total size of each of the 13 arrays is divided by the cache size, about 13 megabytes ÷ 4 megabytes = about 3.25, so the number of divisions is 4 or more. Here, it is divided into four.
[0118]
Then, the loop matching division by the loop matching division unit 13H is performed as follows. FIGS. 14 to 17 show a state where the loop matching division is performed on the program 200 of FIG. The left part of FIGS. 14 to 17 shows each data localizable group obtained by performing the loop matching division, and the right part is a part accessed by each small loop constituting each data localizable group. An image is shown in which each of the typical array data is allocated on the cache.
[0119]
The three loops 203, 204, 205 included in the program 200 of FIG. 13 are each divided into four small loops as shown in FIGS. 14 to 17, and these four small loops form four data localizable groups. Is done.
[0120]
That is, for the loop 203 (j = 1 to 512) in FIG. 13, as shown in FIGS. 14 to 17, a small loop 203A (j = 1 to 128) and a small loop 203B (j = 129 to 256) , A small loop 203C (j = 257 to 384) and a small loop 203D (j = 385 to 512). As for the loop 204 (j = 1 to 512) in FIG. 13, as shown in FIGS. 14 to 17, the small loop 204A (j = 1 to 128), the small loop 204B (j = 129 to 256), It is divided into a loop 204C (j = 257 to 384) and a small loop 204D (j = 385 to 512). Regarding the loop 205 (j = 1 to 512) in FIG. 13, as shown in FIGS. 14 to 17, the small loop 205A (j = 1 to 128), the small loop 205B (j = 129 to 256), The loop is divided into a loop 205C (j = 257 to 384) and a small loop 205D (j = 385 to 512).
[0121]
As shown in FIG. 14, one small data loop localizable group (hereinafter, DLG20) is formed by three small loops 203A, 204A, and 205A. As shown in the lower right part of FIG. 14, partial array data (hatched portions in the figure) accessed by the small loops 203A, 204A, 205A constituting the DLG 20 are allocated to the same area on the cache. It can be seen that this causes a line conflict.
[0122]
As shown in FIG. 15, three small loops 203B, 204B, and 205B form one data localizable group (hereinafter, referred to as DLG21). As shown in the lower right part of FIG. 15, partial array data (shaded portions in the figure) accessed by the small loops 203B, 204B, and 205B constituting the DLG 21 are allocated to the same area on the cache. It can be seen that this causes a line conflict.
[0123]
As shown in FIG. 16, three small loops 203C, 204C, and 205C form one data localizable group (hereinafter, DLG22). As shown in the lower right part of FIG. 16, each partial array data (hatched portion in the figure) accessed by each of the small loops 203C, 204C, 205C constituting the DLG 22 is allocated to the same area on the cache. It can be seen that this causes a line conflict.
[0124]
As shown in FIG. 17, three small loops 203D, 204D, and 205D form one data localizable group (hereinafter, referred to as DLG23). As shown in the lower right part of FIG. 17, each partial array data (hatched portion in the figure) accessed by each of the small loops 203D, 204D, 205D constituting the DLG 23 is allocated to the same area on the cache. It can be seen that this causes a line conflict.
[0125]
Therefore, the size of the padding data is determined by the padding size determination unit 13K. Here, for a set of four array data (that is, about four megabytes in total), insertion of padding data having the same or substantially the same size as one partial array data (that is, about 256 kilobytes) Shall be performed.
[0126]
FIGS. 18 to 21 are explanatory diagrams showing a state in which padding is performed to avoid a line conflict when the DLG 20, DLG 21, DLG 22, or DLG 23 is executed. The right part of FIGS. 18 to 21 shows a state in which padding dummy data (shaded area in the drawing) is inserted behind each of the arrays E, K, and R by the data layout changing unit 13L. I have. Instead of inserting dummy data, padding may be performed by increasing the size of the arrays E, K, and R.
[0127]
18 to 21, partial array data (areas indicated by oblique lines in the drawings) accessed by the small loops constituting DLG20, DLG21, DLG22, and DLG23 are shown in the lower right part of FIGS. Are assigned without overlapping on the cache. Therefore, it can be seen that line conflict is avoided.
[0128]
When the program 100 of FIG. 4 described above is compiled, as shown in FIG. 11, the DLG 10, DLG 11, DLG 12, and DLG 13 are allocated to different processors 30, 31, 32, and 33, respectively, and are processed in parallel. As shown in FIG. 13, the scheduling for processing the DLG 10, DLG 11, DLG 12, and DLG 13 by one processor 30 in this order is performed. Similarly, when the program 200 of FIG. 13 is compiled, the DLG 20, DLG 21 , DLG22, and DLG23 may be assigned to different processors 30, 31, 32, and 33, respectively, or scheduling may be performed such that one processor 30 processes the DLG20, DLG21, DLG22, and DLG23 in this order. Yuringu may be carried out.
[0129]
In FIGS. 18 to 21, padding is performed by inserting padding dummy data (shaded area in the figure) behind each of the arrays E, K, and R. However, the last array may be omitted.) The array size of the non-contiguous access dimension may be increased for each array, or dummy data may be added to the rear of each array (however, the last array may be omitted). Padding may be performed by insertion.
[0130]
FIG. 22 shows a state in which the array size of the discontinuous access dimension is expanded and padding is performed for each array. The left part of FIG. 22 shows a state in which a line conflict occurs before padding, and the right part shows a state in which the occurrence of a line conflict after padding is avoided.
[0131]
In FIG. 22, before padding, the constant size setting unit 201 in the program 200 (see FIG. 13) specifies that the first dimension array size is N1 = 513 and the second dimension array size is N2 = 513. However, the array size N2 of the second dimension, which is a discontinuous access dimension, is increased from 513 to 544 by the data layout changing unit 13L, and N2 is set to 544 after padding. Therefore, for each of the 13 arrays U, V, T, E, F, G, H, K, N, P, Q, R, and S, an array of (544-513) .times.513.times.4 = approximately 64 kilobytes. The size is increased. If this is summed up for the four arrays, it will be about 64 kilobytes x 4 = about 256 kilobytes, which is compared to the case of padding a set of four arrays as shown in Figs. , The padding amount will be the same. The size of the last array S does not need to be increased. In the example of FIG. 22, padding is performed by increasing the array size of the non-contiguous access dimension for each array. However, padding is performed by inserting dummy data behind each array. Is also good.
[0132]
According to this embodiment, the following effects can be obtained. That is, when compiling by the compiling apparatus 10, after performing loop matching division on a plurality of data-dependent loops included in the source program 1, each small loop belonging to the same data localizable group can be connected. In addition to performing scheduling as long as possible and using padding to change the layout of array data used in each data localizable group, it is used by each small loop after matching division belonging to the same data localizable group. A plurality of partial array data can be allocated on the cache without overlapping (see the right part of FIGS. 7 to 10, 18 to 21, and 22). Therefore, the occurrence of a cache line conflict can be suppressed, so that the processing speed of the cache optimal use arithmetic unit 20 can be improved.
[0133]
Further, the cache optimum use arithmetic unit 20 is a multiprocessor machine with a shared main memory, but when compiling a program executed by such a machine having a plurality of processors by the compiling device 10, the same data is used. Since the small loops belonging to the localizable group perform scheduling that is continuously executed on the same processor as much as possible, the loop processing performed in each data localizable group is distributed to a plurality of processors. be able to. For example, as shown in FIG. 11, each process of DLG10, DLG11, DLG12, and DLG13 can be assigned to different processors 30, 31, 32, and 33, respectively. For this reason, the parallel processing of the loop processing of the DLG 10, DLG 11, DLG 12, and DLG 13 can be used to further improve the processing speed of the cache optimal use arithmetic unit 20.
[0134]
It should be noted that the present invention is not limited to the above embodiment, and modifications and the like within a range that can achieve the object of the present invention are included in the present invention.
[0135]
That is, in the above-described embodiment, the cache optimal use operation device 20 is a multiprocessor machine with a shared main storage. However, the present invention can be applied not only to a multiprocessor machine but also to a single processor machine.
[0136]
In the above embodiment, as shown in FIG. 3, the scheduling process (step S7) is performed before the padding size determination process (step S8) and the data layout change process (step S9). However, the order of these processes may be reversed.
[0137]
Further, in the above embodiment, the cache optimization is performed for the L2 caches 50 to 53 (the cache size is, for example, 4 megabytes). However, the present invention provides a cache optimization for the L1 caches 70 to 73. Can also be performed.
[0138]
【The invention's effect】
As described above, according to the present invention, after performing loop matching division on a plurality of loops having data dependence included in a source program, each small loop belonging to the same data localizable group is In addition to performing scheduling for continuous execution, since the layout is changed for the array data used in each data localizable group using padding, a plurality of data used by each small loop after the matching division belonging to the same data localizable group is used. Can be allocated without overlapping on the cache, and the processing speed can be improved by suppressing the occurrence of cache line conflict.
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram of a compiling device and a cache optimal use operation device according to an embodiment of the present invention.
FIG. 2 is a configuration diagram functionally showing the compiling device of the embodiment.
FIG. 3 is an exemplary flowchart showing the flow of a compile process by the compile device of the embodiment.
FIG. 4 is a view showing an example of a program to be compiled in the embodiment and an image when target array data used in a cache optimization target loop included in the program is allocated to a cache;
FIG. 5 is a view showing a state when a loop matching division is performed on a cache optimization target loop included in a program to be compiled in the embodiment.
FIG. 6 is an explanatory diagram of a line conflict occurring at the time of execution of a data localizable group (DLG10) obtained by the loop matching division of the embodiment and a padding amount for avoiding the line conflict.
FIG. 7 is an explanatory diagram of a state in which padding is performed to avoid a line conflict when a data localizable group (DLG10) is executed in the embodiment.
FIG. 8 is an explanatory diagram of a state in which padding is performed to avoid a line conflict when executing a data localizable group (DLG11) in the embodiment.
FIG. 9 is an explanatory diagram of a state in which padding is performed to avoid a line conflict when a data localizable group (DLG12) is executed in the embodiment.
FIG. 10 is an explanatory diagram of a state in which padding is performed to avoid a line conflict when a data localizable group (DLG13) is executed in the embodiment.
FIG. 11 is a diagram showing an execution image when scheduling for allocating different data localizable groups to a plurality of processors is performed in the embodiment.
FIG. 12 is a diagram showing an execution image when scheduling for allocating all data localizable groups to one processor is performed in the embodiment.
FIG. 13 is a view showing another example of a program to be compiled according to the embodiment and an image when target array data used in a cache optimization target loop included in the program is allocated to a cache;
FIG. 14 is a diagram showing a data localizable group (DLG20) obtained by performing loop matching division and partial array data accessed by each small loop constituting the DLG20 in the cache in the embodiment; The figure which shows the image of the state allocated.
FIG. 15 is a diagram showing a data localizable group (DLG21) obtained by performing loop matching division and partial array data accessed by each small loop constituting the DLG21 in the cache in the embodiment. The figure which shows the image of the state allocated.
FIG. 16 is a diagram showing a data localizable group (DLG22) obtained by performing loop matching division and partial array data accessed by each small loop constituting the DLG22 in the cache in the embodiment; The figure which shows the image of the state allocated.
FIG. 17 is a diagram showing a data localizable group (DLG23) obtained by performing loop matching division and partial array data accessed by each small loop constituting the DLG23 in the cache in the embodiment. The figure which shows the image of the state allocated.
FIG. 18 is an explanatory diagram of a state in which padding is performed to prevent a line conflict when executing a data localizable group (DLG20) in the embodiment.
FIG. 19 is an explanatory diagram of a state in which padding is performed to avoid a line conflict when a data localizable group (DLG21) is executed in the embodiment.
FIG. 20 is an explanatory diagram of a state in which padding is performed to avoid a line conflict when executing a data localizable group (DLG22) in the embodiment.
FIG. 21 is an explanatory diagram of a state in which padding is performed to avoid a line conflict when a data localizable group (DLG23) is executed in the embodiment.
FIG. 22 shows a state in which a line conflict occurs before padding and a state in which the occurrence of a line conflict is avoided by performing padding by expanding the array size of the discontinuous access dimension in each array in the embodiment. FIG.
[Explanation of symbols]
1 Source program
2 Purpose program
3 programs
10 Compiling device
13A Macro task generation means
13B Parallelism analysis means
13C Target loop group selection means
13D target loop group storage means
13E Target sequence data selection means
13F Target array data storage means
13G division number determination means
13H Loop matching division means
13J scheduling means
13K padding size determination means
13L data layout changing means
14 Target loop group table
15 Target array data table
20 Cache optimal use arithmetic unit
30-33 processor
40 main memory
50-53 L2 cache which is a cache memory
102, 103, 203, 204, 205 loop
102A, 102B, 102C, 102D, 103A, 103B, 103C, 103D, 203A, 203B, 203C, 203D, 204A, 204B, 204C, 204D, 205A, 205B, 205C, 205D Small loop
DLG10, DLG11, DLG12, DLG13, DLG20, DLG21, DLG22, DLG23 Data Localizable Group
TLG1, TLG2 Target loop group
A, B, C, D, E, F, G, H, K, N, P, Q, R, S, T, U, V arrays

Claims (14)

A compiling method for compiling a source program to generate a target program,
A plurality of small loops each having a data dependence included in the source program are divided to generate a plurality of small loops for each of the loops, and a small loop using the same partial array data among these small loops A plurality of data localizable groups are formed by aggregating each other, and in this division / grouping process, partial arrays used by the small loops belonging to the data localizable groups, respectively. Performing consistent division so that the total size of the data falls within the size of the cache memory for each of the data localizable groups,
Thereafter, the same data is set within a range that satisfies the earliest executable condition including the execution determination condition for determining the execution of each of the small loops and the data access condition for enabling data necessary for the execution of each of the small loops. Each of the small loops belonging to the localizable group performs scheduling that is executed as continuously as possible,
A data layout using padding for each of the array data so that the partial array data used by each of the small loops belonging to each of the data localizable groups do not overlap on the cache memory. A compilation method characterized by making a change. 2. The compiling method according to claim 1, wherein
When performing scheduling for a multiprocessor to perform parallel processing using a plurality of processors,
Compiling wherein the small loops belonging to the same data localizable group are continuously executed on the same processor as much as possible within a range satisfying the earliest executable condition. Method. 3. The compiling method according to claim 1, wherein
The compiling method according to claim 1, wherein the padding is an area secured by data different from an array used by each of the small loops belonging to each of the data localizable groups. 3. The compiling method according to claim 1, wherein
The padding is an area secured by enlarging the size of at least one array among the arrays used by each of the small loops belonging to each of the data localizable groups in a non-contiguous access dimension. How to compile. 5. The compiling method according to claim 4, wherein
The compilation is characterized in that the padding is an area in which the size of an array used by each of the small loops belonging to each of the data localizable groups is expanded and secured for a non-contiguous access dimension for each array. Method. A compiler that performs compilation using the compilation method according to claim 1. A compiler that compiles a source program to generate a target program,
Macrotask generating means for generating a plurality of macrotasks by dividing the source program into blocks;
Parallelism analysis means for analyzing an execution determination condition for determining execution of each macrotask and an earliest execution condition including a data access condition for enabling data necessary for execution of each macrotask to be usable;
From among the loops having data dependence included in the source program as the respective macro tasks, a plurality of loops that can be subjected to loop matching division for effectively using a cache memory are set as target loop groups for cache optimization. Target loop group selecting means to select as
Target loop group storage means for storing the target loop group selected by the target loop group selection means in a target loop group table;
Target array data selecting means for selecting each array data used by each of the plurality of loops constituting the target loop group as target array data for cache optimization,
Target sequence data storage means for storing the target sequence data selected by the target sequence data selection means in a target sequence data table;
Division number determining means for determining a division number of the plurality of loops constituting the target loop group based on a total size of the respective target array data and a size of the cache memory;
On the basis of the division number determined by the division number determination means, the plurality of loops constituting the target loop group stored in the target loop group table are respectively divided to generate a plurality of small loops for each of the loops And a loop matching division unit that aggregates small loops using the same partial target sequence data among these small loops to form a plurality of data localizable groups,
The same data localizable as long as it satisfies the earliest executable condition including an execution determination condition for determining execution of each of the small loops and a data access condition for enabling data necessary for the execution of each of the small loops. A scheduling means for performing scheduling in which the small loops belonging to a group are executed as continuously as possible;
The storage position of each of the target array data in the main memory so that the partial target array data used by each of the small loops belonging to each of the data localizable groups do not overlap on the cache memory. Padding size determining means for determining the size of padding data to be inserted to shift
A data layout using padding by inserting padding data corresponding to the size determined by the padding size determining means inside the target array data stored in the target array data table or between the target array data. As a data layout change means for making changes,
A compiler that causes a computer to function. A compiling device for compiling a source program to generate a target program,
Macrotask generating means for generating a plurality of macrotasks by dividing the source program into blocks;
Parallelism analysis means for analyzing an execution determination condition for determining execution of each macrotask and an earliest execution condition including a data access condition for enabling data necessary for execution of each macrotask to be usable;
From among the loops having data dependence included in the source program as the respective macro tasks, a plurality of loops that can be subjected to loop matching division for effectively using a cache memory are set as target loop groups for cache optimization. Target loop group selecting means to select as
A target loop group table storing the target loop group selected by the target loop group selection means,
Target array data selecting means for selecting each array data used by each of the plurality of loops constituting the target loop group as target array data for cache optimization,
A target sequence data table storing the target sequence data selected by the target sequence data selecting means,
Division number determining means for determining a division number of the plurality of loops constituting the target loop group based on a total size of the respective target array data and a size of the cache memory;
On the basis of the division number determined by the division number determination means, the plurality of loops constituting the target loop group stored in the target loop group table are respectively divided to generate a plurality of small loops for each of the loops And a loop matching division unit that aggregates small loops using the same partial target sequence data among these small loops to form a plurality of data localizable groups,
The same data localizable as long as it satisfies the earliest executable condition including an execution determination condition for determining execution of each of the small loops and a data access condition for enabling data necessary for the execution of each of the small loops. A scheduling means for performing scheduling in which the small loops belonging to a group are executed as continuously as possible;
The storage position of each of the target array data in the main memory so that the partial target array data used by each of the small loops belonging to each of the data localizable groups do not overlap on the cache memory. Padding size determining means for determining the size of padding data to be inserted to shift
A data layout using padding by inserting padding data corresponding to the size determined by the padding size determining means into the target array data stored in the target array data table or between the target array data. A compiling device comprising: a data layout changing means for performing a change. A program code creating method for creating code constituting a program,
A plurality of loops each having a data dependency to be executed are divided, and a plurality of small loops are created for each of the loops. Of these small loops, small loops using the same partial array data are separated from each other. Collectively form a plurality of data localizable groups, and at the time of this division / grouping work, partial array data of partial array data respectively used by the small loops belonging to the data localizable groups. Performing consistent division so that the total size falls within the size of the cache memory for each of the data localizable groups,
Thereafter, the same data is satisfied within a range that satisfies the earliest executable condition including the execution determination condition for determining the execution of each of the small loops and the data access condition in which data necessary for the execution of each of the small loops becomes available. Each of the small loops belonging to the localizable group performs scheduling so as to be executed as continuously as possible,
Laying out each of the array data using padding so that the partial array data used by each of the small loops belonging to each of the data localizable groups do not overlap on the cache memory. Characteristic program code creation method. 10. The method according to claim 9, wherein:
When performing scheduling for a multiprocessor to perform parallel processing using a plurality of processors,
Within the range that satisfies the earliest executable condition, scheduling is performed such that the small loops belonging to the same data localizable group are continuously executed on the same processor as much as possible. How to create program code. A program created or created by using the compiling method according to any one of claims 1 to 5 or the program code creating method according to any one of claims 9 and 10. A program generated by the compiler according to claim 6. Using an arithmetic unit including a processor, a main memory, and a cache memory provided therebetween,
13. A method for optimally using a cache, wherein the program according to claim 11 or 12 is executed to perform arithmetic processing using the cache memory while suppressing occurrence of a cache line conflict miss. A processor, a main memory, and a cache memory provided therebetween;
The program according to claim 11 or 12, wherein the program is executed to execute arithmetic processing using the cache memory while suppressing occurrence of a cache line conflict miss. Characteristic cache optimal use arithmetic unit.

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