JP2004250263A - High-quality wafer and its manufacture method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon wafer which, when annealed, reduces in the density of defects on its surface layer and uniformly and sufficiently forms a BMD in the surface and to provide its manufacture method. <P>SOLUTION: There are provided a wafer characterized in that the oxygen concentration is at least 24 ppma, the entire exists in a crystal originated particle (COP) formation region, the size of a COP is 0.1 to below 0.15 μm on the average, the existence density of bulk microdefects (BMD) formed inside is at least 2.5×10<SP>8</SP>defects/cm<SP>3</SP>, and the density distribution in the radial direction is at most 4 in terms of a maximum/minimum ratio; a wafer obtained by annealing the above wafer; a wafer manufacture method characterized in that G<SB>c</SB>is at least 3.0 in the range of the melting point to 1,000°C, the G<SB>c</SB>/G<SB>s</SB>ratio is at least 1.0 in the range of the melting point to 1,300°C, and the V/G<SB>c</SB>ratio is 0.17 to 0.25 (mm<SP>2</SP>/[°C×min]) (wherein V is the pulling speed; G<SB>c</SB>is the temperature gradient in the direction of the axis of pulling at the center; and G<SB>s</SB>is that temperature gradient at the periphery); and a wafer manufacturing method comprising heating for 0.5 to 6 hr at 1,100-1,250°C in a non-oxidizing and non-nitriding atmosphere. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【００７０】
次に、表１に示した６種の試験材それぞれから得たウェーハにて、育成のまま、高純度アルゴン中にて１２００℃、１時間加熱のアニール処理、および同じく１１５０℃、１時間のアニール処理の３種のウェーハを作製した。
【００７１】
得られた各ウェーハにて、光散乱による表層部欠陥測定装置（三井金属工業社製ＭＯ６０１）を用いて、表面における大きさが０．１μｍを超えるＣＯＰ欠陥の密度を測定した。さらに、それぞれの条件ごとに５枚ずつウェーハを用意し、その酸化膜耐圧特性を以下の条件で測定した。
（ａ）酸化膜厚：２５ｎｍ
（ｂ）電極面積：８ｍｍ^２
（ｃ）測定電極：リンドープ・ポリシリコン
（ｄ）判定電流：１ ｍＡ／ｃｍ^２
（ｅ）良品判定：絶縁破壊電界が１１ ＭＶ／ｃｍ以上
また、アニール処理後のウェーハ内部ＢＭＤの状況を見るため、上記の１２００℃アニール処理後のウェーハにて、１０００℃、１６時間の加熱処理をおこなった後、破面にて２μｍのライトエッチングを施してその密度を測定した。これらの結果を表２に示す。さらに、試験材番号２のウェーハについて、１１５０℃のアニール処理および１０００℃、１６時間のＢＭＤ発生加熱処理をおこなったときの、径方向における表面無欠陥層の深さ分布および内部のＢＭＤ密度の分布を調べた結果を図５に示す。
【００７２】
【表２】

【００７３】
表１、図３および図４の、試験材番号１および２、あるいは３の結果からわかるように、本発明のウェーハは、ａｓ ｇｒｏｗｎ の状態においてＣＯＰ欠陥の大きさは小さいが、その密度が高く、そして発生する酸素析出物は、その密度が高く、かつウェーハ面内で均一に分布している。そして、このようなウェーハは、素材となる単結晶育成時に、冷却の温度勾配を大きくし、凝固直後では単結晶表面部よりも内部の方の温度勾配を大きくして、Ｖ／Ｇ_Ｃを特定範囲に制御し育成することにより製造できる。
【００７４】
表２に示された結果から、試験材１、２および３の本発明のウェーハは、 ａｓ ｇｒｏｗｎ の状態においては酸化膜耐圧特性の良品率はよくないが、アニール処理を施すことにより良品率が１００％近いウェーハとなることが明らかである。それに加えて、ウェーハ内部におけるＢＭＤ発生量が多く、位置によるばらつきも小さい。
【００７５】
これに対し、従来の方法で製造された試験材４、５および６のウェーハは、Ａｓ ｇｒｏｗｎの状態では、酸化膜耐圧特性が本発明のウェーハより良好であるが、アニール処理をおこなっても大きくは改善されない。その上、ＢＭＤの発生量が少なく、ばらつきが大きい。
【００７６】
さらに図５からわかるように、本発明のウェーハは、１１５０℃という低いアニール処理温度であるにもかかわらず、ウェーハ表面のＣＯＰ欠陥のほとんどない無欠陥層の厚さは１５μｍ以上形成されており、内部のＢＭＤの発生密度は少ない部位でも３５×１０^８個／ｃｍ^３以上ある。しかも多い位置でも６５×１０^８個／ｃｍ^３以下であり、密度分布は最大値／最小値比において２以下のすぐれた分布を示している。
【００７７】
【発明の効果】
本発明のシリコンウェーハは、非酸化非窒化雰囲気中での高温加熱によるアニールを施すことにより、表面層にＣＯＰ欠陥の極めて少ない無欠陥層を形成させることとができ、しかも内部にはゲッタリング作用のあるＢＭＤを十分多く、ウェーハ面内で均一に分布させることができる。このウェーハはその上に形成される集積回路の良品歩留まりを大きく向上させ、集積回路すなわちＩＣの製造コスト低減に大きく寄与する。
【００７８】
【図面の簡単な説明】
【図１】シリコンウェーハで観察される、典型的な欠陥分布の例を模式的に示した図である。
【図２】実施例に用いたシリコン単結晶の製造装置の断面を模式的に示した図である。
【図３】各ウェーハにおけるＣＯＰ欠陥の大きさとその存在密度を示した図である。
【図４】各ウェーハ内部に発生したＢＭＤの密度のウェーハ面内での分布を示す図である。
【図５】１１５０℃のアニール後、酸素析出処理をおこなったウェーハの面方向における、表面のＢＭＤ無欠陥層の厚さ分布、および内部のＢＭＤの密度分布を示す図である。
【符号の説明】
１． るつぼ
２． シリコン溶融液
３． ヒーター
４． 単結晶
５． 熱遮蔽材
６． 冷却材[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a silicon wafer used as a semiconductor material, particularly to a silicon wafer having a defect-free layer formed on a surface of the wafer by high-temperature heat treatment (annealing treatment) and a method of manufacturing the same.
[0002]
[Prior art]
A silicon wafer of a semiconductor material is cut out of a silicon single crystal, and the most widely used method for producing the silicon single crystal is a single crystal pulling and growing method by a Czochralski method (CZ method).
[0003]
In the CZ method, a seed crystal is immersed in molten silicon in a quartz crucible and pulled up to grow a single crystal. Due to the progress of the silicon single crystal pulling and growing technique, a large number of dislocation-free large single crystals has been developed. Crystals are being manufactured. However, as the circuit density of the device has become higher and smaller, defects that have not been a problem in the past have a great influence on the performance of the device, and fine defects formed during crystal growth, that is, grown-in defects, Various studies have been made to reduce and eliminate as much as possible.
[0004]
A typical distribution of the grown-in defects is observed, for example, as shown in FIG. This is a diagram schematically showing a result obtained by cutting a wafer from a single crystal immediately after growth, immersing the wafer in an aqueous copper nitrate solution to attach Cu, and after heat treatment, observing the distribution of minute defects by X-ray topography. . This figure shows an example of a wafer in which an OSF (Oxidation induced Stacking Fault: Oxidation induced Stacking Fault) distributed in a ring shape appears in the vicinity of half of the wafer diameter. Defects with a size of about 10 μm³-10⁴Pieces / cm³In the inner part, there is an infrared scatterer having a size of about 0.2 μm or less, or a defect called COP (Crystal Originated Particle).⁵-10⁶Pieces / cm³Degree is detected.
[0005]
OSF is a stacking fault caused by interstitial atoms generated during oxidation heat treatment, and when generated and grown on a wafer surface which is an active region of a device, causes a leak current and deteriorates device characteristics. In the dislocation cluster, a device formed in a portion where the dislocation cluster exists becomes an operationally defective product, and when a COP is present, the initial breakdown voltage characteristics of the oxide film are reduced.
[0006]
If the pulling speed at the time of growing a single crystal is reduced, the ring-shaped OSF becomes small, and only a region where dislocation clusters are likely to be generated eventually. If the pulling speed is increased, the ring-shaped OSF moves to the outer peripheral position of the wafer. As a result, an area where COP is likely to be generated in the center is enlarged. Conventionally, from the viewpoint of the large influence of the occurrence of defects due to dislocation clusters and the productivity, wafers with a ring-shaped OSF positioned near the outer periphery, where the pulling speed is increased within a range where a sound single crystal can be obtained, are often used. Have been.
[0007]
However, due to the increasing demand for wafers with fewer grown-in defects, various countermeasures have been studied. When observing the wafer shown in FIG. 1 in detail, there is an oxygen precipitation promoting region where oxygen precipitation is likely to occur immediately outside the ring-shaped OSF, and there is a substantially defect-free region outside the region. It is a cluster defect generation area. In addition, there is a region inside the ring-shaped OSF generation region where the COP generation density is extremely low. The distribution of these ring-shaped OSF generation regions and the respective regions in the vicinity thereof changes depending on the temperature distribution in the single crystal immediately after the pulling and the pulling speed.
[0008]
Therefore, various single crystal growing techniques and processing methods have been developed to obtain a defect-free wafer in which a portion where generation of such a grown-in defect is extremely small is enlarged over the entire surface.
[0009]
For example, in the invention disclosed in Patent Document 1, the pulling speed at the time of growing a single crystal is V (mm / min), and the temperature gradient in the pulling axis direction in the temperature range from the melting point to 1300 ° C. is G (° C./mm). ), V / G is set to 0.20 to 0.22 (mm²/ [° C. · min]), and the temperature gradient is controlled by improving the components placed around the single crystal to be pulled, that is, the hot zone, so as to gradually increase the temperature toward the outer periphery of the crystal. When the growth rate is adjusted by adjusting the pulling speed of the hot zone in this manner, only the oxygen precipitation promoting region outside the ring-shaped OSF and the defect-free region of the oxygen precipitation suppressing region are formed without generating OSF and dislocation cluster. , Spread over the entire surface of the wafer.
[0010]
The inventions disclosed in Patent Literature 2 and Patent Literature 3 set the oxygen concentration to less than 24 ppma (old ASTM) so that the ring-shaped OSF does not become apparent, and further reduce the V / G to 0.112 to 0.142 (mm).²/ [° C. · min]) to manufacture a wafer including a region including not only the outer portion of the ring-shaped OSF but also the inner portion where no COP is generated.
[0011]
Further, in order to more stably expand the defect-free region, a hot zone structure is provided in which the temperature gradient G in the crystal in the pulling axis direction of the single crystal to be grown is larger in the central portion than in the outer peripheral surface portion. An apparatus invention is disclosed in Patent Document 4. This device surrounds the periphery of the single crystal being pulled up, and has a heat shielding material having a cooling member whose inner peripheral surface is coaxial with the pulling axis and an outer surface of the cooling member and a lower side of the lower end surface. Are provided. By controlling the distance from the single crystal surface and the distance from the melt surface of the component combining the cooling member and the heat shielding material, the single crystal surface at a temperature close to the melting point immediately after solidification below the single crystal is The temperature is maintained by the radiation from the melt surface or the inner surface of the crucible, and the portion facing the cooling member above is forcibly cooled to realize the above-described temperature gradient or temperature distribution.
[0012]
The method of expanding the defect-free region generated during the growth of such a single crystal over the entire surface of the wafer by controlling the temperature distribution and the pulling speed in the single crystal immediately after solidification is limited by an increase in the pulling speed of the single crystal. In addition, stable implementation is difficult for large diameter wafers, and application to mass production is not easy.
[0013]
It is essential for the wafer to have as few defects as possible on the surface layer where the integrated circuits are formed, but the substrate below the integrated circuit formation area must be contaminated with heavy metals and other unavoidable parts during the manufacturing process. On the other hand, it is also important to have a gettering effect. This internal gettering effect is caused by a defect called BMD (Bulk Micro Defect) in the wafer, and oxygen precipitates generated in the COP generation region are one of them.
[0014]
Although the above-described wafer can reduce defects harmful to the formation of an integrated circuit, the number of defects inside the wafer may be reduced or the distribution may be non-uniform, and effective BMD may not be sufficiently or uniformly formed.
[0015]
On the other hand, there has been proposed a method in which a single crystal is produced under conditions of a COP generation region, and the obtained wafer is annealed to reduce defects in a surface layer for forming an integrated circuit. In this case, it is necessary to separately anneal the wafer, but it is possible to grow a single crystal under a condition of a high pulling rate, and a hole serving as a source of COP acts inside the wafer to form a BMD. There is an advantage.
[0016]
For example, in Patent Document 5, an oxygen concentration of 4 × 10¹⁷Atom / cm³As described above, the size of COP defects is reduced and distributed by rapidly cooling the passage time in the temperature range between 1100 to 850 ° C. during pulling of the single crystal to less than 80 minutes, and annealing at 1000 ° C. or more and 1 hour or more is performed. An invention of a wafer manufacturing method for reducing defects by processing is disclosed. This is because when the size of the COP defect is reduced, defects near the wafer surface can be easily reduced by annealing. Also, instead of the rapid cooling between 1100 ° C and 850 ° C, 1 × 10¹⁴Atom / cm³It is stated that a similar effect can be obtained by doping with nitrogen.
[0017]
Further, Patent Document 6 discloses that a nitrogen concentration of 10^ThirteenAtom / cm³As described above, the cooling time from 1200 ° C. to 1000 ° C. was set to 200 minutes or less, and the ring-shaped OSF was pulled up to a diameter of 0.8 or less of the outer diameter of the single crystal, and was collected from the obtained single crystal. An invention of a method of manufacturing a wafer for a substrate, in which a wafer is annealed at 1000 to 1350 ° C. in an atmosphere containing hydrogen or argon, has been proposed.
In the invention disclosed in Patent Document 7, the oxygen concentration is set to 25 ppma or more, and the temperature gradient in the vertical direction of the single crystal to be pulled is G at the center._C, G on the surface_SIn the temperature range from the melting point to 1370 ° C., G_CIs 2.8 ° C / mm or more and G_C/ G_SIs raised to 1 or more so that the entire surface of the wafer becomes a COP generation region. Thus, the average density of COP defects is 0.1 μm or less, and the density of defects exceeding 0.1 μm is 10 μm.⁵Pieces / cm³The following single crystal is obtained, and it is stated that a wafer obtained from this single crystal easily forms a defect-free layer on the surface by annealing, and also generates BMD.
[0018]
As described above, various studies have been made to obtain a wafer in which a BMD having an extremely effective gettering effect exists inside a surface layer portion where an integrated circuit is formed and has very few defects. . However, it is difficult to say that a wafer capable of easily realizing a defect-free state of the surface layer and having BMDs sufficiently and uniformly present on the entire surface is obtained.
[0019]
[Patent Document 1]
JP-A-8-330316
[Patent Document 2]
JP-A-11-147786
[Patent Document 3]
JP-A-11-157996
[Patent Document 4]
JP 2001-220289 A
[Patent Document 5]
JP-A-10-98047
[Patent Document 6]
JP 2001-240490 A
[Patent Document 7]
JP-A-2002-187794
[0020]
[Problems to be solved by the invention]
An object of the present invention is to anneal in a non-oxidizing and non-nitriding gas such as an inert gas or hydrogen so that the defect density of the surface layer becomes extremely low and the BMD is formed uniformly and sufficiently in the plane. An object of the present invention is to provide a wafer and a manufacturing method thereof.
[0021]
[Means for Solving the Problems]
On silicon wafers on which integrated circuits are formed, there are very few defects in the circuit formation area near the surface, and there must be defects inside to obtain the gettering effect. Required. The present inventors have proposed a method of manufacturing a wafer having such characteristics as a method of eliminating defects on a surface portion by a relatively simple heat treatment and forming a BMD having a gettering effect therein. Considering this as desirable, a method for producing a wafer suitable for it or a single crystal for obtaining the wafer was studied.
[0022]
As a heat treatment method for reducing defects in a circuit formation portion on the surface, there is an annealing method in which heating is performed at 1000 ° C. or more for one hour or more in a non-oxidizing non-nitriding atmosphere such as hydrogen or argon. In this method, since the dislocation clusters cannot be eliminated, a wafer having the ring-shaped OSF shown in FIG. 1 near the outer periphery and occupying most of the COP defect generation region is used.
[0023]
When performing this annealing, the smaller the size of the COP defect, the more easily it can be eliminated. There is a method of doping with nitrogen in order to reduce the size of the COP defects to a small value. However, as a result of the investigation, it has been found that nitrogen doping has various practical problems even though it can disperse COP defects to a small extent. For example, oxygen precipitate defects caused by nitrogen may not easily disappear when annealing is performed and may remain as defects on the surface layer, and segregation of nitrogen in the pulling axis direction is large, which is caused by this. Possible uneven distribution of BMD is likely to occur, and furthermore, in the radial direction, the in-plane distribution of BMD becomes uneven due to the spread of the ring-shaped OSF.
[0024]
Therefore, regarding the possibility of finely and uniformly dispersing the COP defects without nitrogen doping, the influence of the temperature distribution in the single crystal at the time of pulling the single crystal and the pulling speed was determined. Here, the size and distribution density of the COP defect were examined on the polished wafer surface using an OPP device (Oxgen Precipitate Profiler, manufactured by Bio-Rad).
[0025]
The formation of integrated circuits requires a defect-free layer of 10 microns or more in thickness on the wafer surface. Investigation into the relationship between the COP defects generated in a single crystal wafer without nitrogen doping and the state of formation of a defect-free layer on the surface by annealing in high-purity argon gas shows that the wafer is grown as is (as grown). The size of a defect that can be detected in a single crystal wafer has a small average diameter and does not exceed a specific size, thereby facilitating the formation of a defect-free layer by annealing and eliminating residual defects in the layer. It was confirmed to be important.
[0026]
In order to realize a wafer having a favorable state of dispersion of COP defects for forming a defect-free layer on the surface by annealing, various investigations were made on single crystal pulling conditions. It has been found that it is necessary to increase the gradient G and, at the same time, control the lifting speed V to keep V / G within a certain range.
[0027]
The reason why the COP defect distribution and the BMD distribution are improved by increasing the temperature gradient G is considered as follows. First, in the temperature range from the melting point to the vicinity of 1300 ° C., the large temperature gradient G reduces the concentration of vacancies taken in at the time of solidification to reduce COP defects, and the cooling in the temperature range from 1300 ° C. to about 1150 ° C. This has the effect of suppressing the diffusion and extinction of holes to the crystal surface, thereby making the distribution of holes in the wafer uniform. Next, in a temperature range of about 1150 ° C. to 1000 ° C., the pores aggregate and coalesce to form a COP defect. However, if G is also increased here, the growth of the COP defect is suppressed by rapid cooling. , Can be fine. It is presumed that such miniaturization of COP defects is also effective in making the distribution of BMD in the wafer uniform.
[0028]
Further, even in the temperature range of about 1000 ° C. to 800 ° C., if G was increased and cooled, it was effective for uniform dispersion of finer BMD. This was considered to suppress the generation of BMD which is a nucleus of the ring-shaped OSF generated in the vicinity of the outer periphery, thereby suppressing the non-uniformity of the BMD.
[0029]
When G is increased in this manner, unless the pulling speed V is increased accordingly, most of the wafer cannot be brought into a COP defect generation region. However, V is limited in order to obtain a sound single crystal such as suppression of polycrystallization, and therefore, it is necessary to control V / G to a specific range. If V / G is too large, a COP defect having a large diameter tends to occur.
[0030]
However, it has been found that there is a limit to improving the density distribution of COP defects on the wafer surface only by increasing the conditions for increasing G and controlling V / G to a specific range. Even though the diameter of the COP defect can be reduced to facilitate the development of a defect-free layer on the surface, the density of the BMD, which is presumed to be caused by vacancies that cause the COP defect generated inside, is reduced. This is not uniform in the direction, and a sufficient wafer for the substrate is not necessarily obtained.
[0031]
BMD is considered to be mainly an oxygen precipitate, but the oxygen precipitate is hardly recognized as it is grown, and is formed by heat treatment in the process of forming an integrated circuit on the wafer. The heat treatment for forming the oxygen precipitate varies depending on the integrated circuit on the wafer, but here, as a typical oxygen precipitation heat treatment, is heated in air at 900 ° C. for 4 hours, and then heated at 1000 ° C. for 16 hours. The conditions were applied. In this case, a light etching of 2 μm in thickness is performed on the wafer cross section after the heat treatment, the volume density is determined from the detected area density of the precipitate, the distribution change in the radial direction of the wafer is investigated, and the BMD density and Distribution.
[0032]
It is considered that COP defects are formed by the coalescence of vacancies in the solidified silicon crystal. These vacancies act on the precipitation nuclei of oxygen dissolved in the single crystal, which grow into oxygen precipitates. Is estimated to be BMD. Therefore, it is considered that the more uniformly the vacancies or COP defects are distributed in the as-grown single crystal wafer surface, the more uniform the distribution of BMD.
[0033]
Therefore, the production conditions of a single crystal in which COP defects are distributed as uniformly as possible in the wafer plane were further studied so that the ratio of the maximum value / minimum value of the oxygen precipitate density in the wafer radial direction was reduced. As a result, as the temperature distribution inside the single crystal immediately after solidification, the temperature gradient at the center of the single crystal in the pulling axis direction is represented by G_C, The temperature gradient at the outer periphery_SAnd G_C/ G_SIt was found that it was better to raise the ratio by setting the ratio to more than 1.0.
[0034]
This G_C/ G_SHas been conventionally studied as a single crystal pulling method for making the entire surface of the wafer a defect-free region in the vicinity of the ring-shaped OSF. For example, as shown in Patent Document 4, A device with a devised structure has been published. On the other hand, if a single crystal is manufactured by using a device having a similar hot zone so that the COP defect generation region is almost entirely over the wafer surface, the distribution of COP defects can be made uniform, and thereby the BMD can be reduced over the entire wafer surface. It was found that they can be generated uniformly.
[0035]
G_C/ G_SMay be realized in a temperature range from immediately after solidification to 1300 ° C. where vacancies and interstitial Si in a single crystal actively move. Thus, G_C/ G_SThe reason why the ratio is more than 1.0 is effective for the uniform distribution of the COP defects is considered as follows.
[0036]
In the growth of a single crystal, a large amount of vacancies and interstitial silicon atoms are incorporated into the solid single crystal during the solidification of the liquid phase. Immediately after solidification, the amount of vacancy is larger in the vacancies than in the interstitial silicon atoms, but diffusion in the direction of the pulling axis from the solid-liquid interface into the crystal also occurs simultaneously due to the temperature gradient. The amount of inflow due to this diffusion is larger for interstitial silicon atoms than for vacancies, and the difference increases as the pulling speed decreases. Vacancies and interstitial silicon that diffuse in a high-temperature single crystal shortly after solidification often disappear in pairs when colliding, and the number rapidly decreases, but the pulling speed increases. When it is slow, defects such as dislocation clusters appear due to the remaining interstitial silicon atoms, and when the pulling speed is fast, many COP defects and oxygen precipitates exist due to the remaining vacancies.
[0037]
Under normal conditions for growing a single crystal, the temperature is lower at the outer periphery than at the center, and the temperature gradient in the pulling axis direction is greater at the outer periphery than at the center. The amount of movement of interstitial silicon atoms by diffusion tends to be proportional to the temperature gradient when the pulling speed is the same, and in this case, the inflow of interstitial silicon atoms is larger at the outer peripheral portion. On the other hand, the vacancies are taken in by the same amount at any position from the solid-liquid interface, and almost immediately exist in the radial direction of the single crystal immediately after solidification, but disappear on the outer peripheral surface, so that the outer peripheral side gradually disappears. The concentration decreases. In such a state, the combined disappearance of the voids and the interstitial silicon proceeds, so that the voids have a non-uniform distribution in the radial direction, and as a result, the wafer has a non-uniform BMD distribution.
[0038]
On the other hand, if a state in which the temperature is higher at the outer peripheral surface than at the central part of the single crystal appears, G_C/ G_SIs more than 1.0. Then, since the temperature gradient in the pulling axis direction is larger at the center than at the outer periphery, the inflow of interstitial silicon atoms increases at the center. The amount of vacancies tends to be larger in the center than in the outer periphery due to diffusion in the outer peripheral direction. However, as the amount of interstitial silicon flowing in increases, many of the voids disappear, and as a result, vacancies increase. The in-plane distribution of the pore concentration is made uniform. As the cooling is performed, the vacancies coalesce to form COP defects or to become precipitation nuclei of BMD. Therefore, if the vacancies are uniformly distributed, the vacancies become uniform.
[0039]
As described above, in the single crystal portion solidified at the time of pulling, G is increased and G is increased._C/ G_SIf the pulling speed is increased so that the COP defect generation region is substantially the entire surface of the wafer, the OSF will not appear on the wafer. However, in this case, if the amount of oxygen is kept low, the amount of BMD tends to be insufficient. Therefore, oxygen needs to be contained in an amount large enough to generate BMD sufficiently.
[0040]
Based on the above study results, annealing in a non-oxidizing and non-nitriding atmosphere for forming a defect-free layer on the surface clearly reveals the limitations of a single crystal that can be obtained as an excellent wafer for a substrate and a manufacturing method thereof. Thus, the present invention has been completed. The gist of the present invention is as follows.
[0041]
(1) When the oxygen concentration is 24 ppma (old ASTM) or more, the size of COP defects observed on the surface is 0.1 μm or less on average and none exceeds 0.15 μm. The density of oxygen precipitates formed inside the wafer is 2.5 × 10⁸Pieces / cm³A silicon wafer, wherein the density distribution of oxygen precipitates in the radial direction of the wafer is 4 or less in a ratio of maximum value / minimum value.
[0042]
(2) When the oxygen concentration is 24 ppma (old ASTM) or more, the number of COP defects observed on the surface is 0.5 / cm.²An annealed wafer produced from the silicon wafer according to the above (1), wherein the following defect-free layer exists at a depth of 5 μm or more.
[0043]
(3) In the production of a silicon single crystal which is pulled and grown by the Czochralski method (CZ method), the single crystal pulling speed is V (mm / min), and the temperature gradient at the center of the single crystal in the pulling axis direction is G._C(° C./mm) and the temperature gradient at the outer_S(° C./mm), the center is G in the temperature range from the melting point to 1000 ° C._CIs 3.0 or more, and G is from the melting point to 1300 ° C._C/ G_SIs greater than 1.0 and V / G_CIs 0.17 to 0.25 (mm²/ [° C. · min]), wherein the silicon wafer is collected from a single crystal pulled up.
[0044]
(4) In the method for producing a silicon single crystal according to the above (3), if the temperature in the central portion is more than 1000 ° C. and up to 800 ° C., G_CIs raised to 2.5 or more.
[0045]
(5) The method is characterized in that the silicon wafer of (1) above is heated at a temperature of 1100 to 1250 ° C. for 0.5 to 6 hours in an atmosphere of hydrogen gas, argon gas or a mixture of these gases. A method for manufacturing an annealed wafer according to claim 2.
[0046]
BEST MODE FOR CARRYING OUT THE INVENTION
In the silicon wafer of the present invention, in growing a single crystal as a material, nitrogen doping is not performed, and the oxygen concentration is 24 ppma (old ASTM) or more. Although nitrogen doping can reduce the diameter of COP defects, segregation is remarkable and non-uniformity of concentration occurs in the crystal pulling axis direction. If the annealing temperature is not increased, oxygen promoted by nitrogen doping can be reduced. This is because undesired effects remain, such as the defects caused by the surface being hardly reduced on the surface.
[0047]
The reason why the oxygen concentration is set to 24 ppma or more is that if the oxygen concentration is less than 24 ppma, the amount of BMD formed inside the wafer becomes insufficient and the gettering effect may not be sufficiently obtained. However, if the content is too large, OSF may be generated or oxygen precipitates may be generated even in the integrated circuit forming portion on the surface. Therefore, the content is preferably at most 34 ppma or less.
[0048]
The portion of the body from which a single-crystal silicon wafer is cut is a cavity defect (COP) generation region. In the cross section of the single crystal shown in FIG. 1 cut perpendicular to the pulling axis, the ring-shaped OSF obtained when the pulling speed is relatively higher is located near the outer peripheral portion. It is assumed that the size of the COP defect detected in the cut wafer has an average diameter of 0.1 μm or less and does not exceed 0.15 μm.
[0049]
The reason why the average diameter of the COP defects is 0.1 μm or less is that if the average diameter is larger than this, the annealing process at 1200 ° C. or less cannot form a surface defect-free layer having extremely few COP defects. More preferably, the average diameter is set to 0.07 μm or less.
[0050]
COP defects exceeding 0.15 μm do not disappear from the surface layer even when annealing is performed, and cause a malfunction of the formed integrated circuit. It is more preferable that the thickness does not exceed 0.12 μm.
[0051]
The density of oxygen precipitates formed inside the wafer (excluding the defect-free layer on the surface) is 2.5 × 10⁸Pieces / cm³That is, it is assumed that the density distribution in the radial direction of the wafer is 4 or less in the maximum value / minimum value ratio. Although this oxygen precipitate is hardly detected on a wafer that has been cut out of a single crystal, it is formed by heat treatment in the process of forming an integrated circuit, and becomes a BMD having an effective gettering action.
[0052]
Although the formation of oxygen precipitates slightly fluctuates depending on the thermal history, here, as conditions that can simulate the formation under general processing conditions, heat treatment is performed at 900 ° C. for 4 hours and then at 1000 ° C. for 16 hours. Then, evaluation is performed on oxygen precipitates formed inside the wafer. This evaluation heat treatment condition is not particularly limited, and may be any condition as long as the BMD forming ability in the processing step of the wafer can be evaluated. With respect to the wafer subjected to the annealing treatment, it is possible to evaluate oxygen precipitates by heat treatment at 1000 ° C. for 16 hours.
[0053]
The density of oxygen precipitates is 2.5 × 10⁸Pieces / cm²If it is less than 3, the internal gettering effect may be insufficient. However, if the amount is too large, oxygen precipitates may remain in the surface defect-free layer after annealing or cause warpage or cracking of the wafer.¹⁰Pieces / cm²It is desirable to be up to. Such a BMD suppresses heavy metal contamination in the active region of the wafer surface layer by the gettering action and reduces the occurrence of defective products in the manufacture of integrated circuit devices. Therefore, it is important that the BMD is uniformly distributed over the entire surface of the wafer as much as possible. It is. Therefore, the distribution of the area density of oxygen precipitates is such that the ratio of the maximum value / minimum value in the radial direction of the wafer is 4 or less. More preferably, the ratio of the maximum value / minimum value is 2 or less.
[0054]
The wafer as described above, that is, the COP defects are finely distributed, a defect-free layer is easily formed on the surface by annealing in a non-oxidizing and non-nitriding atmosphere, and a sufficient amount of BMD is uniformly distributed inside. The production of a wafer that can be performed is performed as follows.
[0055]
In pulling and growing a silicon single crystal by the CZ method, the pulling speed is V (mm / min), and the temperature gradient at the center in the pulling axis direction of the single crystal is G._C(° C./mm) and the temperature gradient at the outer_S(° C./mm), the center is G in the temperature range from the melting point to 1000 ° C._CIs 3.0 or more, and G is from the melting point to 1300 ° C._C/ G_SIs not less than 1.0 and V / G_CIs 0.17 to 0.25 (mm²/ [° C. · min]). Here, the temperature gradient may be an average value obtained by dividing the difference between the highest temperature and the lowest temperature in the target temperature range by the distance between the two points.
[0056]
Temperature gradient G at the center from melting point to 1000 ° C._CIs set to 3.0 (° C./mm) or more, if it is less than 3.0, a wafer having an average diameter of COP defects of 0.1 μm or less and having no average diameter of more than 0.15 μm cannot be obtained. The pulling speed for realizing the required BMD density is limited, the density fluctuation due to the pulling speed becomes large, and the BMD density fluctuation in the radial direction of the wafer becomes large, so that the ratio of the maximum value / minimum value becomes four. This is because there are problems such as exceeding.
[0057]
Further, even in the temperature range from 1000 ° C. to 800 ° C., the temperature gradient G_CIs set to 2.5 (° C./mm) or more, the distribution of BMD becomes even more uniform. In this temperature range, a BMD which is a nucleus of OSF generation is formed. However, under the above-mentioned pulling condition, this defect is easily generated in the vicinity of the outer periphery of the crystal and makes the BMD density distribution non-uniform. In this temperature range, the temperature gradient G_CIs set to 2.5 (° C./mm) or more, generation of such defects can be suppressed, and the ratio of the maximum value / minimum value of the BMD density distribution in the wafer radial direction can be reduced to 2 or less. Will be possible.
[0058]
G in the temperature range from these melting points to 1000 ° C. and from 1000 ° C. to 800 ° C._CAlthough there is no particular upper limit, the non-contact cooling method has a limit, and it is difficult to grow dislocation-free crystals due to rapid cooling, and there is a risk of crystal cracking. / Mm).
[0059]
G from melting point to 1300 ° C_C/ G_SIs required to make the distribution of COP defects and BMD the target value of the wafer by combining with the above-mentioned temperature gradient in the single crystal. G in this temperature range_C/ G_SIs greater than 1.0 means that the temperature distribution in the direction of the wafer surface of the single crystal is higher at the outer peripheral portion than at the central portion, which is a cause of COP and BMD generation. This has the effect of making the amount of vacancies to be taken into the crystal plane at the solid-liquid interface uniform, and uniforming the distribution of vacancies during cooling.
[0060]
Next, in a temperature range from the melting point of the central portion of the single crystal to 1300 ° C., V / G_C0.17 to 0.25 (mm²/ [° C. · min]) is because when less than 0.17, the generation position of the ring-shaped OSF shifts into the inside of the wafer, and the variation in the area density of the BMD becomes large, and exceeds 0.25. This is because a COP defect of 0.15 μm or more tends to occur.
[0061]
In the manufacturing apparatus used to obtain the single crystal of the present invention, the structure around the hot zone, that is, the cooling portion of the single crystal during pulling, includes a cooling member by water cooling and a heat shielding material as shown in Patent Document 4, for example. Desirably, the composition is a combination. FIG. 2 is a schematic view of a cross section of the pulling apparatus having the hot zone. Here, it is assumed that the silicon single crystal 4 is pulled upward from the molten silicon 2 in the crucible 1 and grown. The hot zone surrounds the periphery of the single crystal 4 being pulled up, and has a cooling member 6 by internal water cooling or the like whose inner peripheral surface is coaxial with the pulling axis, and an outer surface and a lower end surface of the outer surface of the cooling member. The heat shield 5 is provided on the lower side.
[0062]
During the pulling, the surface of the single crystal 4 from immediately after solidification to the lower end of the heat shielding material 5 is kept warm by heat radiation from the wall of the crucible 1 heated by the heater 3 and the liquid surface of the molten silicon 2. It is in. On the other hand, the surface of the upper portion faces the cooling member 6 and is relatively strongly cooled. By adjusting the position of the component composed of the cooling member 6 and the heat shielding material 5, in the central portion of the single crystal immediately after solidification, the temperature decreases due to heat conduction of cooling to the surface of the upper portion, and the temperature decreases from the melting point. In the temperature range up to about 1300 ° C., the temperature gradient G of the surface in the pulling axis direction_STemperature gradient G in the center_CIs larger. That is, G_C/ G_SIs realized, the ratio of which exceeds 1.0.
[0063]
The cooling member 6 is installed at a temperature between the melting point and 1000 ° C._CTo 3.0 (° C./mm) or more, and further, G in a temperature range of 1000 ° C. to 800 ° C._CIs 2.5 (° C./mm) or more.
[0064]
In order to form a defect-free layer of COP on the surface using a wafer collected from the single crystal of the present invention, 0.5 to 6 at a temperature of 1100 to 1250 ° C. in an atmosphere of hydrogen, argon, or a mixed gas thereof. It is good to heat for hours. By performing annealing in such a non-oxidizing and non-nitriding atmosphere, a defect-free layer having a depth of 10 μm or more from the surface and having no BMD is formed.
[0065]
【Example】
A crucible is filled with 120 kg of a silicon raw material to which a dopant B is added so that the electric resistance becomes 10 Ωcm, and the target diameter is 210 mm, the body length is 1000 mm, and the oxygen concentration is 13 × 10¹⁷Atom / cm³A (26 ppma) single crystal growth experiment was performed. The growth conditions were as follows: the apparatus was set in a vacuum atmosphere of argon, the raw material was melted in a crucible by heating with a heater, the crystal orientation was set to <100>, and the seed crystal was adapted to the melt. The seed is squeezed while rotating, so that a shoulder portion is formed, and when the body length reaches 200 mm, the pulling speed is set to a predetermined value. To end.
[0066]
In the apparatus having the hot zone shown in FIG. 2, the distance between the melt surface and the lower end of the heat shielding material was set to 70 mm, and the lifting speed V when the body length reached 200 mm was set to 0.80 mm / min. Crystal growth was performed. The average temperature gradient G at the center of the single crystal from the melting point to 1000 ° C. and from 1000 ° C. to 800 ° C._CV / G in the temperature range from the melting point to 1300 ° C._C, Also the temperature gradient G at the surface_SG for_CRatio G_C/ G_SAnd the like were as shown in Test Material No. 1 in Table 1. In the above hot zone, the temperature gradient G was set to 90 mm between the melt surface and the lower end of the heat shield._CIs shown as Test Material No. 2 and the case where the distance between the melt surface and the lower end of the heat shielding material is set to 60 mm is shown as Test Material No. 3.
[0067]
Also, as a comparative example, G_C/ G_SIn the case where the COP defect generation area is set to a pull-up speed that occupies the entire surface of the wafer so that the COP defect generation area is 1 or more, the test material No. 4 is used._C/ G_SIn the case of the conventional hot zone in which the COP defect occurrence area is set to a pulling speed that occupies the entire surface of the wafer, the test material No. 5 is used. Test material No. 6 shows the case where the lifting speed was 70%.
[0068]
Using a OPP apparatus, the density, average diameter, and maximum defect diameter of COP defects were measured on a wafer cut from the center of each sample single crystal and polished on the surface. Oxygen precipitates were heated at 900 ° C for 4 hours, then heated at 1000 ° C for 16 hours, and subjected to 2 μm light etching at the fracture surface at five or more locations in the radial direction of the wafer. Was measured, and its minimum and maximum values were determined. Table 1 also shows these results. FIG. 3 shows the relationship between the size of the observed COP defects and the density of the defects for the wafers of Test Material Nos. 1, 2, 4, and 5, and FIG. FIG. 4 shows the change in density of each sample.
[0069]
[Table 1]

[0070]
Next, as grown, wafers obtained from each of the six test materials shown in Table 1 were subjected to annealing at 1200 ° C. for 1 hour in high-purity argon, and annealing at 1150 ° C. for 1 hour in the same manner. Three types of wafers were prepared for processing.
[0071]
In each of the obtained wafers, the density of COP defects having a size of more than 0.1 μm on the surface was measured using a surface layer defect measuring device by light scattering (MO601 manufactured by Mitsui Kinzoku Kogyo KK). Further, five wafers were prepared for each condition, and the breakdown voltage characteristics of the oxide film were measured under the following conditions.
(A) Oxide film thickness: 25 nm
(B) Electrode area: 8 mm²
(C) Measurement electrode: phosphorus-doped polysilicon
(D) Judgment current: 1 mA / cm²
(E) Non-defective product: dielectric breakdown electric field is 11 MV / cm or more
Further, in order to check the state of the BMD inside the wafer after the annealing, the wafer after the above 1200 ° C. annealing was subjected to a heating treatment at 1000 ° C. for 16 hours, and then a 2 μm light etching was performed on the fractured surface. The density was measured. Table 2 shows the results. Furthermore, the distribution of the depth of the surface defect-free layer and the distribution of the internal BMD density in the radial direction when the annealing treatment at 1150 ° C. and the heating treatment at 1000 ° C. for 16 hours were performed on the wafer of Test Material No. 2 FIG. 5 shows the results of the examination.
[0072]
[Table 2]

[0073]
As can be seen from the results of Test Material Nos. 1 and 2 or 3 in Table 1, FIG. 3 and FIG. 4, in the wafer of the present invention, the size of the COP defect is small in the as-grown state, but the density is high. The generated oxygen precipitate has a high density and is uniformly distributed in the wafer plane. In such a wafer, when growing a single crystal as a raw material, the temperature gradient of cooling is increased, and immediately after solidification, the temperature gradient inside is larger than the surface portion of the single crystal, and V / G_CCan be produced by controlling and cultivating a specific range.
[0074]
From the results shown in Table 2, the wafers of the present invention of Test Materials 1, 2 and 3 do not have a good non-defective rate of oxide film breakdown voltage characteristics in the as-grown state, but have a high non-defective rate by performing annealing. It is clear that the wafer is close to 100%. In addition, the amount of BMD generated inside the wafer is large, and the variation due to the position is small.
[0075]
On the other hand, the wafers of the test materials 4, 5, and 6 manufactured by the conventional method have better oxide film breakdown voltage characteristics than the wafer of the present invention in the as-grown state. Does not improve. In addition, the amount of BMD generated is small and the variation is large.
[0076]
Further, as can be seen from FIG. 5, despite the low annealing temperature of 1150 ° C., the wafer of the present invention has a defect-free layer with almost no COP defects formed on the wafer surface with a thickness of 15 μm or more. 35 × 10 even at low internal BMD generation density⁸Pieces / cm³That's it. And 65 × 10 even in many positions⁸Pieces / cm³Below, and the density distribution shows an excellent distribution of 2 or less in the maximum value / minimum value ratio.
[0077]
【The invention's effect】
By subjecting the silicon wafer of the present invention to annealing by high-temperature heating in a non-oxidizing and non-nitriding atmosphere, a defect-free layer having extremely few COP defects can be formed on the surface layer, and the gettering action is provided inside. BMDs with defects can be distributed sufficiently in the wafer surface. This wafer greatly improves the yield of non-defective products of the integrated circuits formed thereon, and greatly contributes to the reduction of the manufacturing cost of integrated circuits, that is, ICs.
[0078]
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing an example of a typical defect distribution observed on a silicon wafer.
FIG. 2 is a diagram schematically illustrating a cross section of a silicon single crystal manufacturing apparatus used in Examples.
FIG. 3 is a diagram showing the size of COP defects and their existing density in each wafer.
FIG. 4 is a diagram showing the distribution of the density of BMD generated inside each wafer in the plane of the wafer.
FIG. 5 is a view showing a thickness distribution of a BMD defect-free layer on the surface and a density distribution of BMD inside the wafer in a plane direction of the wafer subjected to the oxygen precipitation treatment after annealing at 1150 ° C.
[Explanation of symbols]
1. Crucible
2. Silicon melt
3. heater
4. Single crystal
5. Heat shield
6. Coolant

Claims (5)

When the oxygen concentration is 24 ppma (old ASTM) or more, the size of COP defects observed on the surface is 0.1 μm or less on average and none exceeds 0.15 μm. The density of the formed oxygen precipitate is 2.5 × 10 ⁸ / cm ³ or more, and the density distribution of the oxygen precipitate in the radial direction of the wafer is 4 or less in a maximum value / minimum value ratio. Silicon wafer. ^{2. The} defect-free layer having an oxygen concentration of 24 ppma (old ASTM) or more and COP defects observed on the surface of 0.5 defects / cm ² or less, having a depth of 5 μm or more, ^2. Annealed wafer made from a silicon wafer. In the production of a silicon single crystal pulled and grown by the Czochralski method (CZ method), the single crystal pulling speed is V (mm / min), and the temperature gradient at the center of the single crystal in the pulling axis direction is G _C (° C./mm). ), Assuming that the temperature gradient at the outer peripheral portion is G _S (° C./mm), _GC is 3.0 or more in the temperature range from the melting point to 1000 ° C. in the central portion, and GC / _C from the melting point to 1300 ° C. in claim 1 in which the ratio of G _S exceeds 1.0 and V / _{G C} is characterized in that collected from a single crystal was pulled as ^{0.17~0.25 (mm 2 / [℃ ·} min]) A method for producing a silicon wafer as described above. In a silicon single crystal manufacturing method according to claim 3, in a temperature range of more central portion to 800 ° C. exceed 1000 ° C., a manufacturing method of a silicon wafer, comprising G _C pulls up as 2.5 or more. The silicon wafer according to claim 1, wherein the silicon wafer is heated at a temperature of 1100 to 1250 ° C for 0.5 to 6 hours in a hydrogen gas, an argon gas, or a mixed gas atmosphere of these gases. Item 3. A method for producing an annealed wafer according to item 2.

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