JP2004247820A - Frequency multiplier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency multiplier for generating a clock signal having a frequency as high as possible according to the frequency of a signal inputted from the outside by bringing out the performance of a PLL to its maximum by using a simple configuration. <P>SOLUTION: The frequency multiplier is provided with a magnification measuring device 30 for comparing the frequency of an external clock with the output frequency of a VCO (variable oscillator) 13 to measure magnification; a multiplication ratio setting means 40 for setting a multiplication ratio for a frequency divider 14 of the PLL 10 on the basis of the measurement result of the device 30; and a multiplication ratio control section 50 for temporarily switching the signal to an output signal of a phase delaying means 60 for delaying the phase of an external clock for a phase comparator 11 of the PLL 10, so that the output frequency of the VCO 13 may become the maximum in magnification measurement by the device 30. If a lock signal of the PLL 10 is not detected when a predetermined time elapses after the multiplication ratio N is set, the multiplication ratio N is decreased step by step. If the lock signal is not detected when the decrease in the multiplication ratio is performed predetermined times, the process goes back to the magnification measurement. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a frequency multiplier that outputs a signal obtained by multiplying the frequency of an external input signal.
[0002]
[Prior art]
In order to operate semiconductor integrated circuits and option boards at high speed, a signal obtained by multiplying an external input signal (hereinafter referred to as an external clock) using a PLL (Phase Locked Loop) is generated, and the signal is used as an internal clock. Operating the circuit has been performed. Hereinafter, a device (circuit) that multiplies the external clock according to a set multiplication factor using such a PLL is referred to as a frequency multiplier (corresponding to a frequency multiplication device).
In such a frequency multiplier, even if the frequency of the input external clock may be different (not predetermined), in order to operate the internal circuit while maintaining a predetermined high-speed performance, the frequency multiplier should be as high as possible. It is necessary to generate an internal clock having a frequency, that is, to set a multiplication factor as high as possible according to the frequency of the external clock. However, the output frequency of the PLL is usually limited in the band of the oscillation frequency. Therefore, if the frequency of the external clock × the multiplication rate is out of the oscillation frequency range of the PLL, the PLL does not operate. For this reason, it is required to set the highest possible multiplication rate within the frequency range in which the PLL can oscillate.
Patent Documents 1 and 2 disclose that a reference clock (oscillator) is provided internally in such a case that the multiplication factor can be automatically set without setting the multiplication factor externally even in a usage environment where the frequency of the external clock is different. It has been proposed to automatically set the multiplication factor based on a comparison between a clock frequency and the frequency of the external clock.
FIG. 6 is a block diagram illustrating a configuration of a conventional frequency multiplier A based on the technology disclosed in Patent Documents 1 and 2.
As shown in FIG. 6, a conventional frequency multiplier A includes a PLL 1, a reference oscillator 2 for generating a reference clock (a signal to be a reference) used for setting a multiplication factor N, and an output frequency of the reference oscillator 2. And a frequency of the external clock, and a magnification measuring device 3 for measuring the ratio (magnification) of the external clock. Multiplication rate setting means 4 for setting the rate N to the PLL 1.
The PLL 1 also includes a phase comparator 11 for comparing the phases of two input signals, a loop filter 12 for smoothing the phase comparison result (phase deviation) by the phase comparator 11 and outputting a voltage, A VCO 13 (an example of a voltage controlled oscillator or a variable oscillator) for adjusting the frequency of an output signal according to the output voltage of the VCO 12 (that is, based on the result of phase comparison by the phase comparator 11); A frequency divider that divides the frequency by an inverse of the multiplier set by the multiplier setting unit, wherein the external clock and the output signal of the divider are input to the phase comparator. Have been.
Accordingly, the output frequency of the VCO 13 is adjusted so that the phases of the two input signals input to the phase comparator, that is, the external clock and the output signal of the frequency divider 14 are synchronized. Therefore, the output signal of the VCO 13 (that is, the internal clock) is a signal obtained by multiplying the frequency of the external clock by the multiplication factor set in the frequency divider 14.
The multiplication rate setting means 4 sets a predetermined frequency near the maximum output frequency of the VCO 13 to y _max When the output frequency of the reference oscillator 2 is a and the magnification of the output frequency a of the reference oscillator 2 with respect to the frequency of the external clock measured by the magnification measuring device 3 is R, for example, the following equation (1) is used. The multiplication factor N is calculated.
N = y _max / (A / R) (however, truncation below decimal point) ... (1)
As a result, the maximum magnification N that can be output as much as possible within the range that the VCO 13 can output is calculated according to the measurement result R by the magnification measuring device 3, that is, according to the frequency of the external clock.
[0003]
[Patent Document 1]
JP-A-10-289032
[Patent Document 2]
JP 2001-135038 A
[0004]
[Problems to be solved by the invention]
However, in the configuration shown in FIG. 6 in which the frequency of the external clock is measured using an independent reference clock (the output of the reference oscillator 2) to determine the multiplication factor N, the output of the PLL 1 can be output. The error of the reference clock (error of the reference oscillator 2) and the error of the oscillation frequency of the PLL 1 (errors of the phase comparator 11, the loop filter 12, the VCO 13, etc.) are set in advance so as to fall within the upper limit frequency. It is necessary to set the multiplying factor N with a margin by taking into account the output frequency error). For example, y in equation (1) _max Is set lower than the maximum frequency that can be actually output. For this reason, there has been a problem that the maximum capability of the PLL 1 cannot be sufficiently exhibited. In particular, when the reference clock is configured using a simple logic circuit, the error between individuals increases, so a larger margin must be expected, and an accurate reference clock must be generated using an oscillation circuit. Then, the cost increases.
Accordingly, the present invention has been made in view of the above circumstances, and it is an object of the present invention to maximize the performance of a PLL with a simple configuration, and to provide a clock having a highest frequency according to the frequency of an external input signal. An object of the present invention is to provide a frequency multiplier for generating a signal.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a phase comparator for comparing the phases of two input signals, and an output signal for synchronizing the phases of the two input signals based on a comparison result by the phase comparator. A variable oscillator for adjusting the frequency; and a frequency divider for dividing an output signal of the variable oscillator to a reciprocal of a set multiplication factor, wherein an external input signal and an output signal of the frequency divider are output by the frequency divider. In a frequency multiplier configured to be input to a phase comparator, frequency comparison means for comparing the frequency of the external input signal with the frequency of the output signal of the variable oscillator; When performing frequency comparison by the frequency comparison means and the frequency comparison means for setting the multiplication rate based on the multiplication rate, control is performed so that the output signal of the variable oscillator becomes substantially the maximum outputtable frequency. And a force frequency up means, is constituted as a frequency multiplying device characterized by comprising comprises a. Here, the phase comparator, the variable oscillator, and the frequency divider constitute a PLL.
As described above, the multiplication factor is set using the output of the variable oscillator such as the VCO included in the PLL without providing an independent reference clock oscillator. In addition, since the multiplication factor is set based on a comparison between the substantially maximum frequency actually output by the variable oscillator and the frequency of the external input signal, the performance variation and error of each device such as a PLL can be set. There is no need to consider the margin due to. As a result, it is possible to set the multiplication factor that maximizes the performance of the PLL according to the frequency of the external input signal.
[0006]
Further, the output frequency maximizing means delays one of the input signals to the phase comparator with a phase delay means for delaying the phase of the external input signal and a predetermined time for comparing the frequency by the frequency comparing means. Signal switching means for switching to the output signal of the phase delay means before, and switching to the output signal of the frequency divider after setting the multiplication rate by the multiplication rate setting means.
According to this configuration, when one of the input signals to the phase comparator is set as the output signal of the phase delay unit by the signal switching unit, the external input which is the other input signal of the phase comparator is used. Since a phase difference (phase delay) occurs between the signal and the signal, the output frequency of the variable oscillator increases in an attempt to eliminate the phase difference. Here, since the output of the variable oscillator is not fed back to the phase comparator through the frequency divider, the output frequency of the variable oscillator continues to increase until it reaches a plateau at the upper limit. Therefore, if the predetermined time is set to a time sufficient to increase the output frequency of the variable oscillator to a maximum (a peak), the output frequency of the variable oscillator can be made substantially the maximum. Moreover, since the maximum output frequency of the variable oscillator is obtained as a result of operating the components of the PLL such as the phase comparator, variations in the characteristics of the components of the PLL are considered when setting the multiplication factor ( There is no need to provide a margin).
[0007]
Further, it is conceivable that the phase comparator uses an exclusive OR logic circuit and the phase delay unit uses an inverter circuit.
This makes it possible to configure the phase comparator and the phase delay unit with a simple configuration.
[0008]
The frequency comparing means may include a frequency of the external input signal and a frequency of the variable oscillator based on the number of times the output signal of the variable oscillator oscillates while the external input signal oscillates a predetermined number of times. Is compared with the frequency of the output signal.
This makes it possible to perform frequency comparison (measurement) with less error than the frequency comparison based on the number of times the reference clock oscillates while the external input signal oscillates once as in the prior art. Become.
[0009]
A timer using the output signal of the variable oscillator as a clock signal; and, after the multiplication rate is set, the phase comparator compares the input signal from the outside with the external input signal until a predetermined time is measured by the timer. If the synchronization of the phase with the output signal of the frequency divider is not detected, it may be possible to provide a multiplying factor reviewing means for changing the setting of the multiplying factor by one step lower.
Thus, even if the multiplication rate once set is too high and a situation where synchronization cannot be normally performed occurs, the multiplication rate is automatically reviewed so that the multiplication rate can be synchronized.
[0010]
In addition, even if the setting of the multiplying factor is changed a predetermined number of times by the multiplying factor reviewing means, the phase comparator does not detect the phase synchronization between the external input signal and the output signal of the frequency divider. It is also conceivable to provide a re-execution control means for controlling the comparison of the frequency by the frequency comparison means and the setting of the multiplication rate by the multiplication rate setting means again.
Thus, even if the multiplication rate is not set correctly due to noise in the external input signal input when performing the frequency comparison, the comparison is performed again from the frequency comparison. Then, the setting of the multiplication rate is performed again, so that an appropriate multiplication rate is reset.
[0011]
Even if the re-execution is performed a predetermined number of times by the re-execution control means, if the phase comparator does not detect the phase synchronization between the external input signal and the frequency divider output signal, An apparatus having an error output unit for performing a predetermined error output may be considered.
As a result, it is possible to notify the user that the multiplication rate could not be automatically set normally.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments and examples of the present invention will be described with reference to the accompanying drawings to provide an understanding of the present invention. The following embodiments and examples are mere examples embodying the present invention, and do not limit the technical scope of the present invention.
FIG. 1 is a block diagram showing a schematic configuration of a frequency multiplier Z according to an embodiment of the present invention, and FIG. 2 is a diagram showing a phase delay means and a signal selector constituting the frequency multiplier Z according to the embodiment of the present invention. FIG. 3 is a diagram showing an example of a circuit configuration of the means and the phase comparator, FIG. 3 is a block diagram showing an example of a configuration of an external clock magnification measuring device in the frequency multiplier Z according to the embodiment of the present invention, and FIG. FIG. 5 is a block diagram illustrating a schematic configuration of a frequency multiplier Z1 according to an embodiment of the present invention. FIG. 5 is a flowchart illustrating a procedure of a multiplication factor adjustment process in the frequency multiplier Z1 according to the embodiment of the present invention. It is a block diagram showing the schematic structure of the container A.
[0013]
First, the configuration of the frequency multiplier Z according to the embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 1, the frequency multiplier Z includes a PLL 10, a magnification measuring device 30, a magnification setting unit 40, a magnification control unit 50, a phase delay unit 60, and a signal selection unit 70. ing.
The PLL 10, like the conventional PLL 1 shown in FIG. 6, smoothes the phase comparator 11 for comparing the phases of two input signals and the result of phase comparison (phase deviation) by the phase comparator 11. A loop filter 12 that outputs a voltage, and a VCO 13 (a voltage controlled oscillator, a variable oscillator) that adjusts the frequency of an output signal in accordance with the output voltage of the loop filter 12 (that is, based on the result of phase comparison by the phase comparator 11). And a frequency divider 14 for dividing the output signal of the VCO 13 to the reciprocal of the multiplication factor set by the multiplication factor setting means 14.
In the PLL 10, the point that one signal input to the phase comparator 11 is a clock signal (the external clock) input from the outside is the same as the conventional frequency multiplication A. However, the other input signal is not always the output signal of the frequency divider 14 and, depending on the situation, the phase delay means 60 for delaying the phase of the output signal of the frequency divider 14 and the phase of the external clock. A conventional configuration (e.g., a configuration in which one of the output signals (the signal obtained by delaying the phase of the external clock) is selected (switched) by the signal selection unit 70 (an example of the signal switching unit)). 6).
Further, the magnification measuring device 30 (an example of the frequency comparing means) compares the frequency of the output signal of the PLL 10 with the frequency of the external clock, and measures the ratio (magnification) thereof (hereinafter referred to as magnification measurement). ) Therefore, an independent oscillator for the reference clock oscillation (the reference oscillator 2 in FIG. 6) is not provided unlike the related art. Further, the magnification measuring device 30 performs the magnification measurement based on the number of times the external clock oscillates while the output signal of the PLL 10 oscillates a predetermined number of times L.
[0014]
FIG. 3 is a block diagram showing an example of the configuration of the magnification measuring device 30. As shown in FIG. 3, for example, the magnification measuring device 30 includes a reference clock number counter 31 that sequentially counts the number of oscillations (the number of clocks) of the output signal of the VCO 13 and an external clock that sequentially counts the number of oscillations of the external clock. The number of counters 32 and the number of counts (the number of signal oscillations) from each of these counters 31 and 32 are input, and while the external clock number counter 32 counts M times (M ≧ 2), the reference clock number counter 31 And a magnification calculating means 33 for calculating a magnification R (= L / M) of the frequency of the external clock from the number L counted by the above.
This makes it possible to perform the magnification measurement with less error than when performing the magnification measurement based on the number of times the reference clock oscillates while the external clock oscillates once as in the related art.
In FIG. 3, the magnification calculation means 33 for calculating the magnification R is provided independently, but the calculation of the magnification R may be performed by the multiplication magnification setting means 40.
[0015]
On the other hand, the multiplication factor setting means 40 (FIG. 1) sets the multiplication factor N for the PLL 10 (that is, for the frequency divider 14) in the same manner as the conventional multiplication factor setting means 4 shown in FIG. The difference from the conventional one is that the frequency of the external clock is compared with the frequency of the output signal of the PLL 10 (that is, the frequency of the external clock measured by the magnification measuring device 30 is different from the frequency of the external clock). This is the point at which the multiplication factor N is calculated based on the multiplication factor of the output frequency.
Further, the multiplication rate control unit 50 outputs a signal switching signal (a signal designating which input signal is to be selected) to the signal selection unit 70, and outputs the signal to the magnification measurement unit 30. , And outputs a measurement command signal for instructing the timing of the magnification measurement.
With the above-described configuration, when the output signal of the frequency divider 14 is selected to be fed back to the phase comparator 11 by the signal selection unit 70, the output frequency of the VCO 13 is changed to the external clock and the external clock. The phase of the output signal of the frequency divider 14 is adjusted to be synchronized, and the output signal of the VCO 13 (that is, the internal clock) is multiplied by the frequency of the external clock at the multiplication factor set in the frequency divider 14. Signal.
[0016]
The phase delay means 60 may be configured to delay an arbitrary phase by a predetermined circuit. However, if the phase is delayed by 180 ° (that is, inverted) using an inverter circuit, the configuration is simplified. It becomes.
When an output signal of the phase delay unit 60 (a signal obtained by delaying the phase of the external clock) is selected as an input signal to the phase comparator 11 by the signal selection unit 70, the phase comparator 11 always outputs the signal. Since the phase delay is detected, the VCO 13 operates to sequentially increase the output frequency so as to eliminate the phase delay. If this state continues for a while, the output frequency of the VCO 13 becomes the upper limit and saturates. The output frequency of the VCO 13 in this saturated state is the true maximum output frequency of the PLL 10. In other words, the maximum output frequency that is declared in the PLL 10 is a value in which various errors of the phase comparator 11, the loop filter 12, the VCO 12, and the like are expected, and is actually higher than the nominal maximum output frequency. In many cases, frequency can be output. However, since the output frequency varies from one PLL 10 to another, a nominal value is conventionally used as the maximum output frequency of the PLL 10, and an error of the reference clock (the output of the reference oscillator 2) is further added. In consideration of the above, the multiplying factor N must be set so as to obtain a lower output frequency.
[0017]
Therefore, in the frequency multiplier Z, when the magnification measurement (that is, frequency comparison) by the magnification measuring device 30 is performed, the output frequency of the VCO 13 is set to the true maximum value, and the frequency is maximized. The multiplication factor N is set by the multiplication factor setting means 40 based on the multiplication factor (comparison result) of the external clock measured by comparing the frequency of the output signal of the VCO 13 with the frequency of the external clock.
The setting procedure of the multiplication rate N is performed as follows, for example.
First, at the time of start-up (when the power is turned on) or at the time of reset, the multiplication rate control unit 50 outputs a signal switching signal to the signal selecting means 70 so that the delay signal side of the external clock is selected. The state is maintained until a predetermined time sufficient for the output frequency of the VCO 13 to be saturated elapses. After the elapse of the predetermined time (that is, when the output frequency of the VCO 13 is saturated and the output frequency is at the true maximum value (substantially the maximum value)), the multiplying factor control unit 50 outputs the scaling factor. A measurement command signal for instructing the measuring device 30 to perform the magnification measurement is output. As a result, the magnification of the frequency of the external clock with respect to the output frequency (maximum output frequency) of the VCO 13 is measured, and is input to the multiplication factor setting means 40. Here, as means for detecting the time lapse until the output frequency of the VCO 13 saturates, for example, the timer is provided in the multiplier control unit 50 to increase the output frequency of the VCO 13. It measures a sufficient time according to the characteristic (rising speed) and monitors a change in the output voltage of the loop filter 12, and detects that the output frequency of the VCO 13 is saturated when the output voltage stops rising. And so on.
When the multiplier R of the frequency of the external clock is input from the multiplier 30, the multiplier R setting unit 40 sets a value obtained by converting the multiplier R into an integer (for example, truncated below the decimal point) as the multiplier N. Set to the frequency divider 14. Of course, if the frequency divider 14 can perform frequency division other than the reciprocal of an integer value, it is not always necessary to convert the frequency to an integer.
By setting the multiplying factor N in this way, the multiplying factor N is set according to the frequency of the external clock so that the output frequency of the VCO 13 is truly maximized in a range where it can be output. Here, in the multiplication measurement of the frequency of the external clock, the maximum frequency output of the PLL 10 itself used for frequency multiplication is used as a reference, instead of using a reference clock provided separately and independently as in the related art. Therefore, it is not necessary to consider a margin rate in consideration of variations among the PLLs 10 and the like, and it is possible to set a truly maximum multiplication factor N.
[0018]
For example, the frequency of the external clock is 40 MHz, and the maximum output frequency of the PLL 10 (that is, the maximum output frequency of the VCO 13) is 100 MHz at a nominal value, but actually has the capability (margin) to output up to 120 MHz. Think about it. In this case, in the conventional method, the multiplication factor N has to be set to 2 (= 100 ÷ 40 where the decimal part is rounded down) or less with reference to the nominal value of 100 MHz in consideration of the individual variation of the PLL 10. However, there is a case where N = 1 must be considered in consideration of the error of the reference clock. However, according to the frequency multiplier Z, it is confirmed that the PLL 10 actually outputs a 120 MHz signal. Since the multiplication factor N is set after measurement, the multiplication factor N can be set to 3 (= 120 （40). As a result, conventionally, only the internal clock of 80 MHz can be obtained, but according to the frequency multiplier Z, it is possible to obtain the internal clock of 120 MHz, which is 1.5 times that of the internal frequency.
After the multiplying factor N is set by the multiplying factor setting unit 40, the signal is switched by the multiplying factor control unit 50 to the signal selecting unit 70 so that the output signal side of the frequency divider 14 is selected. Output a signal. Thereby, the output signal of the VCO 13 (that is, the internal clock) is adjusted to be a signal obtained by multiplying the frequency of the external clock by the multiplication factor N set in the frequency divider 14.
[0019]
By the way, various types of the phase comparator, such as a positive edge trigger type tri-state output phase comparator for comparing the rising timing of the input pulse signal, an RS flip-flop applied type phase comparator, and the like are conceivable. If the means 60 delays (inverts) the phase by 180 ° by using, for example, an inverter circuit, the phase comparator 11 can use an exclusive-OR logic circuit. .
FIG. 2 is a diagram illustrating an example of a circuit configuration of the phase delay unit 60, the signal selection unit 70, and the phase comparator 11 when an inverter circuit is used as the phase delay unit 60. In the example shown in FIG. 2, the phase delay means 60 comprises an inverter circuit, and the phase comparator 11 comprises an exclusive-or logic circuit. When the selection signal output from the multiplication rate control unit 50 is “0” (OFF), the signal selection unit 70 selects the output signal of the frequency divider 14 and outputs “1” ( ON), the delay signal of the external clock (that is, the output signal of the phase delay unit 60) is selected.
With such a configuration, the combination of the external clock and a signal obtained by delaying the phase of the external clock by 180 ° (combination of inputs to the phase comparator 11) is (1, 0) or (0, 1). The output of the phase comparator 11 (exclusive OR logic circuit) which receives this as an input is always "1" (indicating that there is a phase shift). Thus, the output frequency of the VCO 13 can be increased to a maximum with a simple circuit configuration.
In addition, as a configuration for increasing the output frequency of the VCO 13 to a maximum (configuration of the output frequency maximizing means), a voltage signal input to the VCO 13 is output from the output of the loop filter 12 to the output of the loop filter 12. It is also conceivable that the maximum voltage signal that can be input to the VCO 13 can be selectively switched, and the magnification measurement by the magnification measuring device 30 is performed with the maximum voltage signal being input to the VCO 13. However, in the case of such a configuration, for example, when an error may occur between the maximum value of the output voltage of the loop filter 12 and the maximum voltage signal, the output signal of the PLL 10 is set to the true maximum frequency. It does not mean (error occurs). Therefore, as shown in FIG. 1, it is desirable to increase the frequency of the output signal of the PLL 10 to the maximum while making use of the components of the PLL 10.
[0020]
【Example】
Next, a frequency multiplier Z1 which is an application example of the frequency multiplier Z will be described.
FIG. 4 is a block diagram illustrating a configuration of the frequency multiplier Z1 according to the embodiment of the present invention. As shown in FIG. 4, the frequency multiplier Z1 has a configuration similar to that of the frequency multiplier Z. The difference is that the multiplier control unit 50 uses a timer that uses the output signal of the VCO 13 as a clock. 51, and the multiplication rate control unit 50 outputs a so-called lock signal from the PLL 10 (whether the phase of the external clock and the output signal of the frequency divider 14 are synchronized by the phase comparator 11 or not). Is detected, and the multiplication factor setting means 40 is controlled so as to review the setting of the multiplication factor N based on the lock signal. Other configurations and operations are the same as those of the frequency multiplier Z.
[0021]
Next, the process of setting and reviewing the multiplication factor N (multiplication factor adjustment process) in the frequency multiplier Z1 will be described.
FIG. 5 is a flowchart showing a procedure for adjusting the multiplication factor N, which is controlled by the multiplication factor controller 50 of the frequency multiplier Z1. Hereinafter, S01, S02,... Represent the numbers of the processing procedures (steps).
First, when the adjustment process of the multiplication factor N is started at the time of startup (when the power is turned on) or at the time of reset, a predetermined error detection counter x is initialized (x ← 0) (S01), and the multiplication factor is set. The control unit 50 outputs a signal switching signal to the signal selection means 70 so that the delay signal side (delay input) of the external clock is selected (S02).
Next, the time counted by the timer 51 is used until a sufficient time elapses for the output frequency of the VCO 13 to be saturated (that is, the output frequency of the VCO 13 is saturated and the output frequency becomes a true maximum value (substantially the maximum value). Value)) (S03). During this time, the output frequency of the VCO 13 changes, so that the timer 51 that uses the output signal of the VCO 13 as a clock signal has low timekeeping accuracy. However, there is no problem if a sufficient time is set for the timekeeping time.
Next, by outputting a measurement command signal instructing the magnification measuring device 30 to perform the magnification measurement from the multiplication ratio control unit 50, the VCO 13 output frequency (maximum output frequency) of the frequency of the external clock is output. Is measured (S04).
Next, the multiplication rate control unit 50 counts up (+1) the error detection counter x and initializes a magnification re-measurement counter y used to determine whether or not to execute the magnification measurement again. (Y ← 0) (S05).
Next, the magnification of the frequency of the external clock measured by the magnification measuring device 30 is input to the multiplication factor setting means 40, and the multiplication factor setting means 40 obtains the multiplication factor N based on the multiplication factor. It is set in the frequency divider 14 (S06).
Next, after the magnification re-measurement counter y is counted up (+1) (S07) by the multiplication rate control unit 50, the multiplication rate control unit 50 instructs the signal selection unit 70 to output the signal of the frequency divider 14. A signal switching signal is output so that the output signal side (that is, the loop feedback side in the PLL 10) is selected (S08). As a result, the output adjustment of the VCO 13 starts so that the output signal of the VCO 13 (ie, the internal clock) becomes a signal obtained by multiplying the frequency of the external clock by the multiplication factor N set in the frequency divider 14.
[0022]
Next, a predetermined time is set (timer set) in the timer 51 by the multiplication rate control unit 50 (S09), and the lock signal (two signals) of the PLL 10 is kept until the time is up (elapsed). It is checked whether or not a signal indicating that the phases of the input signals are synchronized (S10, S11). If the lock signal of the PLL 10 is detected before the time is up (Y side of S11), the multiplication rate adjustment process is terminated as it is, but the lock signal is not detected until the time is up. On the Y side of S10, the multiplication rate control unit 50 checks whether or not the magnification remeasurement counter y is larger than a predetermined value Y (≧ 1) (S12). If there is, the process proceeds to S15, and if it is larger than the predetermined value Y, the process proceeds to S13.
When the process proceeds to S15, the multiplying factor controller 50 outputs a signal switching signal to the signal selecting means 70 so that the delay signal side (delay input) of the external clock is selected (S15). Further, the time counted by the timer 51 is used until the time sufficient for the output frequency of the VCO 13 to be saturated elapses (that is, the output frequency of the VCO 13 is saturated and the output frequency becomes a true maximum value (substantially the maximum value). )) (S16), and the multiplying factor setting means 40 reduces the multiplying factor N, which is one step lower than the currently set multiplying factor N (one step), to the frequency divider 14 (step S16). After setting (S17), the above-described processing from S07 is repeated.
After the multiplication rate N is set (S06) by the processing from S06 to S12 to S15 to S17, the lock signal is not detected until a predetermined time is measured by the timer 51 (the phase comparator 11 determines the lock signal). When the synchronization of the phase between the external clock and the output signal of the frequency divider 14 is not detected), the setting of the multiplication rate N is changed by one step lower (an example of the processing of the multiplication rate reviewing means).
By performing such a process, even if the multiplication factor N once set is too high and a situation in which synchronization cannot be normally achieved occurs, the multiplication factor N is automatically adjusted so that the multiplication factor N can be synchronized. Will be reviewed.
[0023]
On the other hand, in S12, when it is determined that the magnification re-measurement counter y is larger than the predetermined value Y, that is, when the lock signal cannot be detected even after decreasing the magnification N by Y steps (Y side of S12). It is checked whether the value of the error detection counter x is greater than a predetermined value X (S13). If it is determined that the value is equal to or less than the predetermined value X, the process returns to S02 to return to the signal selection means 70. The process is repeated from the point at which the signal is switched and the magnification measurement is performed again (an example of the process of the re-execution control unit).
Thus, even if the multiplication factor N is not set correctly due to noise in the external clock input when performing the magnification measurement (frequency comparison), the processing is restarted from the magnification measurement. Then, the multiplying factor N is set again, so that the appropriate multiplying factor N is reset.
Further, in S13, when it is determined that the value of the error detection counter x is larger than the predetermined value X, that is, even if the re-setting of the multiplication factor N from the magnification measurement is executed X times, the lock is still performed. If no signal is detected, a predetermined error output (S14) is output from the multiplication rate control unit 50 to a display device (not shown), and the multiplication rate adjustment processing ends. As a result, it is possible to inform the user that the multiplication factor N has not been automatically set normally.
By performing the above processing, even if the multiplication factor N is not set correctly, the multiplication factor N is reviewed and the appropriate multiplication factor N is automatically set as high as possible.
[0024]
【The invention's effect】
As described above, according to the present invention, with a simple configuration that does not require an independent reference clock, the performance of the PLL can be maximized without considering margins due to performance variations and errors of individual devices such as a PLL. It is possible to provide a frequency multiplier (apparatus) that generates a clock signal having a frequency as high as possible in accordance with the frequency of an input signal from the outside or from the outside.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a frequency multiplier Z according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a schematic configuration of a frequency multiplier Z according to the embodiment of the present invention.
FIG. 3 is a block diagram illustrating an example of a configuration of an external clock magnification measuring device in the frequency multiplier Z according to the embodiment of the present invention.
FIG. 4 is a block diagram showing a schematic configuration of a frequency doubler Z1 according to the embodiment of the present invention.
FIG. 5 is a flowchart illustrating a procedure of a multiplication factor adjustment process in the frequency multiplier Z1 according to the embodiment of the present invention.
FIG. 6 is a block diagram illustrating a schematic configuration of a conventional frequency multiplier A.
[Explanation of symbols]
1,10 ... PLL
2. Reference oscillator
3, 30 ... magnification measuring device
4, 40... Multiplication rate setting means
11 ... Phase comparator
12 ... Loop filter
13. VCO (variable oscillator)
14 ... frequency divider
31: Reference clock counter
32: External clock number counter
33: Magnification calculation means
50: Multiplication rate control unit
51 ... Timer
60 phase delay means
70 ... Signal selecting means (signal switching means)
S01, S02,... Processing procedure (step)

Claims (7)

A phase comparator for comparing phases of two input signals, a variable oscillator for adjusting a frequency of an output signal based on a comparison result by the phase comparator so as to synchronize the phases of the two input signals, and a variable oscillator And a frequency divider that divides the output signal of the frequency divider to the reciprocal of the set multiplication factor. The external input signal and the output signal of the frequency divider are input to the phase comparator. In a frequency multiplier,
Frequency comparing means for comparing the frequency of the external input signal with the frequency of the output signal of the variable oscillator;
Multiplication factor setting means for setting the multiplication factor based on the comparison result by the frequency comparison means;
Output frequency maximizing means for controlling the output signal of the variable oscillator to be substantially the maximum outputtable frequency when comparing the frequencies by the frequency comparing means;
A frequency multiplier comprising: The output frequency maximizing means comprises:
Phase delay means for delaying the phase of the external input signal;
One of the input signals to the phase comparator is switched to the output signal of the phase delay means a predetermined time before the frequency comparison is performed by the frequency comparison means, and the division signal is set after the multiplication rate setting means sets the multiplication rate. 2. The frequency multiplier according to claim 1, further comprising signal switching means for switching to an output signal of the frequency divider. 3. The frequency multiplier according to claim 2, wherein said phase comparator uses an exclusive-OR logic circuit, and said phase delay means uses an inverter circuit. The frequency comparing means determines the frequency of the external input signal and the output of the variable oscillator based on the number of times the external input signal oscillates while the output signal of the variable oscillator oscillates a predetermined number of times. The frequency multiplier according to any one of claims 1 to 3, wherein the frequency multiplier compares the frequency of the signal. A timer using the output signal of the variable oscillator as a clock signal;
When the phase comparator does not detect the phase synchronization between the external input signal and the frequency divider output signal before the timer measures the predetermined time after the multiplication rate is set, The frequency multiplier according to any one of claims 1 to 4, further comprising: a multiplier ratio reviewing unit that changes the setting of the multiplier ratio by one step. If the phase comparator does not detect the synchronization of the phase between the external input signal and the output signal of the frequency divider even if the setting of the multiplier is changed a predetermined number of times by the multiplier reviewer, 6. The frequency multiplication device according to claim 5, further comprising a re-execution control unit that controls the comparison of the frequency by the frequency comparison unit and the setting of the multiplication ratio by the multiplication ratio setting unit to be executed again. Even if the re-execution control means performs the re-execution a predetermined number of times, if the phase comparator does not detect the phase synchronization between the external input signal and the output signal of the frequency divider, a predetermined number 7. The frequency multiplier according to claim 6, further comprising error output means for outputting an error.

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