JP2004240811A - Information processor and prefetch method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a prefetch control mechanism (prefetch system) which can intermittently specify different attributes to the prescribed regions of a main storage. <P>SOLUTION: A prefetch control mechanism 4 has a request address register 401 to store an address of the main storage, a significant bit string 402a which gives an instruction to prefetch, and an address space table 402 having a high order address string 402b which stores prescribed values. The prefetch control mechanism 4 has functions (a request valid flag register 400, a request address register 401, a comparator 403, and an AND circuit 404) to output a prefetch instruction signal and an address stored in the request address register 401 to a cache memory device, when a part of the address of the request address register 401 and a prescribed value stored in the high order address string 402b agree and the significant bit string 402a gives an instruction to prefetch. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a cache memory prefetch control method and method.
[0002]
[Prior art]
Some information processing apparatuses having a conventional processor and having a memory hierarchical structure of a cache memory device and a main storage device have a prefetch function for high performance. Prefetching (fetching) data from a high-speed (short access time) but large-capacity cache memory from a large-capacity but low-speed (long access time) main memory is called prefetch, and is information with a memory hierarchical structure. This is an effective means for increasing the speed of the processing apparatus (there are many known techniques, for example, JP-A-2001-175533 and JP-A-11-167520).
[0003]
However, in prefetching, data that will be needed in the future is predicted and brought, so that useless data is brought to waste memory bandwidth (data transfer capability at the exit of the external memory) or to be useful. There is an adverse effect such as useless data overwriting unnecessary cache data. In order to reduce this adverse effect, Japanese Patent Laid-Open No. 2000-148584 divides the entire address space into three spaces, a “normal space”, a “prefetch space”, and a “cache space”, and divides the normal space into addresses 0x00000000 to 0x3ffffffff. , The prefetch space is allocated to addresses 0x40000000 to 0x7ffffffff, and the cache space is allocated to addresses 0x80000000 to 0xffffffffff. That is, it is possible to determine the belonging space only by referring to the upper two bits of the address.
Note that “0x” is a prefix indicating a hexadecimal number.
[0004]
In the "prefetch space", data that is continuously accessed by the processor and is used only once, such as stream data, is arranged, and the prefetch mechanism operates in response to a read request from the processor. On the other hand, the "cache space" has locality in space and time, and the processor arranges reusable data, copies data fetched from external memory to internal memory (cache), Used for lead. Further, the “normal space” is an address space that does not use a prefetch or a cache.
[0005]
In the preceding case, since the address space has different attributes in this way, if programs (instructions and data) are optimally allocated according to their characteristics, the internal memory can be effectively used to achieve high performance. System.
[0006]
[Patent Document 1]
JP 2001-175533 A
[Patent Document 2]
JP-A-11-167520
[0007]
[Problems to be solved by the invention]
However, in the above case, since the address space is simply divided into three parts, in the current operating system (OS) such as Linux, the possibility of prefetching and the possibility of caching are appropriately determined according to a plurality of programs and data characteristics. Is impossible to control.
[0008]
Further, in a program that processes data continuously at short intervals, prefetching data one block ahead cannot be performed in time and performance is not sufficiently exhibited. Therefore, it is necessary to prefetch data several blocks ahead. On the other hand, in an area where the continuity of data is not always strong, careful "conservative prefetch" such as prefetching the next block after confirming continuous access of two blocks is necessary. As described above, the optimal prefetch method differs for each program area and each data area.
[0009]
Furthermore, when storing a large amount of sequential data in the cache in order, even if the cache is composed of a plurality of ways, the sequential data removes the frequently used data that has been stored in the past, and the cache miss rate. (Performance is degraded).
The present invention provides a prefetch function for intermittently giving different attributes to a predetermined area (for example, a plurality of programs, OS kernel routines, and data areas) of a main storage device without largely changing the current OS. The purpose is to provide.
It is another object of the present invention to increase the effect of prefetch by individually setting the number of blocks to be prefetched and the prefetch activation condition, and to further improve the performance by reducing side effects.
[0010]
[Means for Solving the Problems]
An information processing apparatus according to the present invention includes an information processing apparatus including a processor, a main storage device, and a cache memory, and having a prefetch function of instructing to read data stored in the main storage device into the cache memory in advance.
An address register for storing an address of a main storage device output from the processor;
An address space table having a first prefetch flag indicating a prefetch and a first address field storing a predetermined value;
When a part of the address of the address register matches a predetermined value stored in the first address field and the first prefetch flag indicates prefetch, a prefetch instruction signal and the address stored in the address register are used. And a control unit for outputting to the cache memory
It is characterized by having.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 shows an information processing apparatus according to Embodiment 1 of the present invention.
The information processing apparatus shown in FIG. 1 includes a processor 1, a cache memory device 2, a main storage device 3, and a prefetch control mechanism (prefetch control device) 4. In FIG. 1, a memory request signal line (consisting of a valid signal and an address signal) 11 issued by the processor 1, a data line 12 for exchanging data between the processor 1 and the cache memory device 2, a cache memory device 2, a fetch request line 21 issued to the main storage device 3, a data line 31 for exchanging data between the cache memory device 2 and the main storage device 3, and a prefetch control mechanism 4 indicating a prefetch request to the cache memory device 2. A prefetch request signal line (valid signal and address signal) 41 and a cache instruction signal line 42 for the prefetch control mechanism 4 to give a special instruction to the cache memory device 2 such as designation of a bypass or way to the cache are shown.
[0012]
In the following description, the information processing apparatus in FIG. 1 will be described as an example in which data transfer on the data line 31 is performed in units of 16 bytes and data transfer on the data line 12 is performed in units of 4 bytes. In the data transfer of the data line 31, that is, the data transfer between the cache memory device 2 and the main storage device 3, an access unit is a block size (access unit to the cache memory device).
[0013]
FIG. 2 is a diagram showing details of a prefetch control mechanism 4 which is a main component in FIG.
2, the memory request signal line 11 includes a request valid signal 11a and a request address signal 11b.
The prefetch request signal line 41 includes a prefetch valid signal 41a and a prefetch address signal 41b.
FIG. 2 shows a request valid flag register 400, a request address register 401, an address space table 402, a comparator 403, an AND circuit 404, and an adder 405 for calculating the next prefetch address.
[0014]
The request valid flag register 400 is set by the request valid signal 11a.
The request address register 401 includes an upper address field 401a, an index field 401b, and a lower address field 401c.
The address space table 402 includes a valid bit string 402a and an upper address string 402b.
[0015]
For clarity of explanation, the dimensions of each element are assumed.
The request address signal 11b has 32 bits.
The request address register 401 has 32 bits, the upper address field 401a has 8 bits, the index field 401b has 12 bits, and the lower address field 401c has 12 bits.
Assume that the number of entries in the address space table 402 is 4096, and the number of bits of one entry in the upper address column 402b is 8 bits.
The comparator 403 compares eight bits.
1, it is assumed that the cache block size is 16 bytes, the 4-way set associative, the number of entries per way is 4096, and the total is 256 Kbytes (= 4 × 4096 × 16).
[0016]
The number of bits is determined so as to have the following relationship (the names are omitted below, and are indicated only by symbols).
11b bit number = 401 bit number = 401a bit number + 401b bit number + 401c bit number.
The number of bits to be compared with the number of bits of 401a = the number of bits of one entry of 402b = 403.
A multiplier of 2 (the number of bits of 401b) (2 to the 12th power) = the number of entries of 402.
[0017]
Next, an operation example will be described.
First, as a system (in the information processing apparatus), an address space from 0x12345000 to 0x12345FFF is set as a prefetch space. In this case, for the 0x345th entry of the address space table 402 in FIG. 2, the effective bit string 402a = 1 and the upper address string 402b = 0x12 are set. The setting may be performed at the time of initial setting from the operating system, or may be performed at the time of executing an application via a dedicated driver. With this setting, the address space from 0x12345000 to 0x12345FFF is set as the prefetch space. The above address space merely specifies a continuous 4K byte space that can be prefetched. The actual prefetch address depends on the address requested by the processor.
[0018]
Next, a case where the processor 1 issues a memory request to address 0x12345010 via the memory request signal line 11 in FIG. 1 will be described. Address 0x12345010 is included in the prefetch space.
When the cache memory device 2 that has received the memory request does not hold the address (cache miss), it issues a fetch request of the same address to the main storage device 3 via the fetch request line 21 and the main storage device 3 responds. Desired data is transferred to the cache memory device 2 via the data line 31, and the cache memory device 2 transfers the data to the processor 1 via the data line 12.
When the cache memory device 2 originally holds the corresponding address (cache hit), the cache memory device 2 sends data to the processor 1 via the data line 12.
[0019]
On the other hand, the memory request issued by the processor 1 via the memory request signal line 11 is also transmitted to the prefetch control mechanism 4. The prefetch control mechanism 4 determines whether or not the corresponding address should be prefetched, and sends a prefetch request to the cache memory device 2 via the prefetch request signal line 41 when determining that the address should be prefetched. The cache memory device 2 checks whether or not the corresponding address has a cache block (hit / miss). If the address is a miss, the data is fetched from the main storage device 3 and stored in the cache.
[0020]
Next, FIG. 2 shows in detail the operation of the prefetch control mechanism 4 which has received the memory request. When a memory request comes via the memory request signal line 11, the request valid signal 11a = 1, and the desired address (0x12345010) is indicated in the request address signal 11b. The request valid flag register 400 is set to 1, and the address value = 0x12345010 is held in the request address register 401 (upper address field 401a = 0x12, index field 401b = 0x345, lower address field 401c = 0x010). Subsequently, the table of the address space table 402 is subtracted with the value of the index field 401b = 0x345 (refer to the 0x345th entry of the address space table 402), and the valid bit string 402a output (valid flag) = 1 and the upper address string 402b output (higher order) Address) = 0x12 is output. The upper address of the output result of the address space table 402 and the upper address field 401a are compared by the comparator 403. Since both values are 0x12, the output of the comparator 403 = 1 is output.
[0021]
Since the output value of the comparator 403, the value of the request valid signal 11a, and the output value of the valid bit string 402a are all 1, the output of the AND circuit 404 = 1, and the 41a (prefetch valid signal) = 1. The prefetch address also inputs the request address signal 11b to the adder 405, and the value obtained by adding 0x10 (cache block size) = 0x12345020 is output to the prefetch address signal 41b as the address to be prefetched. That is, a valid prefetch request is transmitted to the cache memory device 2 via the prefetch request signal line 41. Finally, the request valid flag register 400 is cleared to 0 by the prefetch valid signal 41a (the request valid flag register 400 is cleared by inputting the prefetch valid signal 41a), and the prefetch valid signal 41a is cleared to 0 in the next cycle. Thus, the prefetch request ends.
[0022]
On the other hand, if an address that should not be prefetched, for example, 0x00345010, enters the prefetch control mechanism 4 via the memory request signal line 11, the value set in the upper address field 401a is 0x00, and the address space table 402 The read upper address (upper address string 402b) is 0x12 and does not match, so that the output of the comparator 403 = 0, and therefore the output of the AND circuit 404 = 0, and the prefetch is not valid.
[0023]
When another example of an address that should not be prefetched, for example, 0x12344010 enters the prefetch control mechanism 4 via the memory request signal line 11, a valid bit (valid bit string 402a) read from the address space table 402. = 0, the output of the AND circuit 404 becomes 0, and the prefetch is not valid.
[0024]
In the above example, 4096 intermittent address spaces can be designated as prefetch spaces every 4 Kbytes. 4K bytes depend on the number of bits of the lower address = 12 bits, and 4096 places depend on the number of bits of the index = 12 bits. By changing the number of these bits, the size and number of the designated space can be changed.
Also, in realizing this, it is sufficient to use a table at the same level as that of the cache tag, and there is almost no increase in cost and no decrease in performance.
[0025]
As described above, this embodiment has the processor 1, the memory hierarchical structure of the main storage device 3, and the cache memory device (cache memory) 2, and stores the data stored in the main storage device 3 in the cache memory device. An example of the information processing apparatus (and the prefetch method) having the prefetch function (prefetch control mechanism 4) for instructing the prefetch to be performed in advance has been described.
The prefetch control mechanism 4 includes an address register (an example of the arrangement of the request address register 401) for storing the address of the main storage device output from the processor, a first prefetch flag for instructing the prefetch (an example of the valid bit string 402a), and a predetermined It has an address space table 402 having a first address field (an upper address column 402b is an example) for storing a value (for example, a part of the address of the main storage device 3) (installed in the information processing apparatus).
[0026]
Further, the prefetch control mechanism 4 determines that the part of the address of the address register matches the predetermined value (part of the address) stored in the first address field, and the first prefetch flag indicates prefetch. And a control unit for outputting a prefetch instruction signal and an address stored in the address register to the cache memory. FIG. 1 shows, as an example, the case where the control unit is realized by the request valid flag register 400, the request address register 401, the comparator 403, and the AND circuit 404.
[0027]
Also, an example has been described in which the address of the main storage device is handled by being divided into three parts, an upper part, a middle part, and a lower part. The address space table 402 stores a value to be compared with the address of the upper part (the upper part of the address of the main storage device) in the first address field, and stores the first prefetch flag and the first address field in one entry. It is assumed that there are entries of the number of the middle part. The control unit searches for an entry in the address space table 402 using the middle part as a search key, and instructs prefetch using the detected entry.
[0028]
In this embodiment, the presence / absence of prefetch is stored in the address space table, the address space table is searched using a part of the address, and the instruction of the presence / absence of prefetch can be immediately determined. Prefetch can be specified for various address spaces.
[0029]
Embodiment 2 FIG.
Next, a mechanism for issuing a plurality of blocks of a prefetch request will be described with reference to FIG.
The prefetch control mechanism 4 shown in FIG. 3 has, in addition to the same functions as in FIG. 2, the address space table 402 has a block number field column 402c, a number control circuit 406, and a selector 407. Elements indicated by other numbers are the same as those in FIG.
The block number field column 402c is a field for specifying the number of blocks for which prefetch is requested. One block corresponds to the block size of the cache (assumed to be 16 bytes in the first embodiment). By specifying the number of blocks, it is possible to specify the prefetch size (16 bytes × the number of blocks).
[0030]
Next, an operation example will be described.
First, the system sets an address space from 0x12345000 to 0x12345FFF as a prefetch space, and sets that there is a request to prefetch 4 blocks (that is, 16 × 4 = 64 bytes).
In this case, for the 0x345th entry in FIG. 3, a valid bit string 402a = 1, an upper address string 402b = 0x12, and a block number field 402c = 4 are set.
[0031]
FIG. 3 shows the operation of the prefetch control mechanism 4 having received the memory request in detail. When a memory request comes via the memory request signal line 11, the request valid signal 11a = 1, and the desired address (0x12345010) is indicated in the request address signal 11b. The request valid flag register 400 is set to 1, and the address value = 0x12345010 is held in the request address register 401 (upper address field 401a = 0x12, index field 401b = 0x345, lower address field 401c = 0x010). Subsequently, the table of the address space table 402 is retrieved with the value of the index field 401b = 0x345, the effective flag (the value of the 0x345th effective bit string 402a) = 1, the upper address (the value of the 0x345th upper address string 402b) = 0x12, and the block. The number (the value of the 0x345th block number field column 402c) = 4 is output. The upper address of the output result of the address space table 402 and the upper address field 401a are compared by the comparator 403, and since both values are 0x12, the result = 1 is output.
[0032]
Since the output result of the comparator 403, the value of the request valid signal 11a, and the valid bit output of the address space table 402 are all 1, the output of the AND circuit 404 = 1, and the 41a (prefetch valid signal) = 1. The prefetch address is also input from the request address signal 11b to the adder 405 via the selector 407, and the value obtained by adding 0x10 = 0x12345020 is sent to the cache memory device 2 via the prefetch address signal 41b as the address to be prefetched. Is transmitted.
[0033]
Here, the number of blocks = 4 output from the address space table 402 is input to the number control circuit 406, and the prefetch request is issued a plurality of times. The number-of-times control circuit 406 issues an instruction to switch the input of the selector 407 from the request address signal 11b to the output of the adder 405, and the selector 407 operates as such. That is, after issuing the value = 0x12345020, the adder 405 subsequently issues 0x12345030, 0x12345040, and 0x12345050. That is, the prefetch request of the address = 0x12345030, 0x12345040, and 0x12345050 is sent to the cache memory device 2 via the prefetch address signal 41b. Three cycles after the start, the number control circuit 406 resets the request valid flag register 400, and the prefetch valid signal becomes 0. This is shown in FIG.
[0034]
In FIG. 4, the names are omitted, and the state of the signals is shown using reference numerals.
In the request address signal 11b, the block number field 402c, and the adder 405, a portion indicated by a numerical value indicates that the indicated numerical value is set to each.
[0035]
In the above example, a value of 4 was set in the field of the block number field 402c, so a prefetch request of 4 blocks occurred. However, if an integer value N of 1 or more is set in the block number field 402c, a prefetch request of N blocks is realized. it can. In the case of a program with fast sequential data processing or a large delay in memory access, by increasing N, a prefetch request can be realized at an earlier timing, so that data can be supplied without interruption and high performance can be maintained.
[0036]
As described above, in the present embodiment, the cache memory of the first embodiment is premised on prefetching a storage area of a predetermined size (described as an example of 16 bytes) of an address input from the control unit. In addition to the function, each of the number of entries in the middle part of the address space table 402 has a block number field (a block number field column 402c is an example) for designating prefetching a storage area having a multiple of the predetermined size. (Requesting a prefetch request) is repeated as a multiple (number) specified in the block number field.
[0037]
In this embodiment, the prefetch method (the number of prefetch blocks, the activation condition) is stored in the address space table, so that the number of prefetch blocks can be prefetched for an intermittent address space.
[0038]
Embodiment 3 FIG.
In some cases, clear sequentiality is not guaranteed. In such a case, unconditionally prefetching the next block for every memory read leads to performance degradation due to side effects such as waste of the memory bus due to useless prefetch and eviction of effective cache blocks. There is. In such a case, determining the prefetch by a more careful (conservative) method is effective as a method of eliminating unnecessary prefetch and reducing side effects.
In this embodiment, the feasibility of such a function will be described with reference to FIG.
In FIG. 5, elements having the same numbers as those in FIG. The prefetch control mechanism 4 of FIG. 5 adds a conservative prefetch flag column 402d and a previous request lower address column 402e to the address space table 402 in addition to the components shown in FIG. Further, in addition to the components shown in FIG. 2, an adder 408 for adding the number of bytes of the block, a comparator 409, an AND circuit 410, a NOT element 411, and an OR circuit 412 are added.
[0039]
Next, an operation example will be described.
First, as a system, an address space from 0x12345000 to 0x12345FFF is set as a conservative prefetch space.
The conservative prefetch space means that a single request does not issue a prefetch request, but issues a prefetch request only when two requests with consecutive addresses come. In this case, for the 0x345th entry of the address space table 402 in FIG. 5, in addition to the valid bit string 402a (valid bit) = 1, the upper address string 402b (upper address) = 0x12, the conservative prefetch flag string 402d (conservative Prefetch flag) = 1 is set. At this stage, the previous request lower address column 402e has no value. When a memory request (address = 0x12345010) is issued from the processor 1, the prefetch control mechanism 4 does not issue a prefetch request. Subsequently, when a memory request (address = 0x12345020) is issued from the processor 1, the prefetch control mechanism 4 issues a prefetch request. Thus, when two consecutive addresses arrive, the prefetch control mechanism 4 issues a prefetch request.
[0040]
FIG. 5 shows the details of the operation of the prefetch control mechanism 4 that has received the memory request.
When a memory request (address = 0x12345010) arrives via the memory request signal line 11, the request valid signal 11a = 1, and the desired address (0x12345010) is indicated in the request address signal 11b. The request valid flag register 400 is set to 1, and the address value = 0x12345010 is held in the request address register 401 (upper address field 401a = 0x12, index field 401b = 0x345, lower address field 401c = 0x010). Subsequently, the table of the address space table 402 is retrieved with the value of the index field 401b = 0x345, the 0x345th entry of the address space table 402 is referred to, the effective bit string 402a (effective flag) = 1, and the upper address string 402b (upper address) = 0x12, conservative prefetch flag column 402d (conservative prefetch flag) = 1 is output.
[0041]
Since the conservative prefetch flag (output of the conservative prefetch flag column 402d) is 1, the output of the NOT element 411 becomes 0, and the output of the AND circuit 404 becomes 0. On the other hand, since the previous request lower address column 402e (previous request lower address) does not contain a value at present, the value becomes invalid, the output of the adder 408 also becomes invalid, the output of the comparator 409 becomes 0, and the AND circuit 410 Also becomes 0. Since the outputs of both the AND circuit 404 and the AND circuit 410 are 0, the output of the OR circuit 412 is also 0, and the prefetch valid signal 41a = 0, that is, the prefetch request is not transmitted to 4. Finally, the lower address writes the value (= 0x010) of the lower address field 401c into the 0x345th entry of the previous request lower address column 402e.
[0042]
Next, when a memory request (address = 0x12345020) arrives, the request valid signal 11a = 1, and the desired address (0x12345020) is indicated in the request address signal 11b. The request valid flag register 400 = 1 is set, and the address value = 0x12345020 is held in the request address register 401 (upper address field 401a = 0x12, index field 401b = 0x345, lower address field 401c = 0x020). Subsequently, the table of the address space table 402 is retrieved with the value of the index field 401b = 0x345, and the effective bit string 402a (effective flag) = 1, the upper address string 402b (upper address) = 0x12, and the conservative prefetch flag string 402d (conservative prefetch flag) ) = 1 and the previous request lower address column 402e (previous request lower address) = 0x010 is output.
[0043]
Therefore, the output of the adder 408 is 0x020, and the two input values of the comparator 409 match at 0x020, and the output of the comparator 409 becomes 1. Therefore, the output of the AND circuit 410 = 1. As before, since the output of the comparator 403 is 1, the output of the AND circuit 404 is 1. Therefore, the output of the OR circuit 412 = 1 and the prefetch valid signal 41a = 1. Further, the output of the adder 405 becomes 0x12345030, and the prefetch address signal 41b becomes 0x12345030. That is, a valid prefetch request is transmitted to the prefetch control mechanism 4. Finally, the lower address writes the value of the lower address field 401c (= 0x020) to the 0x345th entry of the previous request lower address column 402e.
[0044]
As described above, in this embodiment, each entry of the address space table 402 further includes a second address field (previous address) for storing the lower part of the address of the main memory previously stored in the address register. The request lower address column 402e is an example) and a second prefetch flag that specifies prefetching based on the address of the second address field (the conservative prefetch flag column 402d is an example). The value stored in the address string 402b) (the value to be compared with the address of the upper part) matches the upper part of the address register (request address register 401), and the first prefetch flag (valid bit string 402a) If you specify prefetch Further, when the difference between the address of the lower part stored in the second address field and the lower part of the address register is within a predetermined range, and the second prefetch flag specifies prefetch, The case where the prefetch instruction signal and the address stored in the address register are output to the cache memory device 2 has been described.
[0045]
In this embodiment, the prefetch method (conservative prefetch) is stored in the address space table, so that prefetch can be designated for conservative prefetch for an intermittent address space.
[0046]
Embodiment 4 FIG.
It is known that caching data having extremely low temporal locality and spatial locality of data leads to eviction of other useful data, which degrades performance. In the present invention, cache bypass designation of intermittent address space data is enabled by adding a small amount of H / W (hardware), and an embodiment thereof is shown in FIGS. 6, those having the same numbers as those in FIG. 2 have the same functions and the same purpose. In addition to the components shown in FIG. 2, a cache bypass flag column 402f, a way designation flag column 402g, and a way number column 402h are added to the address space table 402. Further, an AND circuit 420 and an AND circuit 421 are added.
[0047]
In this embodiment, the way designation flag column 402g and the way number column 402h are not used. Therefore, a configuration not included in the way designation flag column 402g and the way number column 402h may be employed.
The prefetch request signal line 41, which is an output signal of the prefetch control mechanism 4, includes a cache bypass instruction signal 42a, a cache way designation signal 42b, and a cache way number signal 42c.
[0048]
Next, an operation example will be described.
First, an address space from 0x12345000 to 0x12345FFF is set as a cache bypass space as a system. The cache bypass space is a function-defined address space in which data received from the main storage device 3 is sent to the processor 1 via the cache memory device 2 but is not left in the cache memory device 2. That is, in the cache memory device 2, the replacement of the cache block does not occur, and the data with low locality is prevented from replacing the data with high locality.
[0049]
In this case, the cache bypass flag 402f = 1 and the upper address string 402b = 0x12 of the 0x345th entry in FIG. 6 are set in advance. When a memory request (address = 0x12345010) is issued from the processor 1 of FIG. 1, the prefetch control mechanism 4 issues a cache instruction signal to the cache memory device 2 via the cache instruction signal line 42 to instruct a cache bypass. The cache memory device 2 receiving this sends the data fetched from the main storage device 3 to the processor 1, but does not replace the corresponding cache block.
[0050]
FIG. 6 shows the operation of the prefetch control mechanism 4 having received the memory request in detail. When a memory request (address = 0x12345010) arrives via the memory request signal line 11, the request valid signal 11a = 1, and the desired address (0x12345010) is indicated in the request address signal 11b. The request valid flag register 400 is set to 1, and the address value = 0x12345010 is held in the request address register 401 (upper address field 401a = 0x12, index field 401b = 0x345, lower address field 401c = 0x010). Subsequently, the table of the address space table 402 is retrieved with the value of the index field 401b = 0x345, and the output (upper address) of the upper address column 402b = 0x12 and the cache bypass flag column 402f are referred to by referring to the 0x345th entry of the address space table 402. (Cache bypass flag) = 1 is output. Since the output of the upper address field 401a and the output of the upper address column 402b match, the output of the comparator 403 = 1, and the output of the cache bypass flag column 402f = 1, so that the output of the AND circuit 420 = 1, indicating cache bypass. It is transmitted to the cache memory device 2 via the cache bypass instruction signal 42a.
[0051]
As described above, in this embodiment, each entry of the address space table 402 further includes the bypass flag (a cache bypass flag column 402f is an example) indicating that prefetch is to be avoided, and the first address field (upper address). The value stored in the column 402b) (the value to be compared with the address of the upper part) matches the upper part of the address register (request address register 401), and the first prefetch flag (valid bit string 402a) specifies prefetch. In this case, an example has been described in which the prefetch instruction signal and the address stored in the address register are output to the cache memory device 2 when the bypass flag specifies that prefetch is not to be avoided.
[0052]
In this embodiment, by storing the control method of the cache block (cache bypass) in the address space table, it is possible to perform the cache instruction limited to the cache bypass in the intermittent address space.
[0053]
Embodiment 5 FIG.
Although there is sequentiality and short-term time locality of data, when dealing with extremely large amounts of data, I want to store it in the cache, but once it is stored, all other useful data will be expelled, It returns and degrades performance. In such a case, in a cache memory composed of a plurality of ways, large-scale sequential data can be limited to a specific cache way and stored, thereby restricting eviction of other useful cache blocks. The side effects of performance degradation can be reduced. In the present invention, the cache way can be specified for intermittent address space data by adding a small amount of H / W, and an example thereof is shown in FIGS. 1 and 6 (FIG. 6 shows the fourth embodiment). The same as those shown in). However, in this embodiment, the cache bypass flag column 402f is not used. Therefore, the cache bypass flag column 402f may not be provided in the address space table 402.
[0054]
Next, an operation example will be described.
First, for the address space from 0x123346 to 0x12346FFF, the system is set to store only cache blocks in way 3. It is assumed that the present cache memory has a 4-way configuration and has ways 0 to 3. In this case, for the 0x346th entry of the address space table 402 in FIG. 6, in addition to the effective bit string 402a = 1, the upper address string 402b = 0x12, the way designation flag string 402g = 1, the way number string 402h = 3 Set. When a memory request (address = 0x12346010) is issued from the processor 1 of FIG. 1, the prefetch control mechanism 4 sends a cache instruction signal to the cache memory device 2 via the cache instruction signal line 42 to limit the cache way to three. Put out.
[0055]
The cache memory device 2 receiving this sets the way in the main storage device 3 regardless of whether the data fetched from the main storage device 3 is in the replaced state. In a normal cache memory, when new data is input and old data is expelled, one of four blocks is selected according to an LRU (Least Recent Used) algorithm in the case of 4-way. In the case of the present invention, it is only necessary to add a mechanism for deciding the way as 3 ignoring the result of the LRU, and it can be realized by an easy logical change and a small addition of H / W as shown in FIG.
[0056]
FIG. 6 shows the operation of the prefetch control mechanism 4 having received the memory request in detail. When a memory request (address = 0x12346010) arrives via the memory request signal line 11, the request valid signal 11a = 1, and the desired address (0x12346010) is indicated in the request address signal 11b. The request valid flag register 400 is set to 1, and the address value = 0x12346010 is held in the request address register 401 (upper address field 401a = 0x12, index field 401b = 0x346, lower address field 401c = 0x010).
[0057]
Subsequently, the table of the address space table 402 is retrieved with the value of the index field 401b = 0x346, and the output of the effective bit string 402a (effective flag) and the output of the upper address string 402b (upper address) = 0x12, output of way designation flag string 402g (way designation flag) = 1, and output of way number string 402h (way number) = 3 are output. Since the output of the upper address field 401a and the output of the upper address string 402b match, the output of the comparator 403 = 1, and the output of the way designation flag string 402g = 1, so that the output of the AND circuit 421 = 1 and the cache way 3 A cache way designation signal 42b = 1 and a cache way number signal 42c = 3 instructing writing to the cache memory device 2 are transmitted to the cache memory device 2.
[0058]
According to FIG. 7, when the cache way designation signal 42b = 1, the way to be removed is the way 3 designated by the cache way number signal 42c.
As shown in FIG. 7, a function of selecting a way can be realized by adding a selector 29 to the cache memory device 2. The selector 29 selects a way to be kicked out according to the value of the cache way designation signal 42b.
[0059]
As described above, in the present embodiment, an example of the prefetch function in the case where the information processing apparatus is configured by a plurality of cache memories specified by way numbers has been described.
In the prefetch control mechanism 4, each entry of the address space table 402 further includes a way number field for storing a way number (a way number column 402h is an example) and a way number valid flag indicating that the way number field is valid. (The way designation flag string 402g is an example), the value stored in the first address field (upper address string 402b) (the value to be compared with the address of the upper part) and the address register (request address register 401). When the first prefetch flag (valid bit string 402a) specifies prefetch and the way number valid flag indicates valid, a prefetch instruction signal and the address Caches the address stored in the register An example was described of outputting to the memory device 2.
Also, an example has been described in which the cache memory device 2 has a function of prefetching a cache memory specified by the way number field (adding a selector as an example).
[0060]
In this embodiment, by storing the cache block control method (explicit way specification) in the address space table, it is possible to specify a cache way in a discontinuous address space.
[0061]
Embodiment 6 FIG.
In the embodiments described above, two or more address spaces cannot be set for addresses having the same index part. For example, in the first embodiment, 0x12345000 to 0x12345fff and 0x13345000 to 0x13345fff cannot be set simultaneously. This is because the index 0x345 overlaps. This problem can be solved by a method having two address space tables as shown in FIG. FIG. 8 is provided with another address space table 430 in addition to the functions similar to those of FIG. The address space table 430 includes a valid bit string 430a and an upper address string 430b. Further, a comparison circuit 431, an AND circuit 432, an AND circuit 433, and an OR circuit 434 are added to FIG.
[0062]
Next, an operation example will be described.
First, as a system, an address space from 0x12345000 to 0x12345FFF and an address space from 0x13345000 to 0x13345fff are set as prefetch spaces. In this case, the effective bit string 402a of the 0x345th entry of the address space table 402 in FIG. 8, the upper address string 402b = 0x12, the effective bit string 430a of the 0x345th entry of the address space table 430 = 1, and the upper address field 430b = Set 0x12.
[0063]
FIG. 8 shows the operation of the prefetch control mechanism 4 having received the memory request in detail. When a memory request (address = 0x12345010) arrives via the memory request signal line 11, the request valid signal 11a = 1, and the desired address (0x12345010) is indicated in the request address signal 11b. The request valid flag register 400 is set to 1, and the address value = 0x12345010 is held in the request address register 401 (upper address field 401a = 0x12, index field 401b = 0x345, lower address field 401c = 0x010). Subsequently, the table of the address space table 402 is retrieved with the value of the index field 401b = 0x345, the output of the valid bit string 402a (valid flag) = 1, and the upper address string 402b (higher order) with reference to the 0x345th entry of the address space table 402. Address = 0x12 is output.
[0064]
The upper address column 402b and the upper address field 401a of the result of the address space table 402 are compared by the comparator 403. Since both values are 0x12, the result = 1 is output. Based on the output (valid bit) of the valid bit string 402a and the result, the output of the AND circuit 432 becomes 1, and the output of the OR circuit 434 becomes 1. Since the output of the request valid flag register 400 = 1, the output of the AND circuit 404 = 1, the prefetch valid signal 41a = 1, and the prefetch valid signal is transmitted to the cache memory device 2.
[0065]
When a memory request (address = 0x13345010) arrives via the memory request signal line 11, the request valid signal 11a = 1, and the desired address (0x13345010) is indicated in the request address signal 11b. The request valid flag register 400 is set to 1, and the address value = 0x13345010 is held in the request address register 401 (upper address field 401a = 0x13, index field 401b = 0x345, lower address field 401c = 0x010). Subsequently, the table of the address space table 430 is looked up with the value of the index field 401b = 0x345, and the valid flag = 1 and the upper address = 0x13 are output with reference to the 0x345th of the address space table 430.
[0066]
The upper address column 430b of the result of the address space table 430 is compared with the upper address field 401a by the comparison circuit 431. Since both values = 0x13, the result = 1 is output. Based on the output (valid bit) of the valid bit string 430a and the result, the output of the AND circuit 433 becomes 1 and the output of the OR circuit 434 also becomes 1. Since the output of the request valid flag register 400 = 1, the output of the AND circuit 404 = 1, the prefetch valid signal 41a = 1, and the prefetch valid signal is transmitted to the cache memory device 2. That is, the prefetch valid signal 41a could be output to both the address = 0x12345010 and the address = 0x13345010.
[0067]
The above method has two address space tables and avoids the problem of collision between two identical indexes. In the case of three identical indices, the above method cannot solve the problem, but in such a case, the probability becomes extremely small, and the influence on the performance is considered to be small. Further, by having three address space tables, the problem of three identical indexes can be solved. The problem of collision of N indices can be solved by using an N-side address space table, and N may be determined by a trade-off between performance and cost.
[0068]
In this embodiment, by having a plurality of address space tables, collision of addresses to be set can be avoided, and the degree of freedom in specifying an address space can be increased.
[0069]
Embodiment 7 FIG.
In the above-described embodiment, the 32-bit address of the request address register 401 is described as 8 bits for the upper address field 401a, 12 bits for the index field 401b, and 12 bits for the lower address field 401c. This is just an example, and division by another number of bits is also possible.
[0070]
Although not specified in the first to sixth embodiments, data stored in the address space table 402 is stored before executing the prefetch method and method. The information processing device obtains data to be stored from the input device in advance, and stores the obtained data in the address space table 402.
The input device has a function of inputting data to the information processing device. For example, when data is input by a user from a keyboard, a mouse, or the like, when the information processing apparatus is connected to a communication network, when data is input through the communication network, or when data is recorded on a recording medium. There is a case where data is input through an apparatus for reading data from a recording medium by an information processing apparatus.
[0071]
Embodiment 8 FIG.
Although the prefetch method (information processing device) and the prefetch method using hardware have been described in the above embodiments, the present invention is not limited to this.
The prefetch method can be realized by hardware, firmware, software, or a combination of the above.
Further, the prefetch method can be realized by a program (prefetch program).
[0072]
The prefetch program is executed by an information processing device (computer) including the processor 1, the main storage device 3, and the cache memory device 2, and caches data stored at an address of the main storage device 3 stored in the request address register 401. It instructs to read into the memory device 2 in advance.
The prefetch program is stored in the main storage device 3 of the information processing device, read out to the cache memory device 2 (or equivalent memory), and executed by the processor 1.
[0073]
The prefetch program has the following procedure.
(1) A procedure for setting an address space table 402 having a first prefetch flag for instructing prefetch and a first address field for storing a part of an address of the main storage device 3 before starting prefetch processing.
(2) obtaining data to be stored in the address space table in advance, and storing the obtained data in the address space table 402;
A procedure for setting an address output from the processor to the request address register 401.
(3) A procedure for determining whether or not a part of the address of the request address register 401 matches a part of the address stored in the first address field.
(4) A procedure for judging that the result of the judgment is that the first prefetch flag indicates a prefetch, and that the first prefetch flag indicates a prefetch.
(5) A procedure for outputting the prefetch instruction signal and the address stored in the request address register 401 to the cache memory device 2.
[0074]
The prefetch program can be recorded on a computer-readable recording medium. The prefetch program recorded on the recording medium is read (loaded) into the cache memory device 2 or the like in the same manner as described above, and is executed by the processor 1.
[0075]
【The invention's effect】
In the present invention, the presence / absence of prefetch is stored in the address space table, and the table is searched using a part of the address so that the instruction of the presence / absence of prefetch can be immediately determined. Can be specified for prefetching.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an entire information processing apparatus according to Embodiments 1 to 6 of the present invention.
FIG. 2 is a block diagram illustrating a prefetch control circuit according to the first embodiment of the present invention;
FIG. 3 is a block diagram illustrating a prefetch control circuit according to a second embodiment of the present invention;
FIG. 4 is a waveform diagram illustrating an operation of a prefetch control circuit according to a second embodiment of the present invention.
FIG. 5 is a block diagram illustrating a prefetch control circuit according to a third embodiment of the present invention;
FIG. 6 is a block diagram showing a prefetch control circuit according to the fourth and fifth embodiments of the present invention.
FIG. 7 is a block diagram illustrating an LRU determination circuit of a cache memory device according to a fifth embodiment of the present invention.
FIG. 8 is a block diagram illustrating a prefetch control circuit according to a sixth embodiment of the present invention.
[Explanation of symbols]
1 Processor, 2 cache memory device, 3 main storage device, 4 prefetch control mechanism (prefetch control device), 11 memory request signal line, 11a request valid signal, 11b request address signal, 12 data line, 21 fetch request line, 29 selector , 31 data line, 41 prefetch request signal line, 42 cache instruction signal line, 400 request valid flag register, 401 request address register, 401a upper address field, 401b index field, 401c lower address field, 402 address space table, 402a valid bit string , 402b Upper address column, 402c Block number field column, 402d Conservative prefetch flag column, 402e Previous request lower address column, 40 f Cache bypass flag string, 402g way designation flag string, 402h way number string, 403 comparator, 404 AND circuit, 405 adder, 406 number control circuit, 407 selector, 408 adder, 409 comparator, 410 AND circuit, 411 NOT element, 412 OR circuit, 420 AND circuit, 421 AND circuit, 430 address space table, 430a effective bit string, 430b upper address string, 431 comparison circuit, 432 AND circuit, 433 AND circuit, 434 OR circuit.

Claims (8)

An information processing apparatus comprising a processor, a main storage device, and a cache memory, the information processing device having a prefetch function of instructing to read data stored in the main storage device into the cache memory in advance.
An address register for storing an address of a main storage device output from the processor;
An address space table having a first prefetch flag indicating a prefetch and a first address field storing a predetermined value;
When a part of the address of the address register matches a predetermined value stored in the first address field and the first prefetch flag indicates prefetch, a prefetch instruction signal and the address stored in the address register are used. And a control unit that outputs the data to the cache memory. The address of the main storage device is handled by being divided into three parts, an upper part, a middle part, and a lower part.
The address space table stores the value to be compared with the address of the upper part in the first address field, and sets the number of the middle part as one entry using the first prefetch flag and the first address field as one entry. Has an entry of
2. The information processing apparatus according to claim 1, wherein the control unit searches an entry of the address space table using the middle part as a search key, and instructs prefetch using the detected entry. The cache memory prefetches a storage area of a predetermined size at an address input from the control unit,
Each of the number of entries in the middle part of the address space table further includes a block number field that specifies to prefetch a storage area having a multiple of the predetermined size,
3. The information processing apparatus according to claim 2, wherein the control unit repeats instructing the prefetch using the detected entry by a multiple specified in the block number field. Each of the number of entries in the middle part of the address space table further includes:
A second address field for storing the address of the lower part of the addresses of the main memory previously stored in the address register;
A second prefetch flag that specifies prefetch based on the address of the second address field,
The control unit may use the detected entry to match a value stored in the first address field with a high-order part of the address register and to specify that the first prefetch flag specifies prefetch. Further, the difference between the address of the lower part stored in the second address field and the lower part of the address register is within a predetermined range, and the second prefetch flag specifies prefetch. 3. The information processing apparatus according to claim 2, wherein a prefetch instruction signal and an address stored in the address register are output to the cache memory. Each of the number of entries in the middle part of the address space table further includes:
A bypass flag indicating that the prefetch is avoided,
The control unit may use the detected entry to match a value stored in the first address field with a high-order part of the address register and to specify that the first prefetch flag specifies prefetch. 3. The information processing apparatus according to claim 2, wherein when the bypass flag specifies that prefetch is not to be avoided, a prefetch instruction signal and an address stored in the address register are output to the cache memory. The information processing device includes a plurality of cache memories specified by way numbers,
Each of the number of entries in the middle part of the address space table further includes:
A way number field for storing a way number;
A way number valid flag indicating that the way number field is valid,
The control unit may use the detected entry to match a value stored in the first address field with a high-order part of the address register and to specify that the first prefetch flag specifies prefetch. Outputting the prefetch instruction signal and the address stored in the address register to the cache memory when the way number valid flag indicates valid;
3. The information processing apparatus according to claim 2, wherein the cache memory performs prefetch to a cache memory specified by the way number field. The information processing device includes a plurality of address space tables,
The information processing apparatus according to claim 2, wherein the control unit searches a plurality of address space tables using the middle part as a search key. In a prefetch method in which an information processing device including a processor, a main storage device, and a cache memory instructs to previously read data stored at an address of the main storage device stored in an address register into a cache memory,
The information processing device,
An address space table having a first prefetch flag for instructing prefetch and a first address field for storing a part of an address of the main storage device is provided;
Determining whether a part of the address of the address register matches a part of the address stored in the first address field;
A prefetch method comprising: outputting a prefetch instruction signal and an address stored in the address register to the cache memory when the result of the determination is a match and the first prefetch flag indicates prefetch.

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