JP2004235833A - Phase locked loop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce EMI in a reception band based on a higher harmonics of a clock signal generated from a phase locked loop circuit in a portable telephone device or the like. <P>SOLUTION: The disclosed phase locked loop circuit is constituted with a phrase comparator 1 without a dead zone at the time of detecting phase differences between a dividing signal fp and a reference signal fr, a band limiting part 6 for disconnecting a high frequency component of an output of the detected phase difference of the phase comparator 1, a charge pump 2 for generating a plus or minus output current in accordance with the output of the detected phrase difference from the band limiting part 6, an LPF 3 for integrating the output current of the charge pump 2 and converting it into a voltage, a VCO 4 for generating an oscillation output in which a frequency changes in accordance with an output voltage from the LPF 3, and a frequency divider 5 for dividing an output of the VCO 4 and generating the dividing signal fr. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a phase locked loop circuit capable of adjusting a width of a dead zone of a phase comparator.
[0002]
[Prior art]
A phase locked loop circuit (hereinafter, also referred to as a PLL (Phase Locked Loop) circuit) is a circuit for obtaining an output signal such as a clock synchronized with an external signal, as a mobile communication device, a television device, a BS (Broadcasting Satellite) tuner. , A GPS (Global Positioning System) device, etc., has been widely used as a clock source of a logic control circuit different from a radio unit.
FIG. 8 is a block diagram showing a basic configuration of a conventional PLL circuit, and includes a phase comparator 1, a charge pump 2, an LPF (Lowpass Filter) 3, a VCO A schematic configuration including a (Voltage Controlled Oscillator) 4 and a frequency divider 5 is shown. 8, the phase comparator 1 and the charge pump 2 form a phase difference detection unit 100.
[0003]
In the phase difference detection section 100, the phase comparator 1 compares the phase of the frequency-divided signal fp from the frequency divider 5 with the phase of the external reference signal fr, An UP signal and a DOWN signal having a pulse width corresponding to the phase error are generated. The charge pump 2 generates DC outputs having different pulse widths and directions according to the UP signal and the DOWN signal from the phase comparator 1. The LPF 3 integrates an output from the charge pump 2 and generates a control signal including a DC voltage having a polarity and a magnitude corresponding to a phase error. The VCO 4 outputs a high-frequency signal fo whose frequency changes according to the control signal from the LPF 3. The frequency divider 5 frequency-divides the high-frequency signal fo of the VCO 4 by M (M is a natural number of 2 or more) and outputs a frequency-divided signal fp.
[0004]
In the PLL circuit shown in FIG. 8, the phase comparator 1 compares the phase of the frequency-divided signal fp obtained by dividing the frequency of the output signal fo of the VCO 4 by the frequency divider 5 with the phase of the reference signal fr. Thus, a DC-converted error output is obtained from the phase error output of the comparison result via the charge pump 2. A control signal composed of a DC voltage obtained by integrating the error output via the LPF 3 is fed back to the VCO 4 to control the frequency of the output signal, so that the phase error output of the phase comparator 1 becomes zero. As described above, the feedback control is performed, and the output signal fo in phase with the reference signal fr is obtained from the VCO 4.
[0005]
FIG. 9 shows an example of the configuration of a phase difference detection unit 100 in a conventional PLL circuit, which is, for example, a well-known circuit described in Patent Document 1.
As shown in FIG. 9, in the phase difference detecting section of this conventional example, the phase comparator 1 includes NAND circuits 11 and 12 constituting a first latch circuit and NAND circuits 13 and 12 constituting a second latch circuit. , NAND circuits 15 and 16 forming a third latch circuit, NAND circuits 17 and 18 forming a fourth latch circuit, and a 4-input NAND circuit 19, and the charge pump 2 is configured by a PchMOS transistor. Tr21, an Nch MOS transistor Tr22, and an inverter 23.
[0006]
In the phase comparator 1, when the frequency of the frequency-divided signal fp is lower than the frequency of the reference signal fr, the first latch circuit (11, 12) adjusts the level of the frequency-divided signal fp connected to the set input to the reference signal fr. It is set when the level is lower than fr level to generate a low-level output (UP signal), and is reset when the output of the 4-input NAND circuit 19 or the output of the third latch circuit (15, 16) at the time of setting is low. Generates high-level output.
The second latch circuit (13, 14) operates when the frequency of the reference signal fr is lower than the frequency of the frequency-divided signal fp and the level of the reference signal fr connected to the set input is lower than the level of the frequency-divided signal fp. Set to generate a low-level output (DOWN signal), reset when the output of the 4-input NAND circuit 19 or the output at the time of setting of the fourth latch circuit (17, 18) is low, and generate a high-level output. I do.
[0007]
The third latch circuit (15, 16) is reset by an output at the time of reset of the first latch circuit (11, 12) connected to the reset input, and the four-input NAND connected to the set input. Set by the low level output of the circuit 19.
The fourth latch circuit (17, 18) resets by the output at the time of reset of the second latch circuit (13, 14) connected to the reset input, and the four-input NAND circuit 19 connected to the set input. Set by low-level output.
The four-input NAND circuit 19 includes an output when the first latch circuit (11, 12) and the second latch circuit (13, 14) are set, a third latch circuit (15, 16), and a fourth latch circuit. When the output of the circuit (17, 18) at the time of reset coincides, a low level is output.
[0008]
In the charge pump 2, when receiving the UP signal (low level) from the phase comparator 1, the Tr 21 causes a current to flow from the power supply Vcc to the LPF 3 via the terminal CPout in accordance with the pulse width of the UP signal. When receiving the DOWN signal (low level) from the phase comparator 1, the inverter 23 inverts the inverted signal and outputs a high-level signal. When the Tr 22 receives the high-level signal from the inverter 23, the Tr 22 connects the terminal CPout to the terminal CPout. After that, a current flows from the LPF 3 to the ground (GND) in accordance with the pulse width of the DOWN signal.
[0009]
FIG. 10 shows the output characteristics of the phase difference detecting section in the case of a small phase difference in the conventional PLL circuit. The output current when the phase difference changes is centered on the point where the phase difference is zero. As a result, there is no dead zone in which the output current does not change even when the phase difference changes linearly with the change in the positive or negative direction and the phase difference is small.
At this time, in order to eliminate the dead zone, the change of the feedback signal from the 4-input NAND circuit 19 of the phase comparator 1 is delayed to some extent with respect to the change of the reference signal fp and the divided signal fr. For this reason, usually, an element is made to have an appropriate output delay time characteristic by increasing the gate width of the MOS transistor constituting the 4-input NAND circuit 19.
[0010]
[Patent Document 1]
Toshiyuki Ozawa: "PLL frequency synthesizer circuit design method", Sogo Denshi Publishing Co., Ltd. (pp. 126-131)
[Patent Document 2]
JP-A-2000-252817
[Patent Document 3]
JP-A-2001-156626
[Patent Document 4]
JP 2001-156629 A
[Patent Document 5]
JP-A-08-213905
[Patent Document 6]
JP-A-10-126259
[Patent Document 7]
JP-A-10-327070
[Patent Document 8]
JP-A-11-220387
[0011]
[Problems to be solved by the invention]
In the conventional PLL circuits shown in FIGS. 8 and 9, in order to minimize the jitter of the clock signal output from the VCO 4, the dead zone of the phase comparator 1 is eliminated and the transfer characteristics (unity gain, angular frequency , Phase margin) are designed to be more stable.
Therefore, although the jitter is reduced, the harmonic component of the output clock signal becomes large, and if the harmonic component is present in the reception band of a mobile phone device or the like, the audible sound is generated in the received voice where transmission and reception cannot be performed. EMI may cause a reception interference problem (Electromagnetic Interference: EMI).
[0012]
The present invention has been made in view of the above-described circumstances, and in a mobile phone device or the like, it is possible to prevent generation of EMI based on harmonics of a clock signal output from a phase locked loop circuit. It is intended to provide a synchronous loop circuit.
[0013]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention according to claim 1 relates to a phase locked loop circuit, comprising: a phase comparison unit having no dead zone when detecting a phase difference between a divided signal and a reference signal; Band limiting means for cutting off the high frequency component of the detection output, charge pump means for generating a positive or negative output current in response to the phase difference detection output from the band limiting means, and integrating the output current of the charge pump means. Low-pass filtering means for converting the output of the voltage-controlled oscillating means into a voltage, a voltage-controlled oscillating means for generating an oscillation output whose frequency changes according to the output voltage of the low-pass filtering means, And frequency dividing means for generating the frequency-divided signal.
[0014]
According to a second aspect of the present invention, there is provided the phase locked loop circuit according to the first aspect, wherein the band limiting means includes a plurality of low-frequency bands having sequentially different cutoff characteristics according to each of a plurality of control inputs. It is characterized in that it comprises a circuit for selecting one of the pass-through filters and connecting it between the input terminal and the output terminal.
[0015]
According to a third aspect of the present invention, there is provided the phase locked loop circuit according to the second aspect, wherein the band limiting means includes a plurality of switch means selectively turned on in response to each of a plurality of control inputs. On the other hand, a number of resistive elements increasing in sequence from zero to one by one are connected in series to the respective switch means, and one ends of the plurality of series circuits are connected in parallel to serve as input terminals. And a circuit in which the other end is connected in parallel to form an output terminal, and a capacitor is connected in parallel between the output terminal and ground.
[0016]
Further, the invention according to claim 4 relates to a phase locked loop circuit, comprising: a phase comparison means with dead zone adjustment capable of adjusting a width of a dead zone when detecting a phase difference between a divided signal and a reference signal; Charge pump means for generating a positive or negative output current in accordance with the phase difference detection output of the means, low-pass filtering means for integrating the output current of the charge pump means and converting it to a voltage, and low-pass filtering A voltage controlled oscillating means for generating an oscillation output whose frequency changes according to an output voltage of the means, and a frequency dividing means for dividing the output of the voltage controlled oscillating means to generate the frequency-divided signal. And
[0017]
According to a fifth aspect of the present invention, there is provided the phase locked loop circuit according to the fourth aspect, wherein the phase comparing means with dead zone adjustment is set when the frequency of the divided signal is lower than the frequency of the reference signal. A first latch circuit which generates an output signal and is reset by the output of the 4-input coincidence detecting means or the output when the third latch circuit is set, and set when the frequency of the reference signal is lower than the frequency of the divided signal. A second latch circuit that generates a second output signal and is reset by an output of the four-input coincidence detection means or an output when the fourth latch circuit is set; and a reset when the first latch circuit is reset; A third latch circuit that is set when the output of the four-input coincidence detecting means is generated, and is reset when the second latch circuit is reset, and is output when the output of the four-input coincidence detecting means is generated The output of the fourth latch circuit to be reset, the output of the first latch circuit and the second latch circuit at the time of setting, and the output of the third latch circuit and the fourth latch circuit at the time of reset coincide with each other. When the four-input coincidence detecting means for generating an output, the output terminal of the four-input coincidence detecting means, and the delay selecting means inserted between the set input terminals of the third latch circuit and the fourth latch circuit, It is characterized by becoming.
[0018]
According to a sixth aspect of the present invention, there is provided the phase locked loop circuit according to the fourth or fifth aspect, wherein the delay selecting means has a plurality of delay characteristics having sequentially different delay characteristics according to each of the plurality of control inputs. It is characterized by comprising a circuit for selecting one of the delay circuits and connecting between the input terminal and the output terminal.
[0019]
According to a seventh aspect of the present invention, there is provided the phase locked loop circuit according to the sixth aspect, wherein the delay selecting means includes a plurality of switch means selectively turned on in response to each of a plurality of control inputs. On the other hand, a number of buffer circuits increasing in sequence from zero to one by one in series is connected to each switch means, and one end of each of the plurality of series circuits is connected in parallel to serve as an input terminal. And the other end is connected in parallel to form an output end.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The description will be made specifically using an embodiment.
◇ First embodiment
FIG. 1 is a block diagram showing a configuration of a phase locked loop circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a phase difference detection unit in the phase locked loop circuit of the present embodiment. 3 is a circuit diagram showing a specific configuration of an LPF circuit in the band limiting section of the present embodiment, and FIG. 4 shows a phase difference versus output current characteristic in the case of a small phase difference in the phase difference detecting section of the present embodiment. FIG.
[0021]
As shown in FIG. 1, the PLL circuit of this example is schematically composed of a phase comparator 1, a charge pump 2, an LPF 3, a VCO 4, a frequency divider 5, and a band limiting unit 6. In FIG. 1, the phase comparator 1, the charge pump 2, and the band limiting section 6 constitute a phase difference detecting section 101.
FIG. 2 shows a specific configuration of the phase difference detection unit 101 including the phase comparator 1, the charge pump 2, and the band limiting unit 6.
In the phase locked loop circuit of this example, the phase comparator 1, the charge pump 2, the LPF 3, the VCO 4, and the frequency divider 5 are the same as those of the conventional example shown in FIG. Detailed description is omitted.
[0022]
In the band limiter 6, the first LPF circuit 61 and the second LPF circuit 62 have the same configuration, and therefore, the configuration and operation of only the LPF circuit 61 will be described below. .
As shown in FIG. 3, the LPF circuit 61 includes switches SW610, SW611, SW612,..., SW61n, resistors R611, R612,.
[0023]
The capacitor C61 is connected in parallel between the output OUT of the LPF circuit 61 and the ground. The switch SW610 is turned on in response to an input from the terminal D1, and connects between the input IN and the output OUT of the LPF circuit 61. The switch SW611 is turned on in response to the input from the terminal D2, and connects the resistor R611 in series between the input IN and the output OUT. The switch SW612 is turned on in response to the input from the terminal D3, and connects the resistor R612 in series between the input IN and the output OUT. Hereinafter, similarly, the switch SW61n is turned on in response to the input from the terminal Dn, and connects the resistor R61n in series between the input IN and the output OUT.
[0024]
In the LPF circuit shown in FIG. 3, by providing N-bit parallel data to the terminals D1, D2, D3,..., Dn, for example, when the switch SW610 is on, the input IN and the output OUT are short-circuited to ground. A low-pass filter composed of a resistor R611 and a capacitor C61 is connected between the input IN and the output OUT when the switch SW611 is on, and a resistor is connected between the input IN and the output OUT when the switch SW612 is on. A low-pass filter composed of R612 and a capacitor C61 is connected. Similarly, when the switch SW61n is turned on, a low-pass filter composed of a resistor R61n and a capacitor C61 is connected between the input IN and the output OUT. Further, when a plurality of switches are turned on, a plurality of resistors connected by the switches are connected in parallel to form a low-pass filter including the capacitor C61. Thus, a low-pass characteristic according to the inputs of the terminals D1, D2, D3,..., Dn can be realized between the input IN and the output OUT.
[0025]
Hereinafter, the operation of the PLL circuit of this example will be described with reference to FIGS.
In the PLL circuits shown in FIGS. 1 to 3, the phase of the frequency-divided signal fp obtained by dividing the frequency of the output signal fo of the VCO 4 by the frequency divider 5 in the phase comparator 1 and the phase of the reference signal fr To obtain a DC-converted error output from the phase error output of the comparison result via the charge pump 2, and a control signal composed of a DC voltage obtained by integrating the error output via the LPF 3 to the VCO 4. The feedback control is performed so that the phase error output of the phase comparator 1 becomes zero by feeding back and controlling the frequency of the output signal, and an output signal fo in phase with the reference signal fr is obtained from the VCO 4. At this time, by providing N-bit parallel data to the terminals D1, D2, D3,..., Dn, the phase error output from the NAND circuit 12 of the phase comparator 1 and the phase error from the NAND circuit 14 are output. The differential output, is band-limited in accordance with the low-pass characteristics of the LPF circuit 61 and 62 respectively, are cut off high-frequency components.
[0026]
The phase error output from the phase comparator 1 has a wide pulse width when the phase synchronization operation of the PLL circuit does not converge, and therefore, the frequency component of the phase error output has many low frequency components. On the other hand, when the phase synchronization operation of the PLL circuit approaches convergence, the pulse width becomes narrow, and therefore, the frequency component of the phase error output increases in high frequency components.
Therefore, the high frequency component of the phase error output from the phase comparator 1 is attenuated by the PLL circuits 61 and 62, and only the low frequency component is passed to the charge pump 2 so as to be supplied to the charge pump 2. By providing a dead zone in the output, the UP signal and the DOWN signal can be prevented from being output in a state where the phase difference between the reference signal fp and the frequency-divided signal fr is reduced.
[0027]
In this case, the output characteristics of the phase difference detection unit 101 in the case of a small phase difference are as shown in FIG. 4, and within a certain range centering on the case of a phase difference of 0, there is a dead zone where no output current exists. It exists.
Since the width of the dead zone in this case is determined by the cutoff characteristics of the LPF circuits 61 and 62, by setting N-bit parallel data given to the terminals D1, D2, D3,..., Dn, for example, in FIG. As shown by B1, B2, and B3, the width of the dead zone can be arbitrarily adjusted.
[0028]
When a dead band is provided in the phase-locked operation of the PLL circuit as in this example, the frequency of the clock signal generated from the VCO fluctuates without stability within the range of the dead band. Also fluctuates. Therefore, since the spectrum of the harmonics falling in the reception band is spread, the peak of the EMI based on the harmonics of the clock signal in the portable telephone device or the like is reduced.
The width of the dead zone in this case can be adjusted to an arbitrary type by appropriately setting externally applied N-bit parallel data so that the fluctuation of the clock signal frequency does not adversely affect the operation of the logic circuit. can do.
[0029]
As described above, in the PLL circuit of this example, by inserting the band limiting unit including the LPF circuit into the output of the phase comparator and intentionally providing the dead zone in the phase synchronization operation, a logic that does not require much frequency accuracy is provided. Since the clock signal of the circuit has jitter to spread the spectrum of the harmonics of the clock signal in the reception band, EMI based on the harmonics of the clock signal can be effectively reduced.
[0030]
◇ Second embodiment
FIG. 5 is a block diagram illustrating a configuration of a phase locked loop circuit according to a second embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a configuration of a phase difference detection unit in the phase locked loop circuit of the present embodiment. FIG. 7 is a circuit diagram showing a specific configuration example of the delay selection circuit in the phase comparator of the present embodiment.
[0031]
As shown in FIG. 5, the PLL circuit of this example is schematically composed of a phase comparator with dead zone adjustment 1A, a charge pump 102, an LPF 3, a VCO 4, and a frequency divider 5. In FIG. 5, the phase comparator 1A and the charge pump 2 constitute a phase difference detection unit 102.
In the phase locked loop circuit of this example, the charge pump 2, LPF 3, VCO 4, and frequency divider 5 are the same as those in the conventional example shown in FIG. 8, and therefore, detailed description thereof will be omitted below. .
[0032]
In the phase difference detecting section 102, the phase comparator with dead zone adjustment 1A includes NAND circuits 11 and 12 forming a first latch circuit and NAND circuits 13 and 12 forming a second latch circuit, as shown in FIG. 14, NAND circuits 15 and 16 forming a third latch circuit, NAND circuits 17 and 18 forming a fourth latch circuit, a 4-input NAND circuit 19A, and a delay selecting circuit 20. Of these, NAND circuits 11 and 12 forming the first latch circuit, NAND circuits 13 and 14 forming the second latch circuit, NAND circuits 15 and 16 forming the third latch circuit, and the fourth latch Since the configuration of the NAND circuits 17 and 18 constituting the circuit is the same as that of the conventional example shown in FIG. 9, detailed description thereof will be omitted below.
[0033]
In the phase comparator with dead zone adjustment 1A, the four-input NAND circuit 19A is constructed by reducing the gate width of the MOS transistor constituting the element so that the delay time characteristic of the four-input NAND circuit itself is reduced in advance. Have been.
The delay selection circuit 20 is connected between a connection point between the output of the 4-input NAND circuit 19A in the phase comparator 1A and the NAND circuit 15 of the third latch circuit and the NAND circuit 17 of the fourth latch circuit, As shown in FIG. 7, switches SW200, SW201, SW202, SW203,..., SW20n, and buffers B201, B2021, B2022, B2031, B2032, B2033,.
[0034]
The switch SW200 is turned on in response to the input from the terminal D1, and connects between the input IN and the output OUT of the delay selection circuit 20. The switch SW201 is turned on in response to the input from the terminal D2, and connects the buffer B201 between the input IN and the output OUT. The switch SW202 is turned on in response to the input from the terminal D3, and connects the buffers B2021 and B2022 in series between the input IN and the output OUT. The switch SW203 is turned on in response to the input from the terminal D4, and connects the buffers B2031, B2032, and B2033 in series between the input IN and the output OUT. Hereinafter, similarly, the switch SW20n is turned on in response to the input from the terminal Dn, and connects the buffers B20n1,..., B20nn in series between the input IN and the output OUT.
[0035]
In the delay selection circuit 20 shown in FIG. 7, by providing N-bit parallel data to the terminals D1, D2, D3,..., Dn, for example, when the switch SW200 is on, the input IN and the output OUT are short-circuited, When the switch 201 is on, the buffer B201 is connected between the input IN and the output OUT. When the switch SW202 is on, the buffers B2021, B2022 are connected between the input IN and the output OUT. Depending on the input of Dn, different types of delay time characteristics are realized between the input IN and the output OUT by short-circuiting the input IN and the output OUT or connecting a different number of buffers in series.
[0036]
Hereinafter, the operation of the PLL circuit of this example will be described with reference to FIGS.
In the PLL circuits shown in FIGS. 5 to 7, in the phase comparator with dead zone adjustment 1A, a frequency-divided signal fp obtained by dividing the frequency of the output signal fo of the VCO 4 by the frequency divider 5 and a reference signal fr Is obtained from the phase error output of the comparison result through the charge pump 2 to obtain a DC-converted error output, and a control signal composed of a DC voltage obtained by integrating the error output via the LPF 3 is output. By feedback to the VCO 4 to control the frequency of the output signal, feedback control is performed so that the phase error output of the phase comparator 1A becomes zero, and the output signal fo from the VCO 4 is phase-synchronized with the reference signal fr. At this time, by providing N-bit parallel data to the terminals D1, D2, D3,..., Dn, the output of the 4-input NAND circuit 19A in the phase comparator with dead zone adjustment 1A is obtained. Delay time between a connection point between the NAND circuit 17 of the NAND circuit 15 and a fourth latch circuit of the first latch circuit is changed depending on the delay characteristics of the delay selection circuit 20 at that time.
[0037]
In the phase difference detection unit 102, the delay signal of the delay selection circuit 20 is large by delaying the feedback signal from the four-input NAND circuit 19A in the delay selection circuit 20 and applying it to the connection point between the NAND circuit 15 and the NAND circuit 17. The reset timing of the third latch circuit composed of the NAND circuits 15 and 16 and the reset timing of the fourth latch circuit composed of the NAND circuits 16 and 17 are smaller than the timing of detecting the phase difference in the phase comparator with dead zone adjustment 1A. As a result of the delay, the width of the dead zone between the UP signal and the DOWN signal output from the phase difference detection unit 102 tends to decrease. Conversely, when the delay time of the delay selection circuit 20 is short, the dead zone of the phase difference detection unit 102 is reduced. Becomes wider.
[0038]
Therefore, by setting N-bit parallel data to be applied to the delay selection circuit 20, a dead zone having an appropriate width is provided in the output of the phase difference detection unit 102, and the phase difference between the divided signal fr and the reference signal fp is reduced to some extent. In this state, the UP signal and the DOWN signal can be prevented from being output.
At this time, the output characteristic of the phase difference detection unit 102 in the case of a minute phase difference is similar to that shown in FIG. 4, and there is no output current within a certain range centering on the case of a phase difference of 0. There will be a dead zone.
Since the width of the dead zone in this case is determined by the delay time characteristic given by the delay selection circuit 20, by setting N-bit parallel data given to the terminals D1, D2, D3,. 4, the width of the dead zone can be arbitrarily adjusted as indicated by B1, B2, and B3.
[0039]
When a dead band is provided in the phase-locked operation of the PLL circuit as in this example, the frequency of the clock signal generated from the VCO fluctuates without stability within the range of the dead band. Also fluctuates. Therefore, since the spectrum of the harmonics falling in the reception band is spread, the peak of the EMI based on the harmonics of the clock signal in the portable telephone device or the like is reduced as in the case of the first embodiment. By setting N-bit parallel data supplied from the outside, the width of the dead zone can be adjusted to any type within a range in which the fluctuation of the clock signal frequency does not adversely affect the operation of the logic circuit.
[0040]
As described above, in the PLL circuit of this example, by adjusting the delay time characteristic of the delay selection circuit in the phase comparator and intentionally providing a dead zone in the phase synchronization operation, a logic circuit that does not require much frequency accuracy is provided. Is given a jitter to spread the spectrum of the harmonics of the clock signal within the reception band, so that EMI based on the harmonics of the clock signal can be effectively reduced.
In the case of the first embodiment, the band limiting unit needs two LPF circuits, and it is necessary to match the band cutoff characteristics of the two LPF circuits. Since there is only one adjustment circuit, the element area can be reduced, and there is no problem that the characteristics of the two circuits need to be relatively matched.
[0041]
As described above, the embodiments of the present invention have been described in detail with reference to the drawings. Included in the invention. For example, in the first embodiment, the phase comparator having no dead zone is not limited to the circuit shown in FIG. 2, but has a specific polarity according to the level of the frequency between the frequency-divided signal and the reference signal. Any circuit type may be used as long as it can output the phase difference detection signal. Also, the phase comparator has been described as being composed of a NAND circuit, but is not limited to this, and may use other circuit elements, and the logic is not limited to negative logic and may be positive logic. .
[0042]
【The invention's effect】
As described above, according to the phase locked loop circuit of the present invention, in the phase difference detection section, a dead zone is provided in the operation thereof, and the phase difference detection output is provided in a range where the phase difference between the divided signal and the reference signal is small. The clock signal supplied to the logic control circuit, which does not require much frequency stability of the clock signal, can have a certain amount of jitter to spread the spectrum of the harmonics of the clock signal. Therefore, it is possible to reduce EMI generated in a reception band in a mobile phone device or the like.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a phase locked loop circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a phase difference detection unit in the phase locked loop circuit of the embodiment.
FIG. 3 is a circuit diagram showing a specific configuration of an LPF circuit in the band limiting section of the embodiment.
FIG. 4 is a diagram showing a phase difference versus output current characteristic in the case of a small phase difference in the phase difference detection section of the embodiment.
FIG. 5 is a block diagram showing a configuration of a phase locked loop circuit according to a second embodiment of the present invention.
FIG. 6 is a circuit diagram showing a configuration of a phase difference detection unit in the phase locked loop circuit of the embodiment.
FIG. 7 is a circuit diagram showing a specific configuration example of a delay selection circuit in the phase comparator of the embodiment.
FIG. 8 is a block diagram showing a basic configuration of a conventional phase locked loop circuit.
FIG. 9 is a circuit diagram illustrating a configuration example of a phase difference detection unit in a conventional phase locked loop circuit.
FIG. 10 is a diagram illustrating phase difference versus output current characteristics in the case of a small phase difference in a conventional phase difference detection unit.
[Explanation of symbols]
1 phase comparator (phase comparing means)
1A Phase comparator with dead zone adjustment (Phase comparison means with dead zone adjustment)
11, 12, 13, 14, 15, 16, 17, 18 NAND circuit
19, 19A 4-input NAND circuit (4-input coincidence detecting means)
20 Delay adjustment circuit (delay selection means)
2 Charge pump (charge pump means)
21 PchMOS transistor
22 NchMOS transistor
23 Inverter
3 LPF (low-pass filtering means)
4 VCO (voltage controlled oscillator)
5 Divider (dividing means)
6 Band limiter (band limiter)
61 LPF circuit
62 LPF circuit
101,102 phase difference detection unit

Claims (7)

Phase comparing means having no dead zone when detecting a phase difference between the frequency-divided signal and the reference signal; a band limiting means for cutting off a high frequency component of a phase difference detection output of the phase comparing means; and a phase difference from the band limiting means. Charge pump means for generating a positive or negative output current in accordance with the detected output, low-pass filtering means for integrating the output current of the charge pump means and converting the same into a voltage, and output voltage of the low-pass filtering means Phase-synchronized means comprising: a voltage-controlled oscillating means for generating an oscillating output whose frequency changes in accordance with a frequency-divided signal; Loop circuit. The band limiting means comprises a circuit for selecting one of a plurality of low-pass filtering circuits having sequentially different cutoff characteristics according to each of a plurality of control inputs and connecting between the input terminal and the output terminal. 2. The phase locked loop circuit according to claim 1, wherein: For a plurality of switch means, wherein the band limiting means is selectively turned on in response to each of a plurality of control inputs, a number of resistors increasing in sequence from zero to one in series with each switch means. And connecting one end of each of the plurality of series circuits in parallel as an input end, and connecting the other end in parallel as an output end, and connecting the output end to ground. 3. The phase-locked loop circuit according to claim 2, comprising a circuit in which a capacitance element is connected in parallel. A phase comparison unit with dead zone adjustment capable of adjusting the width of a dead band when detecting a phase difference between the frequency-divided signal and the reference signal, and a positive or negative output current according to the phase difference detection output of the phase comparison unit with dead zone adjustment. Charge pump means, a low-pass filtering means for integrating the output current of the charge pump means and converting it to a voltage, and an oscillation output whose frequency changes according to the output voltage of the low-pass filtering means. A phase-locked loop circuit comprising: voltage-controlled oscillation means; and frequency-dividing means for dividing the output of the voltage-controlled oscillation means to generate the frequency-divided signal. The dead band adjustment phase comparison means,
A first latch which is set when the frequency of the frequency-divided signal is lower than the frequency of the reference signal to generate a first output signal, and which is reset by the output of the four-input coincidence detecting means or the output of the third latch circuit when set; Circuit and
A second latch which is set when the frequency of the reference signal is lower than the frequency of the frequency-divided signal to generate a second output signal, and which is reset by the output of the four-input coincidence detecting means or the output of the fourth latch circuit at the time of setting; Circuit and
A third latch circuit that resets when the first latch circuit resets and sets when the output of the four-input coincidence detecting means is generated;
A fourth latch circuit that resets when the second latch circuit resets and sets when the output of the four-input coincidence detecting means is generated;
4-input match detection for generating an output when an output at the time of setting of the first latch circuit and the second latch circuit matches an output at the time of resetting of the third latch circuit and the fourth latch circuit. Means,
5. The phase synchronization according to claim 4, further comprising an output terminal of said four-input coincidence detecting means and a delay selecting means inserted between a set input terminal of said third latch circuit and a set input terminal of said fourth latch circuit. Loop circuit. The delay selecting means comprises a circuit which selects one of a plurality of delay circuits having sequentially different delay characteristics according to each of a plurality of control inputs and connects between the input terminal and the output terminal. The phase-locked loop circuit according to claim 4 or 5, wherein For a plurality of switch means, wherein the delay selection means is selectively turned on in response to each of a plurality of control inputs, a number of buffers sequentially increasing by one from zero in series with each switch means. A circuit is connected, and one end of each of the plurality of series circuits is connected in parallel to serve as an input terminal, and the other end is connected in parallel to constitute an output terminal. The phase-locked loop circuit according to claim 6.

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