JP2004235334A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device which is reduced in device size and can modulate a gain factor and can ensure the modulation degree of the gain factor regardless of conductance in a gate region. <P>SOLUTION: On both end sides of gate in the lengthwise direction of a gate region 1 of a MOS (metal oxide semiconductor) transistor, i.e., on a source region 2 side and a drain region 3 side, a control gate 5 is installed which forms a control gate channel region 6 along with gate width direction and over full width. A threshold value in the control gate channel region 6 has heterogeneity which changes continuously or stepwise with one direction change property from one end toward the other end in the gate width direction. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device capable of modulating a gain coefficient of a field-effect transistor, and more particularly to a future large-scale and highly integrated semiconductor integrated circuit (LSI) device by optimizing each chip after manufacturing the LSI. The present invention relates to a semiconductor device as a basic device for realizing a new type of LSI device such as a self-optimizing LSI or a self-adaptive LSI realizing high performance.
[0002]
[Prior art]
In recent LSI devices, with the progress of miniaturization of elements, large-scale and high-integration has progressed, and the realization of a system-on-chip has become a reality, and it is essential to integrate a large number of various functional circuits inside a chip. Was. In the design of such a large-scale LSI device, it is particularly important to optimize and adjust the operation timing and the like between the functional circuits in order to correctly operate a large number of integrated functional circuits.
[0003]
On the other hand, for over 30 years since the invention, the performance of LSI devices has been improved mainly by miniaturization of elements. However, recently, various physical limitations have become apparent in miniaturization of elements, It is becoming extremely difficult to produce a stable and homogeneous product.
[0004]
As a result, in designing an LSI device, it is necessary to take measures to secure an operation margin in order to cover process fluctuations that cannot be avoided in the LSI manufacturing process. The measures for securing the operation margin have hampered the further enhancement of the performance of large-scale LSI devices with the diversification and large-scale of the functions integrated in the LSI devices.
[0005]
As described above, in future LSI devices, non-uniformity of device characteristics having individuality for each LSI chip, such as variation (distribution) of device characteristics in a chip and median value shift (shift) of device characteristics due to process variation. And the accompanying difficulty in LSI physical design (performance optimizing design) has become apparent, and techniques for improving the performance of LSI devices relying only on miniaturization of elements are approaching their limits.
[0006]
Therefore, in order to promote the high performance of LSI devices in the future, it is indispensable to establish a new LSI design / manufacturing method on the premise of a somewhat large variation in element characteristics. One approach to LSI design / manufacturing on the premise of a somewhat large variation in element characteristics is to incorporate a self-adjustment function in the LSI chip itself.
[0007]
Specifically, the electric characteristics adjustment based on the setting of the size (gate length and gate width) of each transistor, which has been performed in the conventional final stage of LSI design (physical design), is automatically performed by the chip itself for each chip after the LSI is manufactured. This is a method of optimizing the electrical characteristics of individual transistors in an LSI chip and improving the chip performance.
[0008]
In order for the LSI chip itself to realize the self-adjustment function, it is necessary to incorporate a mechanism in the LSI chip that can automatically adjust the electric characteristics by a program or electric dynamics. Therefore, in order to realize the method, at least some means for electrically modulating the electric characteristics is indispensable, and the technical development thereof is the key to realizing the self-adjustment function.
[0009]
Hereinafter, an electric modulation method of electric characteristics which can be realized by using the related art will be described. In the prior art, when electrically modulating the electric characteristics, a method mainly using a circuit configuration and a method of modulating the characteristics of the element itself can be adopted.
[0010]
(I) As a method based on a circuit configuration, for example, as shown in (Ia) to (Id), a plurality of field effect transistors (hereinafter, referred to as “MOS transistors”) are used, and the number of parallel connections is determined by an electrical switch. A method of switching circuit configuration is conceivable. According to this, it is possible to modulate the effective electrical characteristics (gain coefficient) when the entire circuit is regarded as one transistor. However, this circuit-based method is extremely inefficient in terms of adjustment accuracy and circuit scale, as described below.
[0011]
(Ia) Two MOS transistors are connected in parallel, a normal signal voltage is applied to the gate electrode of one MOS transistor, and an OFF voltage for turning off the signal voltage by a switch is applied to the gate electrode of the other MOS transistor. Consider a configuration that switches and gives.
[0012]
According to this configuration, in a state where the switch connects the signal voltage to the gate electrode of the other MOS transistor, in this circuit, two MOS transistors connected in parallel function as one MOS transistor. When the switch connects the OFF voltage to the gate electrode of the other MOS transistor, only one of the MOS transistors operates in this circuit. Thereby, the substantial gain coefficient of the MOS transistor can be modulated.
[0013]
(Ib) Five MOS transistors are connected in parallel, a normal signal voltage is applied to the gate electrode of one MOS transistor, and a signal voltage and OFF are respectively applied to the gate electrodes of the remaining four MOS transistors by switches. Consider a configuration in which voltage and voltage are switched and applied.
[0014]
According to this configuration, 16 variations can be realized depending on the states of the four switches. That is, by setting the gain coefficient of each of the four MOS transistors to a power of 2, it is possible to make the coefficient values in 16 steps at equal intervals.
[0015]
(Ic) Two MOS transistors are connected in series, a normal signal voltage is applied to the gate electrode of one MOS transistor, and an ON voltage for turning on the signal voltage by a switch is applied to the gate electrode of the other MOS transistor. Consider a configuration that switches and gives.
[0016]
According to this configuration, in a state where the switch connects the signal voltage to the gate electrode of the other MOS transistor, this circuit has two MOS transistors connected in series and performs the same operation. Works as a MOS transistor. When the switch connects the ON voltage to the gate electrode of the other MOS transistor, this circuit functions as a circuit in which one MOS transistor is connected in series with the ON resistance of the other MOS transistor.
[0017]
(Id) Two MOS transistors are connected in series, a normal signal voltage is applied to the gate electrode of one MOS transistor, and a control voltage for varying the ON resistance value is applied to the gate electrode of the other MOS transistor. Consider the configuration to give. This circuit functions as a circuit for adjusting the resistance value connected in series to one MOS transistor.
[0018]
Here, the switch is usually composed of a CMOS switch in which a PMOS transistor and an NMOS transistor are connected in parallel, an inverter for generating a gate signal thereof, and a latch circuit for holding a state of the switch. MOS transistors are required.
[0019]
Therefore, in the circuit configuration example of the parallel connection shown in (Ia) and (Ib), there is a trade-off relationship between the accuracy of the characteristic adjustment and the circuit scale. Therefore, there is a problem that the circuit scale increases in order to increase the adjustment accuracy. is there.
[0020]
In addition, in the circuit configuration example by series connection shown by (Ic) and (Id), in addition to the problem that the circuit scale becomes large, since a resistance component having a non-linear characteristic with respect to an input signal is interposed in series, the effective The problem is that the characteristic adjustment range is limited.
[0021]
As described above, the method of modulating the electrical characteristics of the transistor by the circuit configuration has an inherent limitation that the number of elements to be adjusted must be several times to several tens times, and the high integration is promoted. However, it is difficult to adapt to the implementation of a self-adjustment function for the purpose of improving the performance of LSI devices.
[0022]
(II) In the conventional MOS transistor, it is not easy to change the electric characteristics after manufacturing the LSI, but the electric characteristics of the element itself can be modulated by operating the back gate voltage. First, the electrical characteristics of a MOS transistor will be outlined.
[0023]
The electrical characteristics of the MOS transistor are determined by using a source / drain current Ids, a source / drain voltage Vds, a gate voltage Vgs, a threshold voltage Vt, and a gain coefficient β.
Vds>Vgs−Vt; Ids ≒ β (Vgs−Vt) ² /2...(1)
Vds ≦ Vgs−Vt; Ids ≒ β ((Vgs−Vt) Vds−Vds ² / 2)… (2)
It can be expressed as. Equations (1) and (2) show a case without a short channel effect or the like for simplicity.
[0024]
The gain coefficient β is calculated using the gate width W, gate length L, gate insulating film thickness Tox, carrier mobility μ, and dielectric constant ε of the gate insulating film.
β ≒ μεW / (L ・ Tox)… (3)
It can be expressed as.
[0025]
As can be understood from the equations (1) and (2), the electrical characteristics of the MOS transistor depend on the threshold voltage Vt. After manufacturing the LSI, the threshold voltage Vt can be changed by manipulating the back gate voltage. Therefore, as a method of changing the electric characteristics of the MOS transistor after manufacturing the LSI by using the conventional technique, it is conceivable to modulate the threshold voltage Vt by changing the back gate voltage.
[0026]
However, the back gate voltage needs to maintain the reverse bias relationship with the source / drain voltage, and it is necessary to electrically separate the back gate voltage for each element to be modulated. Not suitable.
[0027]
Moreover, since the change in the threshold voltage Vt can affect the source / drain current Ids only by the difference from the gate voltage Vgs, the electric characteristics of the MOS transistor can be dynamically modulated only by changing the threshold voltage Vt. It is difficult.
[0028]
In other words, the transistor electric characteristic modulation method by changing the threshold voltage Vt using the conventional technique promotes high integration and enhances the performance of LSI devices due to the hindrance of the integration degree and the weakness of the modulation degree due to the back gate separation. It is unfamiliar with the intended self-adjustment function implementation.
[0029]
As described above, in the conventional technology, it is not easy to incorporate the self-adjustment function in a highly integrated manner and to change the electrical characteristics after manufacturing the LSI. Therefore, development of a new element that does not hinder high integration and enables dynamic electrical characteristic modulation is desired.
[0030]
Here, in equation (3), generally, the carrier mobility μ, the dielectric constant ε, and the gate insulating film thickness Tox are constant, so that the gain coefficient β can be set by the ratio of the gate width W to the gate length L. it can. Therefore, the electrical characteristic of the MOS transistor that can be set in the physical design of the LSI device is the gain coefficient β.
[0031]
If this gain coefficient β can be modulated, as can be understood from the above equations, it is possible to strongly influence the source / drain current Ids in proportion to the product of the gate voltage Vgs. Characteristics can be dynamically modulated. In other words, if the gain coefficient β can be electrically modulated by several times to several tens times, it becomes possible to correct element characteristics variation comparable to that and automatically compensate for load fluctuations after manufacturing the LSI device.
[0032]
At this time, as a basic element for an active LSI, it is important that analog modulation of the gain coefficient β can be performed with a compact element size that does not hinder high integration without increasing power consumption.
[0033]
From such a viewpoint, the present inventor has developed a semiconductor device in which the gain coefficient of a field-effect transistor can be voltage-modulated, and has previously filed an application (Patent Document 1). Here, it is referred to as a gain coefficient variable MOS transistor, and its outline will be described.
[0034]
A structural feature of the variable gain coefficient MOS transistor is that a control gate is additionally provided obliquely to a gate region (referred to as a main gate) in a conventional MOS transistor. In other words, this gain coefficient variable MOS transistor forms a triangular region on the source region side and the drain region side of the channel region under the control gate that is not overlapped with the main gate, and these regions sandwich the main gate. It is characterized in that a parallelogram is formed.
[0035]
The modulation characteristic of the gain coefficient β can be set by the element shape parameters (the gate width W and the gate length L of the main gate, and the angle θ between the main gate and the control gate).
[0036]
According to this configuration, the direction of the electric field with respect to the gate channel can be controlled by the voltage of the control gate. That is, by adjusting the voltage of the control gate and changing the conductance of the control gate channel with respect to that of the main gate, the effective gate length L and gate width W can be modulated in an analog manner, and the gain coefficient β Can be analog-modulated.
[0037]
Therefore, by incorporating this variable gain coefficient MOS transistor into an LSI, it is possible to dynamically adjust the characteristics of the device on-chip itself, and to improve the operation timing between the built-in functional circuits accompanying the increase in the scale of the LSI and the performance of the device. A mechanism for automatically correcting variations in element characteristics that increase with miniaturization can be realized with high integration.
[0038]
[Patent Document 1]
JP-A-2002-222944 (0020 to 0032, FIGS. 1 to 5)
[0039]
[Problems to be solved by the invention]
However, in a semiconductor device that can be called a variable gain coefficient MOS transistor, which the present inventor has previously filed, in order to form a triangular region on the source region side and the drain region side of the main gate, a certain angle with respect to the main gate is required. Since an additional control gate is provided, there is a problem that the size of the element is increased.
[0040]
Further, since the modulation characteristic of the gain coefficient in the semiconductor element is determined by the conductance ratio between the main gate and the control gate as described above, there is also a problem that as the conductance of the main gate decreases, the degree of modulation of the gain coefficient decreases. is there.
[0041]
The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor element capable of modulating a gain coefficient, which can reduce the element size and ensure the degree of modulation of the gain coefficient regardless of the conductance of the gate region. Aim.
[0042]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention is provided with a control channel region extending over the entire width thereof along the gate width direction at both ends or one end of the gate region in the field effect transistor. The threshold value in the control channel region has a non-uniformity that changes continuously or stepwise with a one-way change characteristic from one end to the other end in the gate width direction. .
[0043]
According to the present invention, since the threshold value in the control channel region is made non-uniform in the gate width direction, when the magnitude of the control voltage applied to the control channel region is changed, the channel formed in the control channel region is changed. Varies according to the threshold distribution. At this time, a channel formed in the control channel region becomes an effective channel in the gate region. That is, by adjusting the magnitude of the control voltage applied to the control channel region, the effective channel width in the gate region can be modulated, and the gain coefficient of the field effect transistor can be modulated.
[0044]
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings.
[0045]
Embodiment 1 FIG.
1 to 3 are schematic diagrams showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a top view. FIG. 2 is a sectional view taken along line AA ′ shown in FIG. FIG. 3 is a sectional view taken along the line BB 'shown in FIG.
[0046]
In FIG. 1, as is well known, the structure of a MOS transistor is such that a gate region 1 is located between a source region 2 and a drain region 3 (center position) and between a source region 2 and a drain region 3. It is arranged across a channel to be formed (hereinafter referred to as “gate channel”). The gate region 1, the source region 2, and the drain region 3 are provided with contacts 4a, 4b, and 4c forming electrodes, respectively.
[0047]
In the semiconductor device according to the first embodiment, in such a MOS transistor, if the gate region 1 is hereinafter referred to as the main gate 1, the control gate 5 is provided so as to cover the main gate 1 from above. As a result, the control gate channel region 6 is formed so as to protrude on both ends in the gate length direction of the main gate 1, that is, on the source region 2 side and the drain region 3.
[0048]
The control gate 5 is provided with a contact 4d forming an electrode. FIG. 1 shows an example in which the arrangement region of the contact 4 d in the control gate 5 and the arrangement region of the contact 4 a in the main gate 1 are formed on the opposite side to the line connecting the source region 2 and the drain region 3. ing.
[0049]
As shown in FIG. 2 which is a cross-sectional view parallel to the gate channel, the main gate 1 and the control gate 5 are separated by an insulating film layer 7 and are electrically separated. On the surface side of the substrate (well region) 8, channel impurity diffusion regions 9 constituting the above-mentioned control gate channel region 6 formed so as to protrude from both ends in the gate length direction of the main gate 1 are formed.
[0050]
The impurity concentration of the channel impurity diffusion region 9 is not uniform in the gate width direction of the main gate 1 and is one end to the other end as shown in FIG. 3 which is a sectional view of the control gate channel region 6 perpendicular to the gate channel. , And shows a non-uniformity that changes continuously toward. FIG. 3 shows that the darker the black, the lower the impurity concentration.
[0051]
As a result, the threshold value of the control gate channel region 6 (hereinafter referred to as the “threshold value of the control gate 5”) is not uniform in the gate width direction of the main gate 1, that is, in the direction crossing the gate channel. It changes continuously with a one-way change characteristic toward the end.
[0052]
FIG. 1 shows that the threshold value of the control gate 5 decreases as the black color becomes darker. That is, the contact 4a side of the main gate 1 is darkest black and the threshold value is the minimum value, and the contact 4d side of the control gate 5 is the lightest and the threshold value is the maximum value.
[0053]
In this manner, the threshold non-uniformity of the control gate 5 is realized by spatially distributing the impurity concentration of the channel impurity diffusion region 9 in the gate width direction of the main gate 1. Therefore, the shape of the control gate 5 is arbitrary. Generally, it depends on the shape of the main gate 1 and often has a rectangular shape.
[0054]
Next, an operation principle of modulating the gain coefficient of the MOS transistor realized by the semiconductor device configured as described above will be described with reference to FIGS. FIG. 4 is a diagram showing an example of drain current characteristics per unit gate width controlled by the control gate shown in FIG. FIG. 5 is a diagram illustrating shape parameters that define the characteristics of the semiconductor device shown in FIG. FIG. 6 is a diagram illustrating a gate channel width modulation operation realized by the semiconductor device shown in FIG.
[0055]
Since the threshold value of the control gate 5 continuously changes in the gate width direction of the main gate 1 with a one-way change characteristic from one end to the other end, the magnitude of the control voltage applied to the control gate 5 changes. Then, the width of the channel formed in the control gate channel region 6 changes according to the threshold distribution. At this time, a channel formed in the control gate channel region 6 becomes an effective channel in the gate region 1.
[0056]
4, the horizontal axis indicates the control gate voltage Vcg of the control gate 5. The vertical axis indicates the drain current Id per unit gate width for each control gate threshold Vt, and the sum of them is the drain current flowing through the MOS transistor shown in FIG. Low indicates low, and High indicates high.
[0057]
As shown in FIG. 4, the drain current Id per unit gate width flows from a lower value of the control gate voltage Vcg as the threshold value Vt of the control gate 5 decreases, and the control gate voltage Vcg increases as the threshold value Vt increases. If it does not become high, the drain current Id in that part does not flow. The drain current Id flows only in a portion where the control gate voltage Vcg exceeds the threshold value Vt.
[0058]
That is, the effective channel width of the main gate 1 can be modulated by the control voltage Vcg applied to the control gate 5, and the gain coefficient β of the MOS transistor can be modulated. The realized channel modulation characteristic can be set by the threshold distribution of the control gate 5 and the shape parameters shown in FIG.
[0059]
In FIG. 5, the gate length L and gate width W of the main gate 1 and the gate length Lc of the control gate 5 are used as shape parameters. By adjusting them, the modulation characteristics of the gain coefficient β can be designed. In general, the degree of modulation of the gain coefficient β increases as the gate length Lc of the control gate 5, which is the control channel length, decreases, or as the amount of change in the threshold distribution of the control gate 5 increases.
[0060]
The effective channel width of the main gate 1 is modulated by the control gate voltage Vcg, for example, as shown in FIG. In FIG. 6, the maximum value of the threshold value of the control gate 5 is represented by Vtmax, the minimum value is represented by Vtmin, and an intermediate value between them is represented by Vtmiddle.
[0061]
As described with reference to FIG. 1, the threshold value of the control gate 5 gradually decreases toward the contact 4a of the main gate 1. Then, the conductance of the main gate 1 is larger at a place where the threshold value is lower. Therefore, in FIG. 6, the effective channel of the main gate 1 is formed on the contact 4a side of the main gate 1.
[0062]
FIG. 6A shows a case where the control gate voltage Vcg is relatively high (Vcg> Vtmax). In this case, a channel is formed in most of the control gate channel region 6 in the control gate 5. As a result, the width of the effective channel 11 formed on the side of the contact 4a of the main gate 1 is relatively widened toward a place where the threshold value is high, and the gain coefficient β is increased. Further, although a large amount of drain current in the main gate 1 flows to a place where the threshold value is low, since the effective width of the channel 11 greatly increases toward a place where the threshold value is high, a distribution proportional to the spread is made. I have. That is, the change range of the drain current is widened.
[0063]
FIG. 6C shows a case where the control gate voltage Vcg is relatively low (Vtmiddle>Vcg> Vtmin). In this case, a channel is formed only in a portion of the control gate channel region 6 in the control gate 5 where the threshold value is lower than the intermediate value Vtmiddle. That is, the width of the channel formed in the control gate channel formation region 6 is considerably reduced. As a result, the width of the effective channel 12 formed on the side of the contact 4a of the main gate 1 is relatively small since the range where the threshold value is low is relatively small, and the gain coefficient β is small. The change range of the drain current is considerably narrowed.
[0064]
FIG. 6B shows a case where the control gate voltage Vcg is medium (Vtmax>Vcg> Vtmiddle). In this case, a channel is formed in the control gate channel formation region 6 until the threshold value is near the intermediate value Vtmiddle. That is, the width of the channel formed in the control gate channel formation region 6 is increased to about the middle between the case of FIG. 6C and the case of FIG. As a result, the width of the effective channel 13 formed on the side of the contact 4a of the main gate 1 is slightly wider toward the higher threshold value than in the case of FIG. It is about the middle between (a) and FIG. 6 (b).
[0065]
As described above, in the semiconductor device of the present invention, the width of the channel formed in the control gate channel region 6 can be changed by the voltage applied to the control gate 5. Thus, the effective channel width of the main gate 1 is modulated, so that the gain coefficient β of the basic MOS transistor, that is, the drain current characteristic can be continuously modulated.
[0066]
Here, in the semiconductor device of the present invention, as described above, a configuration system which does not require the formation of a triangular region by the control gate channel which is necessary in the configuration system of the semiconductor device filed by the present inventors previously is adopted. Therefore, the element size can be reduced.
[0067]
In the semiconductor device of the present invention, the effective channel width of the main gate is modulated by changing the direction of the electric field applied to the gate channel by the control gate voltage. Since the effective channel width of the main gate 1 is modulated by adjusting the width of the channel formed in the control gate channel region 6, the degree of modulation of the gain coefficient β is ensured regardless of the conductance of the main gate 1. This has the effect that the modulation characteristic of the gain coefficient β does not strongly depend on the gate voltage.
[0068]
Further, in the semiconductor device of the present invention, since both the NMOS transistor and the PMOS transistor can be realized with the same configuration, the semiconductor device can be easily applied to a CMOS circuit.
[0069]
The power consumed for modulating the gain coefficient β is only due to the leakage current of the control gate 5. This is extremely small and does not cause a problem in practical use.
[0070]
Embodiment 2 FIG.
FIG. 7 is a cross-sectional view (a cross-sectional view taken along the line BB 'shown in FIG. 1) showing a configuration of a semiconductor device according to a second embodiment of the present invention. In FIG. 7, components that are the same as or equivalent to the configuration illustrated in FIG. 1 are denoted by the same reference numerals. Here, a description will be given focusing on a portion relating to the second embodiment.
[0071]
In the second embodiment, another configuration example (part 2) for realizing spatial non-uniformity of the control gate threshold value is shown. That is, in the semiconductor device according to the second embodiment, as shown in FIG. 7, the surface of the substrate 8 is covered with the gate insulating film 21 instead of the insulating film layer 7 in the control gate channel region 6 shown in FIG. The thickness of the gate insulating film 21 is spatially non-uniform. That is, the gate insulating film 21 is formed so as to gradually increase in thickness from one end to the other end. Note that the impurity concentration of the channel impurity diffusion region 22 formed on the surface side of the substrate 8 is spatially uniform.
[0072]
Even with such a structure, the threshold value of the control gate 5 can be made to be spatially non-uniform, so that the same modulation effect as in the first embodiment can be expected. In addition, in the second embodiment, since the spatial non-uniformity of the threshold distribution can be realized while the impurity concentration of the control gate channel region remains uniform, a photomask for forming the concentration distribution becomes unnecessary. This has the effect of reducing manufacturing costs and manufacturing steps.
[0073]
Embodiment 3 FIG.
FIG. 8 is a top view showing the configuration of the semiconductor device according to the third embodiment of the present invention. In FIG. 8, components that are the same as or equivalent to the configuration illustrated in FIG. 1 are denoted by the same reference numerals. Here, a description will be given focusing on a portion relating to the third embodiment.
[0074]
In the third embodiment, another configuration example (part 3) for realizing spatial non-uniformity of the control gate threshold value is shown. That is, as shown in FIG. 8, in the third embodiment, a control gate 31 is provided instead of control gate 5 shown in FIG.
[0075]
In the control gate channel region 32 of the control gate 31, the spatial distribution of the one-way change characteristic of the threshold value is set so as to change stepwise instead of continuously. This stepwise change is the same at both ends of the main gate 1 in the gate length direction.
[0076]
Specifically, the threshold value of the control gate 31 is Vt = low on both ends of the main gate 1 in the gate length direction in the gate width direction, for example, on the contact 4a side of the main gate 1 as shown in FIG. On the contact 4d side of the control gate 31, Vt = high, and during that time, Vt = medium.
[0077]
The control gate 31 having such a plurality of different threshold values can be obtained by changing the concentration of the channel impurity for each region as described in the first embodiment, or by changing the gate insulating concentration as described in the second embodiment. It can be realized by a method such as changing the film thickness.
[0078]
According to the third embodiment, in addition to obtaining the same modulation effect as that of the first embodiment, it is necessary to newly develop a special means for forming the threshold distribution of the control gate in a stepwise manner. In addition, there is an effect that a method of separately making with a conventional mask can be used.
[0079]
Embodiment 4 FIG.
FIG. 9 is a top view showing a configuration of the semiconductor device according to the fourth embodiment of the present invention. In FIG. 9, components that are the same as or equivalent to the configuration shown in FIG. 1 are given the same reference numerals. Here, a description will be given focusing on a portion related to the fourth embodiment.
[0080]
In the fourth embodiment, another configuration example (part 4) for realizing spatial non-uniformity of the control gate threshold value is shown. That is, as shown in FIG. 9, in the fourth embodiment, a control gate 41 is provided instead of control gate 5 shown in FIG.
[0081]
In the control gate channel regions 42 and 43 of the control gate 41, the spatial distribution of the one-way change characteristic of the threshold value is set so as to change stepwise instead of continuously changing. Unlike the third embodiment, the stepwise change has a reverse relationship in the gate width direction at both ends of the main gate 1 in the gate length direction.
[0082]
Specifically, for example, as shown in FIG. 9, the threshold value of the control gate 31 is Vt = low on the contact 4a side of the main gate 1 in the control gate channel region 42, and is Vt = low on the contact 4d side of the control gate 41. , Vt = high, while Vt = medium.
[0083]
On the other hand, in the control gate channel region 42, Vt = high on the contact 4a side of the main gate 1, Vt = low on the contact 4d side of the control gate 41, and Vt = medium in the meantime. I have.
[0084]
According to the fourth embodiment, in addition to obtaining the same modulation effect as in the first embodiment, the modulation of the channel length also occurs in addition to the modulation of the channel width of the main gate. There is an effect that a proper modulation can be realized.
[0085]
In the fourth embodiment, an example of application to the third embodiment has been described. However, the fourth embodiment can be similarly applied to the first and second embodiments. Further, in the first to fourth embodiments, the case where the control gate has control gate channel regions formed at both ends in the gate length direction of the main gate has been described. However, the present invention is not limited to this. The control gate channel region may be formed on one side of the gate in the gate length direction, that is, on either the source region side or the drain region side. With this, the same operation and effect can be obtained.
[0086]
Here, the semiconductor device according to the present invention has a compact size and features that do not involve an increase in power consumption as compared with the semiconductor device previously filed by the present inventors, so that the electrical characteristics of the device are automatically adjusted on-chip. In addition, it is possible to implement a high-density mounting of a mechanical circuit for correcting characteristic variations on all LSI devices.
[0087]
In other words, performance variations due to element miniaturization that prevent future high-performance of large-scale LSI devices, performance degradation due to non-uniform characteristics such as element characteristic fluctuations due to process fluctuations, and difficulty in LSI physical design, etc. It has the effect of greatly reducing the amount of water.
[0088]
Therefore, the device configuration technology according to the present invention is expected to contribute to the realization of a new type LSI based on a completely new design concept, such as a self-optimizing LSI or a self-adaptive LSI that allows a large variation in device characteristics.
[0089]
【The invention's effect】
As described above, according to the present invention, a control channel region extending over the entire width in the gate width direction is provided at both ends or one end of the gate region in the field effect transistor in the gate length direction. Is applied to the control channel region because the threshold value in the above has a non-uniformity that increases or decreases continuously or stepwise with a unidirectional change characteristic from one end to the other end in the gate width direction. By adjusting the magnitude of the control voltage, the effective channel width in the gate region can be modulated, and the gain coefficient of the field-effect transistor can be modulated.
[0090]
Therefore, according to the present invention, a configuration method that does not require the formation of a triangular region by the control gate channel, which is required in the configuration method of the semiconductor element filed by the present inventor earlier, is adopted. And the gate voltage dependence of the gain coefficient modulation characteristic can be reduced.
[Brief description of the drawings]
FIG. 1 is a top view illustrating a configuration of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a sectional view taken along line AA ′ of the semiconductor element shown in FIG. 1;
FIG. 3 is a sectional view taken along line BB ′ of the semiconductor device shown in FIG. 1;
FIG. 4 is a diagram showing an example of a drain current characteristic per unit gate width controlled by a control gate of the semiconductor device shown in FIG. 1;
FIG. 5 is a diagram showing shape parameters defining characteristics of the semiconductor device shown in FIG. 1;
FIG. 6 is a diagram for explaining gate channel width modulation realized by the semiconductor device shown in FIG. 1;
FIG. 7 is a cross-sectional view of a main part (a cross-sectional view taken along the line BB ′ shown in FIG. 1) illustrating the configuration of the semiconductor element according to the second embodiment of the present invention;
FIG. 8 is a top view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention;
FIG. 9 is a top view illustrating a configuration of a semiconductor device according to a fourth embodiment of the present invention;
[Explanation of symbols]
1 gate region (main gate), 2 source region, 3 drain region, 4a, 4b, 4c, 4d contact, 5, 31, 41 control gate, 6, 32, 42, 43 control gate channel region, 7 insulating film layer, 8 substrate (well region), 9, 22 channel impurity diffusion region, 21 gate insulating film, 12-13 effective channel of main gate.

Claims (4)

At both ends or one end of the gate region of the gate region in the field-effect transistor, a control channel region is provided over the entire width along the gate width direction,
The threshold value in the control channel region has a non-uniformity that changes continuously or stepwise with a one-way change characteristic from one end to the other end in the gate width direction.
A semiconductor element characterized by the above-mentioned. In the case where the control channel region is provided at both ends in the gate length direction,
The one-way change characteristic of the threshold has a reverse relationship between the control channel region on the source region side and the control channel region on the drain region side.
The semiconductor device according to claim 1, wherein: The non-uniformity of the threshold value in the control channel region is realized by making the impurity concentration of the control channel diffusion region forming the control channel region non-uniform from one end to the other end in the gate width direction. The semiconductor device according to claim 1, wherein: The non-uniformity of the threshold value in the control channel region is realized by making the thickness of the insulating film in the control channel region non-uniform from one end to the other end in the gate width direction. The semiconductor device according to claim 1.

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