JP2004234523A - Data arithmetic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data arithmetic circuit capable of shortening the time of using a CPU. <P>SOLUTION: This data arithmetic circuit 100 comprises a first input part 10 for inputting n-digit first input data, a second input part for inputting n-digit second input data, and a correction register 30 for storing optionally set first correction data and second correction data. This arithmetic circuit further comprises an addition/substraction circuit 80, which outputs, when arithmetic data that are the sum of the first input data and the second input data are carried up from n digits, the lower n digits of a numerical value obtained by adding the second correction data to the arithmetic data as result data; outputting, when the arithmetic data are not carried out from n digits, and no digit borrowing is cause when the first correction data are subtracted from the arithmetic data, a numerical value obtained by subtracting the first correction data from the arithmetic data as result data; and outputting, when the arithmetic data are not carried up from n digits, and no borrowing is caused when the first correction data are subtracted from the arithmetic data, the arithmetic data as result data. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data operation circuit.
[0002]
[Prior art]
In general, a data recorder, a CD (Compact Disc) player, a DVD (Digital Video Disk) player, or a VTR (Video Tape Recorder) has a function of performing time calculation of data stored in a storage medium. For example, in a CD player, time calculations such as calculation of the remaining time of one tune being played, calculation of the time to access a certain tune, calculation of the time difference between the data stored in the DRAM and the data currently being read, and the like are performed. Done. Conventionally, these time calculations have been performed by causing a CPU to process a program. That is, the time calculation of the data has been realized by software.
[0003]
[Problems to be solved by the invention]
When the above-described time calculation was processed by software, it took about 250 μs (microsecond) for a 10 MHz CPU.
[0004]
In recent years, data compression techniques such as CD-MP3 have been developed, and the CPU must process compressed information having a large amount of information. Therefore, it is better that the time for using the CPU for calculating the time of data is short.
[0005]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a data operation circuit that reduces the time for which a CPU is used for data operation processing.
[0006]
[Means for Solving the Problems]
The data operation circuit according to the embodiment according to the present invention includes:
a first input unit for inputting n-digit first input data;
a second input unit for inputting n-digit second input data;
A correction register for storing arbitrarily set first correction data and second correction data,
If the operation data obtained by adding the first input data and the second input data carry from n digits, the lower n of the numerical value obtained by adding the second correction data to the operation data The digit is output as result data, and if the arithmetic data does not carry over from the n-th digit and if the first correction data is subtracted from the arithmetic data and no borrow occurs, the arithmetic data is A numerical value obtained by subtracting the first correction data is output as result data. When the arithmetic data does not carry over from n digits and when the first correction data is subtracted from the arithmetic data, a borrow occurs. Comprises an operation circuit for outputting the operation data as result data.
[0007]
The data operation circuit according to the embodiment according to the present invention includes:
an adder / subtracter for adding or subtracting n-digit first numerical data and n-digit second numerical data to output operation data;
An input unit for inputting first input data and second input data;
A correction register for storing arbitrarily set first correction data and second correction data,
A first selection circuit that selects one of the operation data or the first input data and outputs the selected data as the first numerical data;
A second selection circuit that selects any one of the first correction data and the second correction data based on whether the calculation data carries more than n digits;
A third selection circuit that selects either the correction data selected in the second selection circuit or the second input data and outputs the selected data as the second numerical data;
A fourth selection circuit that selects either the operation data or the first numerical data based on whether the operation data requires borrowing, and outputs the data as result data;
A control circuit for controlling the first selection circuit, the third selection circuit, and the adjustment circuit;
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The arithmetic circuit according to the embodiment of the present invention executes a numerical operation conventionally performed by software by a digital logical operation using hardware.
[0009]
FIG. 1 is a block diagram of a time operation circuit 1 including data operation circuits 100a to 100c according to an embodiment of the present invention. The time calculation circuit 1 is provided, for example, in a CD player, and calculates a reproduction time of a CD and the like. Usually, the CD player is provided with a panel (not shown) for displaying a reproduction time of the CD and the like. The time calculation circuit 1 can display seconds and minutes on the panel.
[0010]
The time operation circuit 1 includes a data operation circuit 100a for frame operation, a data operation circuit 100b for second operation, a data operation circuit 100c for minute operation, and a control circuit 101 for controlling these data operation circuits 100a to 100c. I have. The data calculation circuit 100b for calculating a second displays a numerical value per second on a panel. The data calculation circuit 100c for minute calculation displays a numerical value in minutes on a panel. Note that the frame is not normally displayed on the panel.
[0011]
A CD is divided into "frames" containing a certain amount of data. The data operation circuit 100a operates this frame. Usually, 75 frames correspond to one second and 60 seconds correspond to one minute.
[0012]
Therefore, the data arithmetic circuit 100a generates a carry (hereinafter also referred to as "carry") CY1 when the number of frames exceeds 74, and returns the number of frames to 0. In response to the carry CY1, the data operation circuit 100b adds one second to the display of seconds on the panel. The data operation circuit 100b generates a carry CY2 when the time exceeds 59 seconds, and returns the second display to 0 seconds. In response to the carry CY2, the data operation circuit 100c adds one minute to the display on the panel.
[0013]
On the other hand, when the data operation circuit 100a becomes smaller than 0 frames, the data operation circuit 100a generates a borrow (hereinafter, also referred to as borrow) BR1, and sets the number of frames to 74 frames. In response to this borrow BR1, the data operation circuit 100b subtracts one second from the display of seconds. If the data operation circuit 100b is shorter than 0 second, the data operation circuit 100b generates a borrow BR2 and sets the display of seconds to 59 seconds. In response to the borrow BR2, the data operation circuit 100c subtracts one minute from the minute display.
[0014]
In this way, the time calculation circuit 1 carries out when the “frame” and “second” exceed the maximum value, and borrows when the “frame” and “second” become smaller than 0. To calculate the time.
[0015]
FIG. 2 is a block diagram of a data operation circuit included in any of data operation circuits 100a, 100b, and 100c. Hereinafter, the data operation circuit 100 will be described as a data operation circuit included in the data operation circuit 100b for second operation.
[0016]
The data operation circuit 100 includes a first input unit 10, a second input unit 20, a correction register 30, a first selection circuit S1, a second selection circuit S2, a third selection circuit S3, and a fourth selection circuit. S4, an adder / subtractor 80 and a control circuit 90 are provided.
[0017]
A register R1 is connected between the selection circuit S1 and the adder / subtractor 80. Register R1 temporarily stores data from selection circuit S1. A register R2 is connected between the selection circuit S3 and the adder / subtractor 80. Register R2 temporarily stores data from selection circuit S3. A register R3 is connected between the selection circuit S4 and the adder / subtractor 80. The register R3 temporarily stores data from the adder / subtractor 80.
[0018]
The adder / subtractor 80 receives data from the registers R1 and R2 and adds or subtracts the data to generate operation data. The adder / subtractor 80 transmits the lower two digits of the numerical value of the operation data to the register R3. The adder / subtractor 80 is connected to the selection circuits S2 and S4. Accordingly, the adder / subtractor 80 issues a carry CY3 to the selection circuit S2 when the operation data carries, and issues a borrow BR1 to the selection circuit S4 when the operation data requires borrowing. The carry CY3 is used in the data operation circuit 100 and is different from the carry CY2. For example, the carry CY2 is generated when the calculation data exceeds 60 seconds, and is used for carry-up in units of minutes in the data calculation circuit 100c for minute calculation shown in FIG. The carry CY3 is generated when the operation data exceeds 100 seconds, and is used for the selection circuit S2. The adder / subtractor 80 is, for example, a decimal adder / subtractor.
[0019]
The selection circuit S1 is connected to the input unit 10 and the register R3. The selection circuit S1 selects data from either the input unit 10 or the register R3 and transmits the data to the register R1.
[0020]
The selection circuit S2 is connected to the correction data register 30. The selection circuit S2 selects either the first correction data or the second correction data stored in the correction data register 30 based on the carry CY3, and transmits the selected data to the selection circuit S3. For example, the selection circuit S2 selects the first correction data when the carry CY3 has not occurred, and selects the second correction data when the carry CY3 has occurred.
[0021]
The selection circuit S3 is connected to the input unit 20 and the selection circuit S2, selects data from either the input unit 20 or the selection circuit S2, and transmits the selected data to the register R2.
[0022]
The selection circuit S4 is connected to the registers R1 and R3. The selection circuit S4 selects data from either the register R1 or the register R3 based on the borrow BR1, and outputs this as result data. For example, the selection circuit S4 selects the register R3 when the borrow BR1 has not occurred, and selects the register R1 when the borrow BR1 has occurred. The result data output from the selection circuit S4 is displayed on a panel or the like of the CD player.
[0023]
The correction data register 30 stores the first correction data and the second correction data. The first correction data and the second correction data are used to correct a numerical value in units of seconds when carrying to minutes is performed. The first correction data and the second correction data can be set after manufacturing the data operation circuit 100. A memory such as a RAM is used as the correction data register 30, for example.
[0024]
The control circuit 90 is connected to the selection circuits S1, S3 and the adder / subtractor 80 and controls them.
[0025]
FIG. 3 is a flowchart showing the operation of the data operation circuit 100. The operation of the data operation circuit 100 will be described with a specific example with reference to FIGS. In the present embodiment, the first correction data is set to 60 seconds, and the second correction data is set to 40 seconds. Carry CY2 occurs when the operation data exceeds 60 seconds. Carry CY3 occurs when the operation data exceeds 100 seconds.
[0026]
(First specific example)
First, the first input data X and the second input data Y are input to the input unit 10 and the input unit 20, respectively (S10). For example, the first input data X is a numerical value in seconds of a time required for reproducing the first music piece recorded on the CD (hereinafter referred to as a reproduction time). The second input data Y is a numerical value of the reproduction time of the second music in seconds.
[0027]
In this specific example, it is assumed that the reproduction time of the first music piece is 3 minutes and 13 seconds, and the reproduction time of the second music piece is 3 minutes and 23 seconds. In this case, the first input data X is 13 seconds, and the second input data Y is 23 seconds.
[0028]
The control circuit 90 controls the selection circuits S1 and S3 such that the selection circuit S1 first selects the first input data X and the selection circuit S3 selects the second input data Y. (S20). As a result, the first input data X is stored in the register R1. The second input data Y is stored in the register R2.
[0029]
The adder / subtractor 80 receives the first input data X and the second input data Y from the registers R1 and R2, and calculates the sum X + Y of them as first operation data (S30). In this specific example, since the first input data X is 13 seconds and the second input data Y is 23 seconds, the first calculation data is 36 seconds (X + Y = 36).
[0030]
Next, the adder / subtractor 80 determines whether the first operation data is longer than 100 seconds. If the first operation data is shorter than 100 seconds, no carry CY3 occurs. On the other hand, when the first operation data is longer than 100 seconds, the carry CY3 occurs (S35). In this specific example, since the first operation data is 36 seconds, carry CY3 does not occur. Further, the adder / subtractor 80 determines whether the first operation data is longer than 60 seconds. If the first operation data is shorter than 60 seconds, no carry CY2 occurs. On the other hand, if the first operation data is longer than 60 seconds, the carry CY2 occurs (S35). In this specific example, since the first operation data is 36 seconds, carry CY2 does not occur.
[0031]
Next, the first operation data is stored in the register R3. The first operation data stored in the register R3 is fed back to the selection circuit S1. Since the borrow BR1 has not occurred at this point, the selection circuit S4 has selected the first operation data in the register R3. However, the data operation circuit 100 does not display the result data on the panel at this time.
[0032]
Next, the control circuit 90 controls the selection circuits 1 and 3 so that the selection circuit S1 selects the first operation data stored in the register R3 and the selection circuit S3 selects the selection circuit S2. Control is performed (S40). As a result, the first operation data is stored in the register R1. Since the carry CY3 has not occurred, the selection circuit S2 selects the first correction data. Therefore, the first correction data is stored in the register R2 via the selection circuits S2 and S3. In this specific example, since the first operation data is 36 seconds and the first correction data is 60 seconds, 36 seconds are stored in the register R1 and 60 seconds are stored in the register R2.
[0033]
Next, the adder / subtractor 80 receives the first operation data and the first correction data from the registers R1 and R2, and subtracts the first correction data from the first operation data (S50). In this specific example, the first calculation data is 36 seconds, and the first correction data is 60 seconds, so that the result of this subtraction is 36−60 = −24. That is, since the second calculation data is smaller than 0 second, a borrow BR1 occurs. Therefore, the selection circuit S4 selects the register R1, and outputs the first operation data as result data (S90). In this specific example, the selection circuit S4 outputs 36 seconds as result data. The result data is displayed on the panel. As described above, the data operation circuit 100 displays “36 seconds” in units of seconds in the total time of 6 minutes and 36 seconds of the reproduction time of 3 minutes and 13 seconds of the first music and the reproduction time of 3 minutes and 23 seconds of the second music. To be displayed.
[0034]
(Second specific example)
In the second specific example, it is assumed that the reproduction time of the first music piece is 3 minutes and 47 seconds and the reproduction time of the second music piece is 3 minutes and 38 seconds. In this case, the first input data X is 47 seconds, and the second input data Y is 38 seconds.
[0035]
Steps S10 to S30 are executed in the same manner as in the first specific example. As a result, the first operation data (X + Y) is 85 seconds. Since the first operation data is shorter than 100 seconds, no carry CY3 occurs in step S35. On the other hand, since the first operation data is longer than 60 seconds, the carry CY2 occurs. Due to the occurrence of carry CY2, carry in minutes is generated in data operation circuit 100c for minute operation.
[0036]
Since the carry CY3 has not occurred, as in the first specific example, in step S40, 85 seconds is stored in the register R1 as the first operation data. The first correction data (60 seconds) is stored in the register R2.
[0037]
Next, in step S50, the first correction data is subtracted from the first calculation data to generate second calculation data. In this specific example, the second operation data is 85 seconds−60 seconds = 25 seconds. That is, since the second operation data is longer than 0 second, the borrow BR1 does not occur in step S55.
[0038]
Therefore, the selection circuit S4 selects the register R3 and outputs the second operation data as result data (S60). That is, the selection circuit S4 outputs 25 seconds as result data. The result data is displayed on the panel. As described above, the data operation circuit 100 can display the unit of second in consideration of the carry to the unit of minute. In this specific example, since the carry to the minute unit is performed, a total of 6 minutes of the minute unit (3 minutes) of the reproduction time of the first music and the minute unit (3 minutes) of the reproduction time of the second music is used. Is carried to 7 minutes. As a result, a total time of 7 minutes and 25 seconds is displayed on the panel. The data operation circuit 100 displays “25 seconds” in seconds of 7 minutes and 25 seconds on the panel.
[0039]
(Third specific example)
In the third specific example, it is assumed that the reproduction time of the first music piece is 3 minutes and 47 seconds and the reproduction time of the second music piece is 3 minutes and 58 seconds. In this case, the first input data X is 47 seconds, and the second input data Y is 58 seconds.
[0040]
Steps S10 to S30 are executed in the same manner as in the first specific example. As a result, the first operation data is 105 seconds. Since the first operation data is longer than 100 seconds, carry CY3 occurs in step S35. Further, since the first operation data is longer than 60 seconds, carry CY2 also occurs. Upon occurrence of carry CY3, selection circuit S2 selects the second correction data (40 seconds). Due to the occurrence of carry CY2, carry in minutes is generated in data operation circuit 100c for minute operation.
[0041]
Since carry CY3 occurs, step S70 is executed next. The adder / subtractor 80 transmits the lower two digits of the numerical value of the operation data to the register R3. Therefore, the lower two digits of the first operation data are stored in the register R1. In this specific example, 05 seconds is stored as the last two digits of the first calculation data of 105 seconds. Also, since the carry CY3 has occurred, the second correction data (40 seconds) is stored in the register R2.
[0042]
Next, the second correction data is added to the lower two digits of the first calculation data to generate second calculation data (S80). In this specific example, the second operation data is 05 seconds + 40 seconds = 45 seconds. Since the second operation data is longer than 0 second, the borrow BR1 does not occur. Therefore, the selection circuit S4 selects the register R3 and outputs the second operation data as result data (S60). That is, the selection circuit S4 outputs 45 seconds as result data. The result data is displayed on the panel.
[0043]
In this specific example, since the carry is performed in units of minutes, a total of 6 minutes of the minute unit of the reproduction time of the first music and the reproduction unit of the second music is carried to 7 minutes. As a result, a total time of 7 minutes and 45 seconds is displayed on the panel. The data operation circuit 100 displays “25 seconds” in seconds of 7 minutes and 25 seconds on the panel.
[0044]
In the present embodiment, the relationship between the first input data X and the second input data Y and the result data can be expressed as follows.
When X + Y <60, the result data is X + Y (corresponding to the first specific example).
When 60 ≦ X + Y <100, the result data is X + Y−60 (corresponding to the second specific example).
When 100 ≦ X + Y, the result data is the last two digits of the numerical value of X + Y + 40 (corresponding to the third specific example).
[0045]
In the present embodiment, the first correction data is set to 60, and the second correction data is set to 40. However, the numerical value of the first correction data and the numerical value of the second correction data are not limited to these, and can be arbitrarily set based on the first input data and the second input data.
[0046]
However, the first correction data is preferably equal to a numerical value obtained by adding 1 to the maximum value of the result data. For example, when the data calculation circuit 100 calculates a frame, the maximum value of the result data is 74, so the numerical value of the first correction data is preferably 75 frames.
[0047]
It is preferable that the minimum value when the arithmetic data carries up is equal to the sum of the first correction data and the second correction data. For example, the minimum value when the arithmetic data carries (when carry CY3 occurs) is 100 frames. Therefore, the sum of the numerical value of the first correction data and the numerical value of the second correction data is preferably 100 frames. Based on this, the second correction data can be calculated. In this case, the second correction data is 25 frames (100−75 = 25).
[0048]
In the present embodiment, the adder / subtractor 80 transmits the last two digits of the operation data to the register R3. However, the adder / subtractor 80 may be configured to transmit the lower n digits (n is a natural number other than 2) of the operation data to the register R3. Here, the reason why the adder / subtractor 80 transmits the last n digits of the operation data is in consideration of the carry by the carry CY3. Therefore, n digits are equal to the number of digits of the first input data and the second input data. That is, the adder / subtractor 80 transmits only the numerical values of the remaining digits of the operation data excluding the digits generated when the carry CY3 occurs to the register R3.
[0049]
This embodiment has been described as being deployed in a CD player. However, the data operation circuit according to the present embodiment can also be applied to devices that require numerical operations, such as DVD players and VTRs.
[0050]
In the present embodiment, the data operation circuit 100 has been described as being used for a hexadecimal operation. However, the data operation circuit according to the present invention can be used for operations such as a decimal operation or a 75 operation.
[0051]
The data operation circuit 100 according to the present embodiment processes a time operation using a digital logic circuit. Therefore, the data operation circuit 100 can perform the time operation without burdening the CPU in the device in which the data operation circuit 100 is provided. For example, when the above-described time calculation is processed by the data calculation circuit 100, only about 2.4 μs (microsecond) is required for a 10 MHz CPU. That is, the data operation circuit 100 according to the present embodiment can execute a numerical operation in 1/100 of the conventional time.
[0052]
【The invention's effect】
Since the data operation circuit according to the present invention executes a numerical operation by a digital logic operation using hardware, it is possible to reduce the time during which the CPU operates for data operation processing.
[Brief description of the drawings]
FIG. 1 is a block diagram of a time operation circuit 1 including a data operation device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a data operation circuit included in any of data operation circuits 100a, 100b, and 100c.
FIG. 3 is a flowchart showing the operation of the data operation circuit 100.
[Explanation of symbols]
REFERENCE SIGNS LIST 100 data operation circuit 10 first input section 20 second input section 30 correction register S1, S2, S3, S4 first selection circuit 80 adder / subtractor 90 control circuit R1, R2, R3 register CY2, CY3 carry BR1 borrow

Claims (6)

a first input unit for inputting n-digit first input data;
a second input unit for inputting n-digit second input data;
A correction register for storing arbitrarily set first correction data and second correction data,
If the operation data obtained by adding the first input data and the second input data is carried over from n digits, the lower n of the numerical value obtained by adding the second correction data to the operation data Output digits as result data,
If the arithmetic data does not carry over from the n-th digit and no borrow occurs when the first correction data is subtracted from the arithmetic data, the first correction data is subtracted from the arithmetic data. Output numerical values as result data,
An arithmetic circuit that outputs the arithmetic data as result data when the arithmetic data does not carry over from n digits and a borrow occurs when the first correction data is subtracted from the arithmetic data. Data operation circuit. an adder / subtracter for adding or subtracting n-digit first numerical data and n-digit second numerical data to output operation data;
An input unit for inputting first input data and second input data;
A correction register for storing arbitrarily set first correction data and second correction data,
A first selection circuit for selecting either the operation data or the first input data and outputting the selected data as the first numerical data;
A second selection circuit that selects any one of the first correction data and the second correction data based on whether the calculation data carries more than n digits;
A third selection circuit that selects either the correction data selected in the second selection circuit or the second input data and outputs the selected data as the second numerical data;
A fourth selection circuit that selects either the operation data or the first numerical data based on whether the operation data requires borrowing, and outputs the data as result data;
A data operation circuit comprising: a control circuit that controls the first selection circuit, the third selection circuit, and the addition / subtraction circuit. First, the first selection circuit and the third selection circuit select the first input data and the second input data, respectively, and the adder / subtracter selects the first numerical data as the first numerical data. Is input, the second input data is input as the second numerical data, and they are added to calculate first operation data. The second correction data is selected when the calculation data of n is carried up from n digits, and the first correction data is selected when the first calculation data is not carried up from n digits. ,
When the first operation data carries from n digits,
Next, the first selection circuit selects the last n digits of the first operation data, the third selection circuit selects the second correction data, and the adder / subtractor selects the first correction data. The lower n digits of the first calculation data are input as numerical data, the correction data is input as the second numerical data, and the selected correction data is added to the lower n digits of the first calculation data. The selection circuit 4 outputs the second operation data as result data,
When the first operation data does not carry from n digits,
Next, the first selection circuit selects the first operation data, the third selection circuit selects the first correction data, and the adder / subtracter selects the first correction data as the first numerical data. Inputting first calculation data, inputting the correction data as the second numerical data, subtracting the selected correction data from the first calculation data to calculate second calculation data,
The fourth selection circuit selects the first operation data when the second operation data requires borrowing, and selects the second operation data when the second operation data does not require borrowing. 3. The data operation circuit according to claim 2, wherein the operation data is selected and the data is output as result data. 3. The data operation according to claim 1, wherein the first correction data and the second correction data are determined by setting the correction register after manufacturing the data operation circuit. 4. circuit. The first correction data is equal to a value obtained by adding 1 to a maximum value of the result data,
The data arithmetic circuit according to claim 1, wherein a minimum value when the arithmetic data carries up is equal to a sum of the first correction data and the second correction data. 3. The data operation circuit according to claim 1, wherein the first input data and the second input data are time data.

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