JP2004234473A - Nonvolatile storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To extend the life of a nonvolatile storage device using a nonvolatile memory by preventing a failure of the nonvolatile memory. <P>SOLUTION: The nonvolatile storage device comprises the nonvolatile memory having a plurality of physical blocks and a controller. The controller selects a plurality of physical blocks from the nonvolatile memory as first reservation blocks, makes any one of the first reservation blocks store a first table showing the correlation between a logic address inputted and the physical address of the nonvolatile memory, and makes the nonvolatile memory store a second table showing the physical addresses of the first reservation blocks. When writing is performed to the nonvolatile memory, the controller rewrites the first table, and makes a block different from the one which stored the first table before rewriting of the first reservation blocks store the rewritten first table. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a storage device having a rewritable nonvolatile memory, and more particularly to a technique for managing writing to the nonvolatile memory.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as an external storage device for storing data used in an electronic device such as a computer, mainly a card-shaped storage device has been widely used. In such a storage device, a rewritable nonvolatile semiconductor memory is used.
[0003]
A flash memory is a typical rewritable nonvolatile semiconductor memory. In a flash memory, stored data is managed in units of blocks (physical blocks), and data is erased in units of blocks. Each block has a plurality of pages. A page is the minimum unit for reading and writing data in the flash memory. Generally, in a flash memory, erasing refers to a process of setting all bits to “1”, and writing refers to a process of setting a designated bit to “0”.
[0004]
Each page has a redundant portion separately from an area for storing data, and information relating to a logical address assigned to the page and a data correction code are stored in the redundant portion. Each page is assigned a unique physical address in the flash memory, and the control device of the flash memory controls processing by sending a command to the flash memory by designating the physical address.
[0005]
On the other hand, when a host such as a computer accesses data in a storage device, the host handles data in units of a data size called a sector. The host manages data stored in the flash memory in units of logical blocks having the same size as physical blocks. A logical block is generally composed of a plurality of sectors. A logical address, which is a logical order, is added to each sector, and the host controls processing by designating the logical address in the storage device.
[0006]
FIG. 14 is an explanatory diagram of data management in a general nonvolatile storage device. FIG. 14 shows the correspondence between the logical data configuration and the physical data configuration. The logical data configuration is a configuration of data specified by the host, and the physical data configuration is a configuration of data stored in the nonvolatile memory.
[0007]
The written logical block is managed in a one-to-one correspondence with the physical block in the flash memory (the unwritten logical block has no corresponding physical block). Q + 1 (Q is an integer of 0 or more) logical blocks constitute one logical segment. In addition, P + 1 physical blocks (P is an integer of 0 or more) constitute one physical segment.
[0008]
Here, each logical segment is assigned to one corresponding physical segment. Logical data constituting a certain logical segment is stored in an area managed as a specific physical segment (in general, Q <P because a physical block also has a bad block). Therefore, address translation information (hereinafter, referred to as AT; also referred to as logical-physical translation information) stored in the flash memory, which is correspondence information between logical blocks and physical blocks, is managed in physical segment units. become.
[0009]
FIG. 15 is a block diagram illustrating an example of a configuration of a conventional nonvolatile storage device. 15 includes a host interface 910, a controller 920, a random access memory (RAM) 930, which is a volatile memory, and a nonvolatile memory 940. The host interface 910 receives a command or the like from the host 902 and transmits it to the controller 920. The controller 920 performs arbitration between the host interface 910, the RAM 930, and the nonvolatile memory 940, and controls these.
[0010]
The non-volatile memory 940 is a rewritable non-volatile memory, and has a management area 942 and a data area 944. The management area 942 stores address conversion information, and the data area 944 stores data that the host 902 reads and writes.
[0011]
The management area 942 has an ATIP 952, an ATI 954, and an AT 956. The data area 944 has four physical segments. AT956 is a table corresponding to each physical segment. The ATI 954 stores a physical address of each table.
[0012]
The RAM 930 has an ATIRAM 932 for storing the ATI 954 after reading it, and an ATRAM 934 for reading one of the tables of the AT 956 and storing it.
[0013]
FIG. 16 is an explanatory diagram showing a data structure in the management area 942 of the nonvolatile memory 940 in FIG. The ATIP 952 is allocated to a specific block (for example, the first block) and stores the physical address of the ATI 954. The ATI 954 stores the physical address of each table (AT0, AT1, AT2, AT3) of the AT956. Tables AT0 to AT3 indicate address conversion information of each of the four physical segments.
[0014]
FIG. 17 is a flowchart illustrating an example of processing at the time of writing in the nonvolatile storage device of FIG.
[0015]
When a data write command is sent from the host 902 to the non-volatile storage device 900, in step S902, the non-volatile storage device 900 allocates a physical block to be written from the logical address of the write target specified by the host 902. The physical segment that is located.
[0016]
In step S904, it is determined whether or not the AT data of the physical segment obtained in step S902 has already been read into the ATRAM 934. If the AT data has not been read, the process proceeds to step S906. If the AT data has already been read, the process proceeds to step S908.
[0017]
In step S906, the AT data corresponding to the obtained physical segment is read out to the ATRAM 934 with reference to the ATIRAM 932. In step S908, a physical block corresponding to the logical address specified by the host 902 is obtained with reference to the ATRAM 934.
[0018]
In step S910, it is determined whether a corresponding physical block exists. If a corresponding physical block exists, the process proceeds to step S916. If there is no corresponding physical block, the process proceeds to step S912 because the corresponding physical block must be specified.
[0019]
In step S912, referring to the ATRAM 934, the physical segment is searched to select a physical block that has not been allocated to a logical block. In step S914, the selected physical block is associated with the specified logical block by rewriting the ATRAM 934 and the AT data. Through the above processing, a physical block corresponding to the logical address specified by the host 902 is allocated.
[0020]
Subsequently, data is written to the allocated physical block. Since the non-volatile memory erases data in units of physical blocks, when overwriting data on a page to which data has already been written, it is necessary to first erase the data of the entire block. For this reason, in step S916, the data in the non-updated area in the physical block to be overwritten is read and temporarily saved in the RAM 930. This is because such data needs to be written again.
[0021]
In step S918, after erasing the data of the physical block to be overwritten, the data saved in step S916 and the data sent from the host 902 are written together. In step S920, it is determined whether the erasing and writing in step S918 have been completed normally. If the writing has been completed normally, the writing process ends. If the processing has not been completed normally, the process proceeds to step S922.
[0022]
If it is determined in step S920 that the physical block has not been completed normally, it means that the physical block has become a bad block, and it is necessary to change the physical block corresponding to the specified logical address. Therefore, in step S922, similarly to step S912, the physical segment is searched to select a physical block that has not yet been assigned to a logical block. In step S924, the selected physical block is selected, as in step S914. Is associated with the logical block, and the ATRAM 934 and the AT data are updated. Further, in step S926, data saving, erasing, and writing are performed as in steps S916 and S918. After that, the process of step S920 is performed again.
[0023]
A related technique is disclosed in, for example, Patent Document 1.
[0024]
[Patent Document 1]
JP 2001-142774 A
[0025]
[Problems to be solved by the invention]
As a feature of the flash memory, if the writing frequency of each block varies, the possibility that the block with the highest writing frequency will be destroyed increases. For this reason, when using the flash memory, data is written so that the writing / erasing frequency of each block is as even as possible, and access such as writing / erasing is not performed on the destroyed block. Need to be managed.
[0026]
In addition, since the processing time required for writing and erasing is long, the power supply is cut off during the writing or erasing processing, especially in a non-volatile storage device such as a memory card which is likely to be used in a portable device having an unstable power supply. Even if it occurs, measures must be taken to ensure data consistency in the flash memory.
[0027]
However, in the related art, a specific logical block may always be written only to the same physical block, such as a logical block to which FAT (file allocation table) information is written. Therefore, when the host performs a process of rewriting the same logical block many times, for example, updating the FAT information, etc., even though there is an unused physical block in the same physical segment, There has been a problem that only the number of times of writing of a specific physical block increases and the life of the flash memory is shortened.
[0028]
Conventionally, when the supply of the power supply voltage from the host is interrupted at the time of rewriting data (particularly, AT data), logical inconsistency of data stored in the nonvolatile memory occurs. Therefore, there is a high possibility that data cannot be correctly read out by the host, or data is destroyed by subsequent access.
[0029]
An object of the present invention is to prevent a failure of a nonvolatile memory and extend the life of a nonvolatile memory device using the same. It is another object of the present invention to prevent stored logic data from being destroyed even when a supply voltage is reduced in a nonvolatile memory device.
[0030]
[Means for Solving the Problems]
In order to solve the above-described problem, a unit implemented by the invention of claim 1 includes, as a nonvolatile storage device, a nonvolatile memory having a plurality of physical blocks, and a controller. A plurality of physical blocks are selected as first reserved blocks, and a first table showing a correspondence relationship between an input logical address and a physical address of the non-volatile memory is selected from one of the first reserved blocks. In the case where the second table indicating the physical addresses of the plurality of first reserved blocks is stored in the non-volatile memory and writing is performed in the non-volatile memory, the first table is stored in the non-volatile memory. After the rewriting, the first reserved block is replaced with a block different from the one storing the first table before the rewriting. It is intended to store the first table.
[0031]
According to the first aspect of the present invention, the first table that is frequently rewritten is not continuously written in the same physical block every time it is updated. Can be. Therefore, the failure probability of the nonvolatile memory device can be reduced.
[0032]
Further, in the invention according to claim 2, in the nonvolatile storage device according to claim 1, the controller reads from the nonvolatile memory when writing to any of the first reserved blocks is performed a predetermined number of times or more. A plurality of the physical blocks are selected and used as a new first reserved block.
[0033]
According to the invention of claim 2, after the first reserved block is used a predetermined number of times, a new first reserved block is used. Therefore, the write frequency of the first reserved block is made substantially equal, and the second table is written. Can be written less frequently.
[0034]
According to a third aspect of the present invention, in the nonvolatile storage device according to the second aspect, the controller selects a plurality of the physical blocks as the second reserved blocks from the nonvolatile memory and stores the second table in the second table. Storing a third table indicating physical addresses of the plurality of second reserved blocks at a predetermined address in the nonvolatile memory; When the first reserved block is used, the second table is rewritten, and the second reserved block is different from the one in which the second table before rewriting is stored. The second table after rewriting is stored.
[0035]
According to the third aspect of the present invention, since the second table is not continuously written in the same physical block every time it is updated, the writing frequency of each physical block in the non-volatile memory can be made more uniform.
[0036]
According to a fourth aspect of the present invention, in the nonvolatile storage device according to the third aspect, the controller reads from the nonvolatile memory when writing to any of the second reserved blocks is performed a predetermined number of times or more. A plurality of the physical blocks are selected and used as a new second reserved block.
[0037]
According to the invention of claim 4, after the second reserved block is used a predetermined number of times, a new second reserved block is used. Therefore, the write frequency of the second reserved block is made substantially equal, and the second reserved block is written at a predetermined address. The writing frequency of the stored third table can be reduced.
[0038]
According to a fifth aspect of the present invention, in the nonvolatile storage device according to the third aspect, the controller adds the first and second tables to the third table, and It is stored at a predetermined address.
[0039]
According to the fifth aspect of the present invention, since the physical block storing the important data with a low update frequency can be directly accessed based on the description in the first table, the data can be easily processed at the time of initialization or the like. Thus, it is possible to shorten the initialization time.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0041]
(1st Embodiment)
FIG. 1 is a block diagram of the nonvolatile memory device according to the first embodiment of the present invention. The non-volatile storage device 100 of FIG. 1 includes a host interface 10, a controller 20, a RAM 30, and a non-volatile semiconductor memory 40. The host 2 is, for example, a computer or an audio player. The nonvolatile storage device 100 is, for example, a memory card.
[0042]
The host interface 10 receives a command from the host 2, performs necessary processing such as converting the command into register information, and outputs the command to the controller 20. The host interface 10 outputs the write data to the nonvolatile memory 40 output from the host 2 to the controller 20, and outputs the read data from the nonvolatile memory 40 to the host 2. The controller 20 controls operations of the host interface 10, the RAM 30, and the nonvolatile memory 40.
[0043]
The nonvolatile memory 40 is rewritable, and is, for example, a flash memory. The non-volatile memory 40 has a data area 44 for storing data sent from the host 2 and a management area 42 for storing data for managing a logical connection between the data stored in the data area 44. ing.
[0044]
The data area 44 has N + 1 physical segments (N is an integer of 0 or more). Each physical segment has a physical block for storing data sent from the host, and a plurality of AT reserved blocks (first reserved blocks). The AT reserved block stores an address translation table (also referred to as an allocation table; hereinafter, referred to as an AT) as a first table that indicates a correspondence between a physical block and a logical block in the physical segment. This is a reserved physical block. One of the AT reserved blocks is used to hold the currently valid AT.
[0045]
The management area 42 includes a physical block storing an ATI 54 as a second table indicating the address of an AT reserved block of each physical segment, and a physical block storing a pointer indicating the physical address of this physical block as an ATIP 52. Have. In particular, the physical block storing the ATIP 52 has a specific physical address, and is, for example, the leading physical block. The ATI 54 may be stored at a fixed address, or the stored address may be changed as needed in the management area 42.
[0046]
The RAM 30 includes an ATIRAM 32 that stores data of the ATI 54, an ATRAM 34 that stores a currently valid AT, and an ATI_Point 36 that stores data indicating a pointer indicating a physical block having a currently valid AT.
[0047]
When initializing the nonvolatile memory device 100, the controller 20 reads the ATI 54 into the ATIRAM 32, determines a physical block having a valid AT among the AT reserved blocks, and sends a pointer indicating the physical block determined to be valid. The indicated data is read out to the ATI_Point 36.
[0048]
FIG. 2 is an explanatory diagram of the configuration of data stored in the nonvolatile memory 40 of FIG. ATIP 52 has the physical address of ATI 54. In each physical segment, M + 1 (M is a natural number) physical blocks are reserved as AT reserved blocks as blocks for storing the AT of the physical segment. In the case of FIG. 2, as shown in the AT 70, in the physical segment 0, the physical block 1, the physical block 3, and the like are reserved as AT reserved blocks 82a and 82b, respectively. The reservation is made at the time of shipment, for example. The reserved block is not associated with the logical block. The currently valid AT 70 is stored in one of the AT reserved blocks.
[0049]
The ATI 54 stores the physical addresses of M + 1 AT reserved blocks for each physical segment. In FIG. 2, the ATI 54 indicates the relationship between a pointer for indicating the AT reservation block 82a and the physical address indicated by the pointer, and the like.
[0050]
FIG. 3 is a flowchart illustrating an example of processing at the time of writing in the nonvolatile storage device of FIG. 1. Each step in FIG. 3 will be described.
[0051]
In step S2, upon receiving a data write command from the host 2, the controller 20 obtains a physical segment to which data is to be written from the logical address specified by the host 2.
[0052]
In step S4, the controller 20 determines whether the AT of the physical segment obtained in step S2 has been read out to the ATRAM 34 or not. If it has been read, the process proceeds to step S8; otherwise, the process proceeds to step S6.
[0053]
In step S6, the controller 20 determines the physical address of the physical block in which the AT of the physical segment is stored from the data of the ATI 54 stored in the ATIRAM 32 using the data of the pointer indicating the currently valid AT stored in the ATI_Point 36. Then, the currently valid AT is read out to the ATRAM 34.
[0054]
Thereafter, in step S8, the controller 20 searches the physical segment with reference to the ATRAM 34, and selects an unallocated physical block other than the AT reserved block and not yet associated with the logical block. Here, the controller 20 randomly selects a physical block from unallocated physical blocks using, for example, a random number. In addition, the number of times of writing performed on the physical block is recorded in each physical block. May be obtained for a physical block having a small number of physical blocks.
[0055]
In step S10, the controller 20 writes the data sent from the host 2 to the selected physical block.
[0056]
In step S12, the controller 20 determines whether the writing has been completed normally. If the writing is completed normally, the process proceeds to step S14. If the writing is not completed normally, the process returns to step S8 to search for an unallocated physical block again.
[0057]
In step S14, the controller 20 refers to the ATRAM 34 to obtain a physical block corresponding to the logical address specified by the host 2.
[0058]
In step S16, the controller 20 determines whether a corresponding physical block exists. If a corresponding physical block exists, the process proceeds to step S18; otherwise, the process proceeds to step S22.
[0059]
In step S18, the controller 20 reads data corresponding to an area where data has not been sent from the host 2 and in which data has not been written from the corresponding physical block obtained in step S14, and is selected in step S8. Write to the physical block.
[0060]
In step S20, the controller 20 determines whether the writing in step S18 has been completed normally. If the process has been completed normally, the process proceeds to step S22. If the process has not been completed normally, the process returns to step S8. Thus, the process of storing the data sent from the host 2 in the nonvolatile memory 40 ends. Subsequently, the AT information of the physical segment is updated.
[0061]
In step S22, the controller 20 updates the data in the ATRAM 34 so that the selected physical block corresponds to the logical block indicated by the logical address specified by the host 2.
[0062]
In step S30, the controller 20 updates the AT and ends the writing process.
[0063]
FIG. 4 is a flowchart illustrating an example of the process in step S30 of updating the AT in FIG.
[0064]
First, in step S32, the controller 20 determines whether there is an updatable AT reservation block. That is, the controller 20 determines that there is no updatable block when all AT reserved blocks have been written a predetermined number of times (for example, once) based on the data of the ATI_Point 36. Judge and proceed to step S34. In other cases, it is determined that there is an updatable block, and the process proceeds to step S40.
[0065]
If writing has been performed a predetermined number of times or more, an AT reserved block for storing an AT is newly set in order to make the writing frequency of the entire physical segment evenly close. Therefore, in step S34, the controller 20 searches this physical segment and selects an unallocated physical block other than the AT reserved block and not yet associated with the logical block. The process in step S34 is the same as the process in step S8 except that M + 1 physical blocks are selected. The selected unallocated physical block is treated as a new AT reserved block.
[0066]
In step S36, the controller 20 updates the ATIRAM 32 and the ATRAM 34 with the physical address of the selected AT reserved block.
[0067]
In step S38, the controller 20 writes the data of the ATIRAM 32 in the management area 42 as the data of the ATI54.
[0068]
After that, in step S40, the controller 20 updates the data in the table of the ATI 54 for this physical block so that the ATI_Point 36 indicates the pointer next to the current pointer. After that, based on the data in the ATIRAM 32 and the ATI_Point 36, the data in the ATRAM 34 is written to an updatable AT reserved block.
[0069]
In step S42, the controller 20 determines whether or not the processing in step S40 has been completed normally. If the processing ends normally, the AT update processing ends. If the operation has not been completed normally, the process returns to step S32.
[0070]
As described above, according to the nonvolatile storage device of the first embodiment, a plurality of reserved blocks for writing AT data are used in the nonvolatile memory. Also, a physical block with a low writing frequency is selected as a reserved block. Since the data of the AT having a high rewriting frequency is not continuously written only in a specific physical block, the writing frequency of each physical block in the nonvolatile memory can be made closer to even. Further, the failure probability of the nonvolatile memory device can be reduced, and the life can be extended.
[0071]
In addition, when writing data from a host to a physical block, the nonvolatile storage device of the first embodiment updates the address translation table between the physical block and the logical block after the writing ends normally. For this reason, even if the supply voltage is reduced during the writing process or the power is cut off, the data before writing is valid, and data loss can be prevented. Therefore, a stable system can be constructed using this nonvolatile storage device.
[0072]
(Second embodiment)
In the second embodiment, a case will be described in which not only the AT but also the ATI is stored in any of a plurality of reserved blocks.
[0073]
FIG. 5 is a block diagram of the nonvolatile memory device according to the second embodiment of the present invention. The nonvolatile storage device 200 of FIG. 5 includes a host interface 210, a controller 220, a RAM 230, and a nonvolatile semiconductor memory 240. 5, a host interface 210 is similar to the host interface 10 of FIG.
[0074]
The non-volatile memory 240 is substantially the same as the non-volatile memory 40 of FIG. 1, and has a management area 242 and a data area 244.
[0075]
The data area 244 has N + 1 physical segments. Each physical segment includes a physical block that stores data sent from the host, a plurality of AT reserved blocks that are reserved to store ATs indicating the correspondence between physical blocks and logical blocks in the physical segment, It has a plurality of ATI reserved blocks (second reserved blocks) reserved for storing ATI, which is a table indicating addresses of AT reserved blocks for the physical segment. As in the first embodiment, one of the AT reserved blocks is used to hold the currently valid AT. In addition, one of the ATI reserved blocks is used to hold the currently valid ATI.
[0076]
The management area 242 has a physical block for storing an ATIP 252 as a third table indicating the address of an ATI reserved block of each physical segment. The physical block storing the ATIP 252 has a specific physical address, and is, for example, the first physical block. That is, the ATIP 252 is stored at a fixed address.
[0077]
The RAM 230 includes an ATI RAM 232 that stores a currently valid ATI, an ATRAM 234 that stores a currently valid AT, an ATI_Point 236 that stores data indicating a pointer indicating a physical block having a currently valid AT, and a physical having a currently valid ATI. ATIP_Point 238 for storing data indicating a pointer indicating a block.
[0078]
The controller 220 reads the ATI into the ATIRAM 232 at the time of initialization of the nonvolatile memory device 200, determines the physical block having the valid AT among the AT reserved blocks, and indicates the pointer indicating the physical block determined to be valid. To the ATI_Point 236, determination of a physical block having a valid ATI among ATI reserved blocks, and reading of data indicating a pointer indicating a physical block determined to be valid at this time to the ATIP_Point 238.
[0079]
FIG. 6 is an explanatory diagram of the configuration of data stored in the nonvolatile memory 240 in FIG. The ATIP 252 has a table indicating the address of the ATI reserved block of each physical segment.
[0080]
In each physical segment, M + 1 physical blocks are reserved as AT reserved blocks as blocks for storing the AT of the physical segment, and L + 1 (L is a natural number) a block for storing the ATI of the physical segment. ) Are reserved as ATI reserved blocks.
[0081]
In the case of FIG. 6, as shown in the table 270, in the physical segment 0, the physical block 1, the physical block 3, and the like are reserved as AT reserved blocks 282a and 282b, respectively. Further, in this physical segment, the physical block 2 and the like are reserved as the ATI reservation block 284a and the like. The reservation is made at the time of shipment, for example. The reserved block is not associated with the logical block.
[0082]
Each ATI stores the physical addresses of M + 1 AT reserved blocks for each physical segment. The ATIP 252 stores the physical addresses of L + 1 ATI reserved blocks for each of the N + 1 physical segments. In FIG. 6, the relationship between a pointer for indicating the ATI reservation block 284a and the physical address indicated by the pointer is shown in the ATIP 252. The ATI 254 stored in the ATI reservation block 284a indicates, for example, the relationship between pointers for indicating the AT reservation blocks 282a and 282b and the physical addresses indicated by these pointers.
[0083]
The processing at the time of writing in the nonvolatile memory device of FIG. 5 will be described. The main processing flow is the same as that described with reference to FIG. 3, but the processing in the step of performing the AT update is different.
[0084]
FIG. 7 is a flowchart illustrating an example of processing of a step of updating the AT at the time of writing in the nonvolatile storage device of FIG. In FIG. 7, the processing of steps S32, S34, S36, S40, and S42 is the same as that described with reference to FIG. In step S150, the controller 220 updates the ATI stored in the data area 244.
[0085]
FIG. 8 is a flowchart illustrating an example of the process in step S150 of updating the ATI in FIG.
[0086]
In step S152, as in step S32, the controller 220 determines whether there is an updatable ATI reserved block. That is, based on the data of the ATIP_Point 238, the controller 220 determines that there is no renewable block if all ATI reserved blocks have been written a predetermined number of times (for example, once) or more, and proceeds to step S154. move on. Otherwise, it is determined that there is an updatable block, and the process proceeds to step S160.
[0087]
If writing has been performed a predetermined number of times or more, an AT reserved block for storing an AT is newly set in order to make the writing frequency of the entire physical segment evenly close. Therefore, in step S154, the controller 220 selects an unallocated physical block other than the AT reserved block and the ATI reserved block and not yet associated with the logical block in this physical segment. The process in step S154 is the same as the process in step S34 except that L + 1 physical blocks are selected. The selected unallocated physical block is treated as a new ATI reserved block.
[0088]
In step S156, the controller 220 updates the ATRAM 234 with the physical address of the selected ATI reserved block.
[0089]
In step S158, the controller 220 updates the ATIP 252 in the management area 242.
[0090]
Then, in step S160, the controller 220 writes the data in the ATIRAM 232 to the ATI reserved block to be updated based on the data in the ATIP_Point 238.
[0091]
In step S162, the controller 220 determines whether the processing in step S160 has been completed normally. If the processing ends normally, the ATI update processing ends. If the operation has not been completed normally, the process returns to step S152.
[0092]
The ATIP 252 in which the physical block to be written is fixed is rewritten in this way each time all the ATI reserved blocks are used at least once, and the rewriting frequency of the ATIP 252 can be greatly reduced.
[0093]
In the nonvolatile memory device according to the second embodiment, not only the AT reserved block but also a plurality of ATI reserved blocks for writing ATI data are used in the nonvolatile memory. Also, a physical block with a low writing frequency is selected as a reserved block. Since the AT and ATI data with a high rewrite frequency are not continuously written only to specific physical blocks, the write frequency of each physical block of the non-volatile memory can be made closer to even. Further, the failure probability of the nonvolatile memory device can be reduced, and the life can be extended.
[0094]
(Third embodiment)
In the third embodiment, a case where a plurality of types of pointers are used will be described.
[0095]
FIG. 9 is a block diagram of a nonvolatile memory device according to the third embodiment of the present invention. 9 includes a host interface 310, a controller 320, a RAM 330, and a nonvolatile semiconductor memory 340. 9, a host interface 310 is similar to the host interface 10 of FIG. RAM 330 is similar to RAM 230 in FIG.
[0096]
The non-volatile memory 340 is substantially the same as the non-volatile memory 40 of FIG. 1, and has a management area 342 and a data area 344. The data area 344 has a plurality of AT reserved blocks and a plurality of ATI reserved blocks, like the data area 244 of FIG.
[0097]
The management area 342 has a physical block for storing the ATIP 352. This physical block has a specific physical address, and is, for example, a leading physical block.
[0098]
When the nonvolatile memory device 300 is initialized, the controller 320 reads the ATI into the ATIRAM 332 and determines the physical block having a valid AT among the AT reserved blocks, and determines that it is valid, as in the case of the controller 220 in FIG. To the ATI_Point 336, reading the data indicating the pointer indicating the physical block to the ATI_Point 336, determining the physical block having a valid ATI among the ATI reserved blocks, and reading the data indicating the pointer indicating the physical block determined to be valid to the ATIP_Point 338. Is read.
[0099]
FIG. 10 is an explanatory diagram of the configuration of data stored in the nonvolatile memory 340 in FIG. ATIP 352 includes a table indicating an address of an ATI reserved block of each physical segment, an ATI which is a table indicating an address of an AT reserved block for the physical segment, and a table indicating a correspondence between a physical block and a logical block in the physical segment. AT.
[0100]
In each physical segment, M + 1 physical blocks are reserved as AT reserved blocks as blocks for storing the AT of the physical segment, and L + 1 physical blocks are stored as blocks for storing the ATI of the physical segment. It is reserved as an ATI reserved block.
[0101]
In the case of FIG. 10, as shown in the table 371, in the physical segment 1, the physical block 1, the physical block 3, and the like are reserved as AT reserved blocks 382a and 382b, respectively. Further, in this physical segment, the physical block 2 and the like are reserved as the ATI reservation block 384a and the like. The reservation is made at the time of shipment, for example. The reserved block is not associated with the logical block.
[0102]
The ATI of each physical segment stores the physical addresses of M + 1 AT reserved blocks. In the case of FIG. 10, the ATIP 352 includes L + 1 physical addresses of N + 1 physical segments, that is, (N + 1) (L + 1) physical addresses of ATI reserved blocks and M + 1 AT reserved blocks of one physical segment. And a physical address corresponding to one logical block. In FIG. 10, ATI 354 is stored in ATI reservation block 384a.
[0103]
ATIP 352 has three types of tables. That is, in the first table indicating the correspondence between the physical blocks and the logical blocks, the logical blocks and the physical blocks are directly associated with each other, and the logical block itself is referred to as a zero-stage pointer. In the second table indicating the addresses of the AT reserved blocks, the pointers are associated with the addresses of the AT reserved blocks, and this pointer is referred to as a one-stage pointer. In the third table indicating the address of the ATI reserved block, the pointer is associated with the address of the ATI reserved block, and this pointer is referred to as a two-stage pointer.
[0104]
In order to access a physical block corresponding to a logical block that stores ordinary data, a two-stage pointer is used. For example, in the case of FIG. 10, when accessing the physical block of the physical segment 1, the ATIP 352 reads out the ATI with reference to the physical block 2 corresponding to, for example, a two-stage pointer described as ATI1_0. In this ATI, for example, the AT 371 stored therein is read by referring to the physical block 1 corresponding to the pointer described as AT1_0. Since the AT 371 is a currently valid AT of the physical segment 1, by referring to this, the physical block corresponding to the logical block can be accessed.
[0105]
FIG. 11 is an explanatory diagram of an access by a one-stage pointer using the data of FIG. A one-stage pointer is used to access a logical block in which the number of data updates is relatively small, such as device information.
[0106]
For example, in the case of FIG. 11, when accessing the physical block of the physical segment 0, the ATIP 352 refers to the physical block 1 corresponding to the one-stage pointer described as, for example, AT0_0, and stores the AT370 stored therein. Read out. Since the AT 370 is a currently valid AT of the physical segment 0, by referring to this, it is possible to access a physical block corresponding to a logical block.
[0107]
FIG. 12 is an explanatory diagram of an access by the 0-stage pointer using the data of FIG. A zero-stage pointer is used to access a logical block storing important data, which is rarely updated like firmware data.
[0108]
For example, in the case of FIG. 11, when accessing the logical block 0, the ATIP 352 can directly access the physical block 4 of the segment 1 corresponding to the logical block 0 indicated as, for example, a 0-stage pointer.
[0109]
Note that the logical block managed by the 0-stage pointer is also managed by the AT referenced using the 2-stage pointer or the 1-stage pointer. This is because the management of physical blocks that do not correspond to logical blocks is managed on a physical segment basis.
[0110]
The processing at the time of writing in the nonvolatile memory device of FIG. 9 will be described. The main processing flow is the same as that described with reference to FIG. 3, but the processing in the step of performing the AT update is different.
[0111]
FIG. 13 is a flowchart illustrating an example of processing of a step of updating the AT at the time of writing in the nonvolatile storage device of FIG. 9. In FIG. 13, the processing of steps S32, S34, and S40 is the same as that described with reference to FIG. 4, and the processing of step S150 is the same as that described with reference to FIG. Description is omitted.
[0112]
In step S272, the controller 320 determines whether the logical block to be written is a logical block managed by a one-stage pointer (one-stage pointer block). If it is managed by the one-stage pointer, the process proceeds to step S276; otherwise, the process proceeds to step S274.
[0113]
In step S274, the controller 320 updates the ATIRAM 332 with the physical address of the selected AT reserved block.
[0114]
In step S276, the controller 320 updates the ATIP 352 according to the physical address of the AT reserved block selected in step S34.
[0115]
In step S278, the controller 320 determines whether the processing in step S40 has been completed normally. If the operation has been completed normally, the process proceeds to step S280; otherwise, the process returns to step S32.
[0116]
In step S280, the controller 320 determines whether or not the logical block to be written is a logical block managed by the 0-stage pointer (0-stage pointer block). If it is managed by the 0-stage pointer, the process proceeds to step S282; otherwise, the process ends.
[0117]
In step S282, controller 320 updates ATIP 352 and ends the process.
[0118]
As described above, in the nonvolatile storage device according to the third embodiment, the link configuration from the management area to the physical blocks can be changed in accordance with the importance of the retained data and the writing frequency. That is, since the logical segment with a low writing frequency is managed by using the one-stage pointer, the number of ATI reserved blocks can be reduced as compared with the second embodiment. In addition, important data that is updated infrequently but is managed using the 0-stage pointer can be obtained by simple processing at the time of initialization, etc., reducing development man-hours and reducing the time required for initialization. Shortening can be achieved.
[0119]
【The invention's effect】
As described above, according to the present invention, the frequency of writing to each physical block in the nonvolatile memory can be made closer to an equal value, so that the failure of the nonvolatile memory is prevented and the life of the nonvolatile memory device using the same is extended. be able to.
[0120]
Further, since there is always a block for managing logical data in the nonvolatile memory, it is possible to prevent the logical data from being destroyed even if the voltage of the supplied power decreases.
[Brief description of the drawings]
FIG. 1 is a block diagram of a nonvolatile memory device according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram illustrating a configuration of data stored in a nonvolatile memory of FIG. 1;
FIG. 3 is a flowchart illustrating an example of a process at the time of writing in the nonvolatile storage device of FIG.
FIG. 4 is a flowchart illustrating an example of a process in a step of updating an AT in FIG. 3;
FIG. 5 is a block diagram of a nonvolatile memory device according to a second embodiment of the present invention.
FIG. 6 is an explanatory diagram illustrating a configuration of data stored in a nonvolatile memory in FIG. 5;
FIG. 7 is a flowchart illustrating an example of processing of a step of updating an AT at the time of writing in the nonvolatile storage device of FIG. 5;
FIG. 8 is a flowchart illustrating an example of a process in a step of updating an ATI in FIG. 7;
FIG. 9 is a block diagram of a nonvolatile memory device according to a third embodiment of the present invention.
FIG. 10 is an explanatory diagram illustrating a configuration of data stored in a nonvolatile memory in FIG. 9;
FIG. 11 is an explanatory diagram of access by a one-stage pointer using the data of FIG. 10;
FIG. 12 is an explanatory diagram of an access by a 0-stage pointer using the data of FIG. 10;
13 is a flowchart illustrating an example of processing of a step of updating an AT at the time of writing in the nonvolatile storage device of FIG. 9;
FIG. 14 is an explanatory diagram of data management in a general nonvolatile storage device.
FIG. 15 is a block diagram illustrating an example of a configuration of a conventional nonvolatile storage device.
16 is an explanatory diagram showing a data structure in a management area of the nonvolatile memory in FIG.
FIG. 17 is a flowchart illustrating an example of a process at the time of writing in the nonvolatile storage device of FIG. 15;
[Explanation of symbols]
20, 220, 320 controller
40,240,340 Non-volatile memory
52,252,352 ATIP (third table)
54,254,354 ATI (second table)
70, 270, 370, 371 AT (first table)
82a, 82b, 282a, 282b, 382a, 382b AT reserved block (first reserved block)
284a, 384a ATI reserved block (second reserved block)

Claims (5)

A non-volatile memory having a plurality of physical blocks,
With a controller,
The controller is
A plurality of physical blocks are selected from the nonvolatile memory as first reserved blocks, and a first table showing a correspondence between an input logical address and a physical address of the nonvolatile memory is stored in the first reserved block. When storing in any one of them, the second table indicating the physical addresses of the plurality of first reserved blocks is stored in the non-volatile memory, and writing to the non-volatile memory is performed, Rewriting the first table, and storing the rewritten first table in a different one of the first reserved blocks from the one storing the first table before rewriting. A non-volatile storage device. The nonvolatile storage device according to claim 1,
The controller is
When writing to any of the first reserved blocks is performed a predetermined number of times or more, a plurality of the physical blocks are selected from the nonvolatile memory and used as the new first reserved blocks. Nonvolatile storage device. The nonvolatile storage device according to claim 2,
The controller is
Selecting a plurality of the physical blocks from the nonvolatile memory as second reserved blocks, storing the second table in any one of the second reserved blocks, and selecting the plurality of second reserved blocks; In the case where a third table indicating the physical address of the non-volatile memory is stored at a predetermined address in the nonvolatile memory, and the new first reserved block is used, the second table is rewritten and the second table is rewritten. A non-volatile memory device, wherein a reserved block stores the second table after rewriting in a block different from the one in which the second table before rewriting is stored. The nonvolatile storage device according to claim 3,
The controller is
When writing to any of the second reserved blocks is performed a predetermined number of times or more, a plurality of the physical blocks are selected from the nonvolatile memory and used as a new second reserved block. Nonvolatile storage device. The nonvolatile storage device according to claim 3,
The controller is
The nonvolatile storage device according to claim 1, wherein the first table and the second table are added to the third table and stored at the predetermined address of the nonvolatile memory.

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