JP2004228356A - Semiconductor integrated circuit and method for designing its layout - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for designing a layout for a semiconductor integrated circuit which enables efficient utilization of a space where no cell has been arranged. <P>SOLUTION: The method for designing a layout comprises: a step (a) of arranging plural kinds of standard cells in a layout region, each comprised of a plurality of base circuit blocks for realizing desired functions in accordance with a given circuit included in the semiconductor integrated circuit; a step (b) of arranging plural kinds of divided cells in the layout region, each comprised of a plurality of circuit portions divided from a single base circuit in accordance with each of the remaining circuits included in the semiconductor integrated circuit; and a step (c) of giving wiring between the plural kinds of standard cells arranged in the step (a) and the plural kinds of divided cells arranged in the step (b). <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a layout design method for a semiconductor integrated circuit, and further relates to a semiconductor integrated circuit manufactured using such a layout design method.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor integrated circuit such as a gate array, a layout design is performed by using a computer to arrange and connect a plurality of types of cells constituting a circuit block that realizes a desired function. Each cell is composed of a plurality of transistors, a wiring pattern in the cell for connecting the transistors, and an input / output wiring pattern for connecting the input / output of the cell. A function such as a gate, an OR gate or a NOR gate, a flip-flop, an inverter, or a buffer is realized.
[0003]
In a conventional layout design using such cells, a plurality of types of cells are combined and arranged so that cells having the same function have the same layout, and wiring between these cells is performed.
[0004]
However, when designing the entire layout area of the semiconductor substrate, the size of the cell to be arranged does not match the empty space, even though there is an empty space where no cells are arranged. In some cases it had to be increased.
[0005]
Japanese Patent Application Laid-Open No. H11-163873 discloses a design method for a semiconductor device having a layout in which the shape, internal element arrangement, and inter-element wiring are different from each other with respect to a functional cell. According to this design method, a plurality of layouts corresponding to a certain functional cell are prepared such as a layout having a different shape, a layout having a different element arrangement, and a layout having a different wiring between internal elements. However, even if a plurality of types of layouts having different shapes, element arrangements, or element-to-element wirings are prepared for one functional cell, their sizes are almost the same. Can not.
[0006]
[Patent Document 1]
JP-A-11-3943 (Page 1, FIG. 1)
[0007]
[Problems to be solved by the invention]
In view of the above, it is an object of the present invention to provide a layout design method capable of effectively utilizing an empty space where cells have not been conventionally arranged when designing a layout of a semiconductor integrated circuit. And Another object of the present invention is to provide a semiconductor integrated circuit manufactured using such a layout design method.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, a layout design method according to the present invention is a method for designing a layout of a semiconductor integrated circuit using a computer, and each of the methods corresponds to a predetermined circuit included in the semiconductor integrated circuit. (A) arranging a plurality of types of standard cells respectively forming a plurality of basic circuit blocks for realizing a desired function in a layout area; and one basic circuit corresponding to the remaining circuits included in the semiconductor integrated circuit. A step (b) of arranging a plurality of types of divided cells respectively constituting a plurality of circuit portions divided from a block in a layout area; (C) performing wiring between the plurality of types of divided cells.
[0009]
In addition, a semiconductor integrated circuit according to the present invention includes a first group of circuits formed on a semiconductor substrate, each of which is configured by a plurality of basic circuit blocks each of which realizes a desired function; A second group of circuits each configured by a plurality of circuit portions divided from the basic circuit block.
[0010]
Here, the basic circuit block may include an AND gate, a NAND gate, an OR gate, a NOR gate, a flip-flop, an inverter, or a buffer.
[0011]
According to the present invention configured as described above, when designing the layout of a semiconductor integrated circuit, by using a plurality of types of divided cells respectively constituting a plurality of circuit portions divided from one basic circuit block, The arrangement efficiency can be improved by effectively utilizing the empty space where cells have not been arranged conventionally. As a result, the area of the semiconductor substrate can be reduced.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the same components are denoted by the same reference numerals, and description thereof will be omitted.
FIG. 1 is a flowchart showing a layout design method of a semiconductor integrated circuit according to one embodiment of the present invention.
First, in step S1, a circuit design of a semiconductor integrated circuit is performed, and a net list is created. The netlist includes information on a plurality of cells for forming various circuits in a semiconductor integrated circuit and information on wiring between these cells. In step S2, the created net list is input to a computer.
[0013]
Next, automatic placement and routing based on the netlist are performed using an automatic placement and routing tool operating on a computer.
In step S3, a plurality of types of standard cells are arranged in a layout area corresponding to a predetermined circuit included in the semiconductor integrated circuit. Here, it is desirable to arrange standard cells for 70% to 90% of the entire circuit included in the semiconductor integrated circuit. Each standard cell constitutes a basic circuit block that realizes a desired function. The basic circuit block includes an AND gate, a NAND gate, an OR gate, a NOR gate, a flip-flop, an inverter, a buffer, and the like.
[0014]
FIG. 2 shows a circuit configuration of an AND gate as an example of the basic circuit block. The basic circuit block 10 of the AND gate shown in FIG. 2 includes P-channel transistors QP1 to QP3 and N-channel transistors QN1 to QN3, and outputs a signal applied to the input terminal A and a signal applied to the input terminal B. The logical product is obtained and output from the output terminal O.
[0015]
Referring to FIG. 1 again, in step S4, a plurality of types of divided cells are arranged in the layout area corresponding to the remaining circuits included in the semiconductor integrated circuit. These divided cells constitute a plurality of circuit portions divided from one basic circuit block, and have the same functions as the original basic circuit block, but have enhanced current supply capability and the like. Alternatively, the circuit may be changed. Such divided cells are arranged in an empty space between the standard cells already arranged. As described above, when standard cells are already arranged for 70% to 90% of the entire circuit, divided cells are arranged for 30% to 10% of the entire circuit included in the semiconductor integrated circuit.
[0016]
FIG. 3 shows first to third circuit portions obtained by dividing the basic circuit block of the AND gate into three parts. As shown in FIG. 3, first circuit portion 21 includes P-channel transistors QP1 and QP2, second circuit portion 22 includes N-channel transistors QN1 and QN2, and third circuit portion 23 includes P-channel transistor QP3. And an N-channel transistor QN3.
[0017]
Referring to FIG. 1 again, in step S5, wiring is performed between the plurality of types of standard cells and the plurality of types of divided cells, and the layout design is completed.
[0018]
FIG. 4 is a layout diagram showing an example of a standard cell in a semiconductor integrated circuit according to one embodiment of the present invention, and FIG. 5 is a layout showing an example of a divided cell in a semiconductor integrated circuit according to one embodiment of the present invention. FIG. Here, as an example, a layout of an AND gate as shown in FIG. 2 or FIG. 3 is shown.
[0019]
In the standard cell shown in FIG. 4, a basic circuit block 10 which is formed on a semiconductor substrate and realizes the function of an AND gate is formed. In the three divided cells shown in FIG. 5, a first circuit part 21, a second circuit part 22, and a first circuit part 21 formed on a semiconductor substrate and obtained by dividing a basic circuit block of an AND gate into three parts are formed. 3 circuit portions 23 are formed.
[0020]
As shown in FIG. 5, the circuit portions 21 to 23 obtained by dividing the basic circuit block of the AND gate into three parts are sufficiently smaller than the basic circuit block 10 of the AND gate. Therefore, it is possible to disperse and arrange these divided cells in the empty space between the already arranged standard cells, and to effectively utilize the empty space where cells have not been conventionally arranged. can do.
[0021]
The present invention is not limited to the above-described embodiment, and may be applied to a case in which transistors are connected in parallel in order to improve the current supply capability of the buffer in view of the result of circuit simulation after layout design using standard cells, The present invention can also be applied to a case where specifications are changed. According to the present invention, it is possible to arrange divided cells in a small empty space, so that the need for large-scale correction is reduced, and the time required for product development can be shortened.
[0022]
[Brief description of the drawings]
FIG. 1 is a flowchart showing a layout design method according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a circuit configuration example of a basic circuit block.
FIG. 3 is a circuit diagram showing a circuit portion divided from a basic circuit block.
FIG. 4 is a layout diagram showing an example of a standard cell according to an embodiment of the present invention.
FIG. 5 is a layout diagram showing an example of a divided cell according to an embodiment of the present invention.
[Explanation of symbols]
Reference Signs List 10 basic circuit blocks, 21 to 23 circuit parts obtained by dividing basic circuit blocks, QP1 to QP3 P-channel transistors, QN1 to QN3 N-channel transistors

Claims (3)

A method of designing a layout of a semiconductor integrated circuit using a computer,
(A) arranging, in a layout area, a plurality of types of standard cells each constituting a plurality of basic circuit blocks, each of which realizes a desired function, corresponding to a predetermined circuit included in the semiconductor integrated circuit;
(B) arranging, in a layout area, a plurality of types of divided cells respectively constituting a plurality of circuit portions divided from one basic circuit block corresponding to the remaining circuits included in the semiconductor integrated circuit;
(C) wiring a plurality of types of standard cells arranged in step (a) and a plurality of types of divided cells arranged in step (b);
Layout design method comprising: A semiconductor integrated circuit,
A first group of circuits formed on a semiconductor substrate and each constituted by a plurality of basic circuit blocks each implementing a desired function;
A second group of circuits formed on the semiconductor substrate, each including a plurality of circuit portions divided from one basic circuit block;
A semiconductor integrated circuit comprising: 3. The semiconductor integrated circuit according to claim 2, wherein the basic circuit block includes an AND gate, a NAND gate, an OR gate, a NOR gate, a flip-flop, an inverter, or a buffer.

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