JP2004226995A - Method for manufacturing photomask, and photomask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the time for changing or correcting the pattern of a mask. <P>SOLUTION: A halftone pattern 3c made of a resist film as well as a light-shielding pattern 2a made of a metal for transferring an integrated circuit pattern is disposed on a mask substrate 1 constituting a photomask PM5. The halftone pattern 3c is a phase regulating pattern which inverts the phase of exposure light. The transmittance of the halftone pattern 3c for the light transmitting the pattern is about 2 to 10% with respect to the light before transmitting the pattern 3c, which means the halftone pattern 3c substantially functions as a light shielding part. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a photomask and a photomask technology, and more particularly to a technology effective when applied to a lithography technology.

  For example, in manufacturing a semiconductor integrated circuit device, a lithography technique is used as a method of transferring a fine pattern onto a semiconductor wafer. In lithography technology, a projection exposure apparatus is mainly used, and a device pattern is formed by transferring a pattern of a photomask (hereinafter simply referred to as a mask) mounted on the projection exposure apparatus onto a semiconductor wafer (hereinafter simply referred to as a wafer). I do.

  The mask pattern of a normal mask studied by the present inventors is formed by patterning a light-shielding film such as chromium (Cr) formed on a transparent quartz substrate. The pattern processing of this light-shielding film is, for example, as follows. First, an electron beam-sensitive resist is applied on a light-shielding film, a desired pattern is drawn on the electron beam-sensitive resist by an electron beam drawing apparatus, and a resist pattern having a desired shape is formed by development. Subsequently, after the light-shielding film is patterned by dry etching or wet etching using the resist pattern as an etching mask, removal and cleaning of the resist pattern are sequentially performed to form a light-shielding pattern of a desired shape on a transparent quartz substrate. I have.

  Also, various mask structures have been proposed for the purpose of improving the resolution of lithography in recent years. For example, Japanese Patent Application Laid-Open No. 4-136854 discloses a technique using a halftone phase shift mask as a means for improving the resolution of a single transparent pattern (see Patent Document 1). In this technique, the periphery of a single transparent pattern is made translucent, that is, with the light shielding portion of the mask being made translucent, a small amount of light less than the sensitivity of the photoresist passing through the translucent portion, and the transparent pattern The phase of light passing through is inverted. Since the light that has passed through the translucent film has a phase inverted with respect to the light that has passed through the transparent pattern, which is the main pattern, the phase is inverted at the boundary and the light intensity at the boundary is zero (0). Approach. As a result, the ratio of the intensity of light that has passed through the transparent pattern and the intensity of light at the boundary of the pattern is relatively large, and a light intensity distribution with a higher contrast is obtained as compared with a technique using no translucent film. This halftone type phase shift mask is obtained by changing the light-shielding film of the ordinary mask to a halftone phase shift film, and is manufactured in substantially the same steps as those of the ordinary mask.

  Further, for example, Japanese Patent Application Laid-Open No. 5-289307 discloses a technique in which a light-shielding film is formed of a resist film for the purpose of simplifying the manufacturing process of a mask and increasing the accuracy (see Patent Document 2). This method utilizes the property that ordinary electron beam-sensitive resists and light-sensitive resists shield vacuum ultraviolet light having a wavelength of about 200 nm or less. According to this method, the step of etching the light-shielding film and the step of removing the resist become unnecessary, so that the cost of the mask can be reduced, the dimensional accuracy can be improved, and the defects can be reduced.

  Also, for example, Japanese Patent Application Laid-Open No. 55-22864 describes a lithography mask technique having a pattern formed by laminating a metal film and an organic material layer, and patterning a chromium layer on a main surface of a glass substrate. A technique for improving the shielding effect against exposure light by irradiating a photoresist pattern for irradiation with argon ions and fixing the photoresist pattern to a chrome layer pattern is disclosed (see Patent Document 3).

  Further, for example, Japanese Patent Application Laid-Open No. 60-85525 discloses that after a photoresist is coated on a mask having a defect to be repaired, a focused charged particle beam is irradiated on a small area of the photoresist to repair the mask. There is disclosed a technique of forming a film into an opaque state (see Patent Document 4).

Also, for example, Japanese Patent Application Laid-Open No. 54-83377 discloses a technique for correcting a pattern by embedding an opaque emulsion in a locally defective portion of a photomask (see Patent Document 5).
JP-A-4-136854 JP-A-5-289307 JP-A-55-22864 JP-A-60-85525 JP-A-54-83377

  However, the present inventors have found that the above-mentioned mask technology has the following problems.

  That is, there is a problem that it is not possible to quickly respond to change or correction of the mask pattern on the mask. In the manufacturing process of the semiconductor integrated circuit device, in order to realize a semiconductor chip configuration in accordance with the specification required by the customer, adjust the characteristics in order to rewrite the memory information for the customer's request during product development and manufacturing. In some cases, the circuit pattern is changed or modified for repairing a defective circuit. For example, Japanese Patent Application Laid-Open No. 63-274156 discloses that in the manufacture of a semiconductor integrated circuit device having a built-in ROM (Read Only Memory), it is necessary to frequently change wiring for writing information to the ROM. Have been. However, in the case of a normal mask, it is necessary to prepare a mask substrate, deposit a chromium film, and perform pattern processing every time the design is changed or corrected, so that it takes time to manufacture the mask. Therefore, a great deal of time and effort is required to develop or manufacture a semiconductor integrated circuit device that meets the specifications required by the customer.

  Further, in the above-described technology for forming a light-shielding pattern of a mask with a resist film, problems in using the mask in a manufacturing process of a semiconductor integrated circuit device, problems in manufacturing the mask, and countermeasures are disclosed. There are, for example, the following issues.

  The first problem is that it is difficult to detect a predetermined pattern used for detecting various kinds of information such as an alignment mark of a mask, a pattern measurement mark, or a product determination mark. For example, currently used mask defect inspection apparatuses and exposure apparatuses mainly use a halogen lamp or the like for mask alignment. Therefore, when the mask is mounted on a defect inspection apparatus, an exposure apparatus, or the like, if the detection mark on the mask is formed by a resist film pattern, the light transmittance of the resist film is high and a high contrast can be obtained. Since it is not possible, it is difficult to detect the pattern. For this reason, it is difficult to align the mask with a defect inspection device, an exposure device, or the like, and there is a problem that good inspection and exposure cannot be performed.

  The second problem is that foreign matter is generated when the mask is mounted on a defect inspection device, an exposure device, or the like. In the above technique, when the mask is mounted on a defect inspection apparatus, an exposure apparatus, or the like, the resist film of the mask comes into direct contact with a mask fixing member (for example, vacuum fixing) of the defect inspection apparatus, the exposure apparatus, or the like. Foreign matter is generated due to chipping or chipping of the resist film. This foreign matter causes deterioration of pattern inspection accuracy and transfer accuracy, for example, due to adhesion to the surface of a lens of an inspection apparatus or exposure apparatus, contamination of a chamber, or adhesion to the surface of a semiconductor wafer. Or a failure such as a short-circuit failure or an open-circuit failure of the pattern occurs, so that the reliability and the yield of the semiconductor integrated circuit device are reduced.

  Third, when a pellicle is pasted on a mask, if the resist film is present at the portion where the pellicle is adhered, the pellicle cannot be adhered well, the pellicle is easily peeled off, and foreign matter is generated when the pellicle is peeled off.

  An object of the present invention is to provide a technique capable of shortening the time required to change or correct a mask pattern in a mask.

  It is another object of the present invention to provide a technique capable of improving information detection capability in a mask that functions as a light-shielding film using a resist film.

  Another object of the present invention is to provide a technique capable of suppressing or preventing the generation of foreign matter in an exposure process using a mask that makes a resist film function as a light-shielding film.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the present invention provides (a) a step of forming a light-shielding pattern made of a metal for transferring an integrated circuit pattern on a mask substrate, (b) a step of depositing a first resist film on the mask substrate, and (c). Depositing a second resist film on the first resist film, (d) forming a light-shielding pattern by patterning the second resist film, and (e) starting from the second resist film. Using a light-shielding pattern as an etching mask to pattern the first resist film.

  In addition, among the inventions disclosed in the present application, the outline of another invention will be briefly described as follows.

  That is, the present invention includes a step of forming a light-shielding pattern formed of a resist film for transferring an integrated circuit pattern on a part of a mask substrate.

  Further, the present invention includes a step of forming a light-shielding pattern made of a metal for transferring an integrated circuit pattern on a mask substrate and a step of forming a light-shielding pattern made of a resist film for transferring an integrated circuit pattern on the mask substrate.

  Further, according to the present invention, at the time of forming the light-shielding pattern made of a metal for transferring an integrated circuit pattern, a light-shielding pattern made of a metal is formed around the main surface of the mask substrate.

  According to the present invention, a pellicle is fixedly contacted with a metal light-shielding pattern in a peripheral portion of a main surface of the mask substrate.

  According to the present invention, an opening is provided in the light-shielding pattern made of metal in a peripheral portion of the main surface of the mask substrate.

  Further, the present invention includes a step of forming a light-shielding pattern made of a metal for transferring an integrated circuit pattern on a mask substrate, and a step of forming a light-shielding pattern made of a resist film for transferring an integrated circuit pattern on the mask substrate. .

  According to the present invention, a light-shielding pattern made of a metal for transferring an integrated circuit pattern and a light-shielding pattern made of a resist film for transferring the integrated circuit pattern are provided on a mask substrate.

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
(1) According to the present invention, by forming a light-shielding pattern made of a resist film for transferring an integrated circuit pattern on a part of a mask substrate, it is possible to shorten the time required to change or correct the pattern of the mask. .
(2) According to the present invention, a light-shielding portion made of metal is provided around the main surface of the mask substrate, and an information detection pattern is formed by providing an opening in the light-shielding portion. In a mask that functions as a light shielding portion, it is possible to improve information detection ability.
(3) According to the present invention, by providing a light-shielding portion made of metal in the periphery of the main surface of the mask substrate, the generation of foreign matter during exposure processing using a mask that makes the resist film function as a light-shielding film is prevented. It can be suppressed or prevented.

  Before describing the present invention in detail, the meanings of terms in the present application will be described as follows.

  1. Mask (optical mask): A pattern in which a pattern that blocks light or a pattern that changes the phase of light is formed on a substrate. A reticle on which a pattern several times the actual size is formed is also included. The term “on the substrate” includes the upper surface of the substrate, the internal region or the sky region adjacent to the upper surface of the substrate (may be disposed on another substrate adjacent to the upper surface). The first main surface of the mask is a surface on which the pattern for blocking the light or the pattern for changing the phase of light is formed, and the second main surface of the mask is on the side opposite to the first main surface. Of the face. An ordinary mask (binary mask) is a general mask in which a mask pattern is formed on a substrate by using a pattern that blocks light and a pattern that transmits light.

  2. The pattern surface of the mask is classified into the following areas. The area where the integrated circuit pattern to be transferred is arranged “integrated circuit pattern area”, the area covered with pellicle “pellicle cover area”, the pellicle cover area other than the integrated circuit pattern area “peripheral area of integrated circuit pattern”, pellicle The outer area not covered by the "peripheral area", of the peripheral area, the inner area where the optical pattern is formed, the "peripheral internal area", and other peripheral areas used for vacuum suction etc. region".

  3. When the term “metal” is used for the mask light-shielding material, it refers to chromium, chromium oxide, other metals and metal compounds, and broadly includes simple substances, compounds, composites, and the like containing a metal element and having a light-shielding effect.

4. The terms "light-shielding region", "light-shielding film", and "light-shielding pattern" indicate that the region has an optical property of transmitting less than 40% of exposure light applied to the region.
In general, those having several percent to less than 30% are used. On the other hand, when referring to “transparent”, “transparent film”, “light transmitting area”, and “light transmitting pattern”, it is necessary to have an optical property of transmitting 60% or more of exposure light applied to the area. Show. Generally, 90% or more is used. A general concept of a light-shielding region, a light-shielding film and a light-shielding pattern formed of a metal or a resist film is called a light-shielding portion.

  5. Halftone mask: A kind of phase shift mask that has a transmittance of 1% or more and less than 40% for a halftone film that also serves as a shifter and a light-shielding film. It has a halftone shifter for inversion.

  6. Levenson-type phase shift mask: A type of phase shift mask that inverts the phases of adjacent openings separated by a light-shielding region to obtain a clear image by the interference action.

  7. Normal illumination: Non-deformed illumination, which refers to illumination with a relatively uniform light intensity distribution.

  8. Deformation illumination: Illumination with reduced illuminance at the center, including multi-pole illumination such as oblique illumination, annular illumination, quadrupole illumination, and quintuple illumination, or a super-resolution technique using a pupil filter equivalent thereto. .

9. Resolution: The pattern dimension can be expressed by standardizing the numerical aperture NA (Numerical Aperture) of the projection lens and the exposure wavelength λ. When a different wavelength or a different lens NA is used, the resolution R is represented by R = K1 · λ / NA, so that it may be converted and used. However, since the depth of focus D is also represented by D = K2 · λ / (NA) ² , the depth of focus is different.

  10. In the field of semiconductors, ultraviolet light is classified as follows. The wavelength is less than about 400 nm, about 50 nm or more is ultraviolet ray, 300 nm or more is near ultraviolet ray, less than 300 nm, 200 nm or more is far ultraviolet ray, and less than 200 nm is vacuum ultraviolet ray. The main embodiment of the present application will be described focusing on the vacuum ultraviolet region of less than 200 nm. However, if a change as described in the following example is made, the deep ultraviolet region with a KrF excimer laser of less than 250 nm and 200 nm or more can be obtained. However, it is needless to say that it is possible. In addition, the principle of the present invention can be similarly applied to a short wavelength end region of ultraviolet light of less than 100 nm and 50 nm or more.

  11. Scanning exposure: A thin slit-shaped exposure band is formed in a direction perpendicular to the longitudinal direction of the slit with respect to a semiconductor wafer and a photomask (or a reticle, which is a broad concept including a reticle when referred to as a photomask in the present application). This is an exposure method in which a circuit pattern on a photomask is transferred to a desired portion on a semiconductor wafer by relatively continuous movement (scanning).

  12. Step and scan exposure: a method of exposing the entire portion of a wafer to be exposed by combining the scanning exposure and the stepping exposure, and corresponds to a lower concept of the scanning exposure.

  13. A semiconductor integrated circuit wafer (semiconductor integrated circuit substrate) or a wafer (semiconductor substrate) is a silicon single crystal substrate (generally a substantially circular shape) used for manufacturing a semiconductor integrated circuit, a sapphire substrate, a glass substrate, or other insulating, anti-insulating or Refers to semiconductor substrates and the like and composite substrates thereof.

  14． The device surface refers to a main surface of the wafer on which device patterns corresponding to a plurality of chip regions are formed by photolithography.

  15. Masking layer: generally refers to a resist film, but also includes an inorganic mask, a non-photosensitive organic mask, and the like.

  16. Transfer pattern: a pattern transferred onto a wafer by a mask, specifically, the photoresist pattern and a pattern on the wafer actually formed using the photoresist pattern as a mask.

  17. Resist pattern: A film pattern obtained by patterning a photosensitive organic film by a photolithography technique. Note that this pattern includes a simple resist film having no opening in the relevant portion.

  18. Hole pattern: A fine pattern such as a contact hole or a through hole having a two-dimensional size on the wafer which is about the same as or smaller than the exposure wavelength. In general, the shape is a square, a rectangle close to the square, an octagon, or the like on a mask, but is often close to a circle on a wafer.

  19. Line pattern: A band-like pattern extending in a predetermined direction.

  20. Custom circuit pattern: A pattern that constitutes a circuit, such as a custom I / O circuit or a custom logic circuit, whose design is changed in response to a customer request.

  21. Redundant circuit pattern: A pattern constituting a circuit for replacing a spare circuit formed on an integrated circuit with a defective circuit.

  In the following embodiments, when necessary for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other and one is the other. In some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), a case where it is particularly specified, and a case where it is clearly limited to a specific number in principle, etc. However, the number is not limited to the specific number, and may be more than or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified, and when it is deemed essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, the shapes are substantially the same unless otherwise specified and in cases where it is considered that it is not clearly apparent in principle. And the like. This is the same for the above numerical values and ranges.

  In the present application, the term “semiconductor integrated circuit device” refers not only to a device formed on a semiconductor such as a silicon wafer or a sapphire substrate or an insulator substrate, but also to a TFT (Thin-Film film) unless otherwise specified. -Transistor) and those made on other insulating substrates such as glass such as STN (Super-Twisted-Nematic) liquid crystal.

  In all the drawings for describing the present embodiment, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

  In the drawings used in the present embodiment, hatching may be applied to a light-shielding pattern or a phase shift pattern even in a plan view so as to make the drawings easy to see.

  In this embodiment, a MIS • FET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel MIS • FET is abbreviated as pMIS, and an n-channel MIS • FET is used. Is abbreviated as nMIS.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1A is a plan view of a photomask according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A when the photomask is mounted on a predetermined device.

  The mask PM1 of the first embodiment is a reticle for forming and transferring an original image of an integrated circuit pattern having a size of 1 to 10 times the actual size on a wafer through a reduction projection optical system or the like. Here, a mask in the case where the periphery of the semiconductor chip becomes a light shielding portion, and a mask in the case of forming a line pattern using a positive resist film on a wafer is illustrated.

  The mask substrate 1 of the mask PM1 is made of, for example, a transparent synthetic quartz glass plate having a thickness of about 6 mm and formed in a plane quadrangular shape. At the center of the main surface of the mask substrate 1, a light-transmitting opening region having a flat rectangular shape is formed, and the main surface of the mask substrate 1 is exposed. This light transmission opening area forms the integrated circuit pattern area. In this integrated circuit pattern region, light-shielding patterns 2a and 3a for transferring the integrated circuit pattern onto the wafer are arranged on the main surface of the mask substrate 1. Here, a case where the light-shielding patterns 2a and 3a are transferred as a line pattern on a wafer is illustrated.

In the present embodiment, the light-shielding pattern 2a is formed of metal as in the case of a normal mask, but the light-shielding pattern 3a of a part of the region RE (region indicated by a broken line) in the integrated circuit pattern region is formed of a resist film. Is formed. Therefore, as described later, the light-shielding pattern 3a in the region RE can be relatively easily removed. Then, it is possible to easily form a new light shielding pattern 3a in a short time. Resist film, for example, have the property of absorbing KrF excimer laser beam (wavelength 248 nm), ArF excimer laser beam (wavelength 193 nm) or F ₂ laser beam (wavelength 157 nm) exposure light such as to form a light-shielding pattern 3a And has a light-shielding function substantially similar to that of the light-shielding pattern 2a formed of metal. The structure of the material of the resist film will be described later. The technique of forming a light-shielding pattern using a resist film is described in Japanese Patent Application No. 11-185221 (filed on June 30, 1999) by the present inventors.

  The outer periphery of the integrated circuit pattern area on the main surface of the mask substrate 1 is covered with a light shielding pattern 2b. The light-shielding pattern 2b is formed in a planar frame shape from the outer periphery of the integrated circuit pattern region to the outer periphery of the mask substrate 1. For example, the light-shielding pattern 2b is formed of the same metal as the light-shielding pattern 2a in the same pattern processing step. The light-shielding patterns 2a and 2b are, for example, chromium or chromium oxide deposited on chromium. However, the material of the light-shielding patterns 2a and 2b is not limited to this, and can be variously changed. For example, a refractory metal such as tungsten, molybdenum, tantalum, or titanium; a nitride such as tungsten nitride; A refractory metal silicide (compound) such as tungsten silicide (WSix) or molybdenum silicide (MoSix) or a laminated film of these may be used. In the case of the mask PM1 of the present embodiment, after removing the light-shielding pattern 3a formed of a resist film, the mask substrate 1 may be washed and used again, so that the light-shielding patterns 2a and 2b have peel resistance. And materials having high wear resistance are preferred. A high melting point metal such as tungsten is preferable as a material for the light-shielding patterns 2a and 2b because it has high oxidation resistance and abrasion resistance, and has high separation resistance.

  A substantially octagonal framed area on the light-shielding pattern 2b indicates the pellicle cover area. That is, here, the case where the pellicle PE is bonded to the main surface side of the mask substrate 1 of the mask PM1 via the pellicle attachment frame PEf is illustrated. The pellicle PE is a structure having a transparent protective film, and is provided at a certain distance from the main surface or the main surface and the back surface of the mask substrate 1 in order to prevent foreign substances from adhering to the mask PM1. This certain distance is designed in consideration of the foreign matter attached to the surface of the protective film and the transferability of the foreign matter to the wafer.

  The base of the pellicle attachment frame PEf is bonded and fixed in direct contact with the light-shielding pattern 2b of the mask PM1. Thereby, peeling of the pellicle attachment frame PEf can be prevented. Further, if a resist film is formed at the position where the pellicle attachment frame PEf is attached, the resist film peels off when the pellicle PE is attached / detached, thereby causing the generation of foreign matter. By joining the pellicle attachment frame PEf in a state where the pellicle attachment frame PEf is in direct contact with the light shielding pattern 2b, such generation of foreign matter can be prevented.

  In the pellicle cover area, an area excluding the integrated circuit pattern area indicates a peripheral area of the integrated circuit pattern. In the peripheral region of the integrated circuit pattern, a mark pattern 4a for detecting information of the mask PM1 is formed. The mark pattern 4a is a pattern for directly detecting positional information of the mask PM1 from the mask PM1 when a predetermined pattern is drawn on the mask PM1 using an electron beam drawing apparatus. That is, when a predetermined integrated circuit pattern is drawn on the integrated circuit pattern area of the mask PM1 using the electron beam drawing apparatus, the mark pattern 4a of the mask PM1 is read once every few seconds, and the Pattern writing while correcting (adjusting) the irradiation position of the electron beam. This makes it possible to improve the pattern writing position accuracy by the electron beam writing apparatus. Such a mark pattern 4a is provided for the following reason, for example.

  That is, in a normal electron beam lithography system, the lithography process on the mask is performed in a vacuum. As shown schematically in FIG. 2, the mask is held in a vacuum by pressing the mask PM1 or the cassette 201 on which the mask PM1 is mounted on the three-point pin 200a of the mask holding unit 200 on the moving stage of the electron beam writing apparatus. , And is mechanically fixed by a pressing pin 200b. Here, in a normal electron beam lithography apparatus, a mark pattern 200m for position detection, which is attached to the mask holding unit 200 for the purpose of preventing a pattern writing position shift due to a position drift of an electron beam during writing, is being drawn. Detected multiple times to correct for misalignment. Since the mask PM1 of the mask holding unit 200 (stage) is mechanically fixed as described above, the relative positional relationship between the mark pattern 200m of the mask holding unit 200 and the mask PM1 should be constant. In some cases, a slight displacement may occur between the mark pattern 200m and the mask PM1 due to the impact of the stage moving at high speed. For this reason, although the position of the mask PM1 is read from the mark pattern 200m during the electron beam writing process, a position shift occurs in the writing pattern. Therefore, the mark pattern 4a for position correction is arranged on the mask PM1 itself, and the position is directly detected from the mask PM1 itself. This makes it possible to correct for the misalignment of the mask PM1 as well, thereby reducing pattern alignment errors. Such a mark pattern 4a is constituted by, for example, whether the pattern position is a light transmitting area or a light shielding area, and information detection is performed by a position detection beam or a reflection state of the detection light applied thereto. Is to be done. As the position detecting means, one using an electron beam of an electron beam drawing apparatus, one using laser light from a laser writer, or another method can be used. In particular, it is desirable to use a device having high positional accuracy. This mark pattern 4a can be formed at the time of forming the common light-shielding pattern in the above-mentioned mask manufacturing, or it is also effective to form it at the time of manufacturing the mask blanks.

  The outside of the pellicle cover area in FIG. 1 indicates a peripheral area. In this peripheral area, a mark pattern 4b for detecting information of the mask PM1 is formed. The mark pattern 4b is used, for example, as an alignment mark or a calibration mark used in manufacturing a mask. The alignment mark is used to detect the position of the mask PM1 when the photomask PM1 is mounted on a predetermined device such as an inspection device or an exposure device, thereby performing alignment between the mask PM1 and the inspection device or the exposure device. Mark used for The calibration mark is a mark used when measuring a pattern misalignment, a pattern shape state, or a pattern transfer accuracy.

  The mark pattern 4b is formed by a light transmission pattern. That is, the mark pattern 4b is formed by removing a part of the light shielding pattern 2b and exposing a part of the transparent mask substrate 1 thereunder. Therefore, even when an exposure apparatus using a normal halogen lamp or the like is used for detecting the position of the mask PM1, a sufficient contrast of the light transmitted through the mark pattern 4b can be obtained. Can be improved. For this reason, the relative position between the mask PM1 and the exposure apparatus can be easily and accurately performed. According to the result of the study by the present inventors, it has become possible to perform the same alignment as the above-mentioned ordinary mask. The mark patterns 4a and 4b are not transferred onto the wafer.

  In the present embodiment, no resist film for pattern formation is formed in this peripheral region. If a resist film is formed in this peripheral region, the resist film peels off or is scraped off by a mechanical impact or the like when the mask PM1 is mounted on an inspection device, an exposure device, or the like, thereby generating foreign matter. However, according to the present embodiment, since the resist film does not exist in the peripheral region, peeling or scraping of the resist film can be prevented, and problems such as generation of foreign matter due to peeling of the resist film can be prevented. Was.

  In addition, the mask MP1 is set in the inspection device, the exposure device, or the like in a state where the mounting unit 5 of the inspection device, the exposure device, or the like is in direct contact with the light shielding pattern 2b of the mask PM1. An area 5A indicated by a thick frame in FIG. 1A indicates an area where the mounting unit 5 comes into contact. Even when the mask PM1 is mounted on an inspection device, an exposure device, or the like, no foreign matter is generated because the resist film is not formed on the light-shielding pattern 2b because the resist film is peeled off or scraped off. Further, since the metal constituting the light shielding pattern 2b is hard, there is no generation of foreign matter due to peeling or scraping of the metal. Note that the mounting section 5 has a vacuum suction mechanism as an example.

  Next, an example of a method for manufacturing the mask PM1 in FIG. 1 will be described with reference to FIGS.

  First, as shown in FIG. 3A, a mask substrate 1 made of, for example, a transparent synthetic quartz substrate having a thickness of about 6 mm is prepared. At this stage, the light-shielding patterns 2a and 2b have already been formed on the main surface of the mask substrate 1 in the same manner as a normal mask. That is, the light-shielding patterns 2a and 2b are formed by depositing a metal film having a high light-shielding property on the main surface of the mask substrate 1a by a sputtering method or the like and then patterning the metal film by a photolithography technique and an etching technique. I have. As a resist film used as an etching mask when forming the light shielding patterns 2a and 2b, a positive resist film is used. This is because the drawing area by the electron beam or the like can be reduced, and the drawing time can be shortened. After pattern processing of the light shielding patterns 2a and 2b, the positive resist film is removed.

Subsequently, as shown in FIG. 3B, a resist having a property of absorbing exposure light such as a KrF excimer laser, an ArF excimer laser, or an F ₂ laser beam is formed on the entire main surface of the mask substrate 1. The film 3 is applied by a spin coating method or the like. The resist film 3 is a resist film sensitive to an electron beam. Here, a novolak-based resist film was formed with a thickness of, for example, 150 nm.

  Subsequently, after the alignment is performed using the alignment mark, as shown in FIG. 3C, the resist film is formed by using the same electron beam writing method as the method of forming a desired pattern in a normal mask manufacturing process. 3 was formed. Here, countermeasures against electrification of an electron beam described later were taken. In addition, since the peripheral portion of the mask PM1 is a contact portion with the projection exposure apparatus, the resist film 3 is removed, thereby preventing the generation of foreign matter due to the peeling or scraping of the resist film 3 due to mechanical shock.

  The resist film 3 is mainly composed of, for example, a copolymer of α-methylstyrene and α-chloroacrylic acid, a novolak resin and quinonediazide, a novolak resin and polymethylpentene-1-sulfone, and chloromethylated polystyrene. Was used. A so-called chemically amplified resist in which an inhibitor and an acid generator are mixed with a phenol resin such as a polyvinyl phenol resin or a novolak resin can be used. The material of the resist film 3 used here has a light shielding property with respect to the light source of the projection exposure apparatus, and has a property of being sensitive to the light source of the pattern drawing apparatus, for example, an electron beam or light of 230 nm or more in the mask manufacturing process. The material is not limited to the above-mentioned material, and can be variously changed. Further, the film thickness is not limited to 150 nm, but may be a film thickness satisfying the above conditions.

FIG. 4 shows the spectral transmittance of a typical electron beam resist film. When a polyphenol-based or novolak-based resin is formed to a thickness of about 100 nm, the transmittance is substantially 0 at a wavelength of, for example, about 150 nm to 230 nm. For example, an ArF excimer laser beam having a wavelength of 193 nm, an F ₂ laser having a wavelength of 157 nm, or the like is used. Has a sufficient mask effect. Here, vacuum ultraviolet light having a wavelength of 200 nm or less is targeted, but is not limited thereto. It is necessary to use another material for a mask material such as a KrF excimer laser beam having a wavelength of 248 nm, or to add a light absorbing material or a light shielding material to the resist film. After the light-shielding pattern 3a formed of the resist film is formed, a so-called resist film hardening process is performed in which an additional heat treatment step is performed for the purpose of improving the resistance to exposure light irradiation, or in which strong ultraviolet light is previously irradiated. Is also effective.

  The resist film 3 is, for example, a negative resist film. This is because the mask PM1 can be created by Q-TAT (Quick Turn Around Time). That is, if the resist film is left outside the integrated circuit pattern region, it causes the generation of foreign matter as described above. Therefore, it is necessary to remove the resist film outside the resist film. Therefore, if a positive resist film is used here, most of the outer periphery of the integrated circuit pattern region must be drawn by an electron beam, which takes time. However, if a negative resist film is used, it is only necessary to draw a region having a relatively small area in the main surface of the mask substrate 1, so that the drawing area can be reduced and the drawing time can be shortened.

  Another example of the method for manufacturing the mask PM1 in FIG. 1 will be described with reference to FIGS. In the case of manufacturing the above-described normal mask, when a resist pattern for forming a light-shielding pattern is drawn by an electron beam drawing apparatus or the like, electrons generated at the time of drawing an electron beam are formed by grounding the metal film for forming the light-shielding pattern. Thus, no antistatic treatment is required. However, when manufacturing the mask PM1 of the present embodiment, when forming a light-shielding pattern on the resist film 3 using an electron beam lithography apparatus, since both the mask substrate 1 and the resist film 3 are insulators, the irradiated electrons May lose charge and become charged, adversely affecting the formation of the resist pattern (that is, the light-shielding pattern 3a). Therefore, for example, the mask PM1 is manufactured as follows.

  First, as shown in FIG. 5A, a transparent conductive film 7a is deposited on the main surface of the mask substrate 1. As the transparent conductive film 7a, for example, an ITO (indium-tin-oxide) film can be used. This transparent conductive film 7a does not need to be processed. Subsequently, the light-shielding patterns 2a and 2b are formed on the transparent conductive film 7a in the same manner as the above-described method of forming a light-shielding pattern of a normal mask. Subsequently, as shown in FIG. 5B, the resist film 3 is applied on the transparent conductive film 7a in the same manner as in the first embodiment. The transparent conductive film 7a is electrically connected to the ground EA. Thereafter, a predetermined pattern (light-shielding pattern 3a) is drawn on the resist film 3 using an electron beam drawing apparatus in the same manner as described above. At this time, the electrons irradiated on the mask substrate 1 can be released to the earth ER through the transparent conductive film 7a. Therefore, it is possible to suppress or prevent problems such as deterioration of the shape of the resist pattern and poor displacement caused by the electrification of the electrons. Becomes possible. Thereafter, a mask PM1 shown in FIG. 5C is manufactured through a developing process and a cleaning process.

  The following may be performed for the same purpose as described above. First, as shown in FIG. 6A, after preparing a mask substrate 1 on which light-shielding patterns 2a and 2b are already formed, as shown in FIG. 6B, the resist film 3 is formed on the main surface thereof. Apply. Subsequently, a water-soluble conductive organic film 7b is applied on the resist film 3. As the water-soluble conductive organic film 7b, for example, E-spacer (manufactured by Showa Denko KK), Aqua Save (manufactured by Mitsubishi Rayon), or the like was used. Thereafter, in a state where the water-soluble conductive organic film 7b and the ground EA were electrically connected, the electron beam drawing process for the above-described pattern drawing was performed. Thereafter, the water-soluble conductive organic film 7b was also removed during the development processing of the resist film 3. By the above method, electrification of the electron beam could be prevented, and defects such as abnormal pattern shape and pattern displacement could be prevented. Thus, the mask PM1 shown in FIG. 6C is manufactured.

In such a mask PM1, it is also effective to keep the pattern surface in an inert gas atmosphere such as nitrogen (N ₂ ) for the purpose of preventing the light-shielding pattern 3a made of a resist film from being oxidized. Further, the pattern drawing of the resist film for forming the light-shielding pattern 3a is not limited to the above-described electron beam drawing method, and it is also possible to draw a pattern using, for example, ultraviolet light having a wavelength of 230 nm or more (for example, i-ray (wavelength: 365 nm)). . The purpose of the present invention is to use a resist film directly as a mask (light-shielding pattern), and to provide a practical mask structure. Therefore, other materials may be used for the light shielding target wavelength, the resist material, and the mask substrate material.

  Using this mask PM1, a pattern was transferred onto a wafer 8 shown in FIG. 7 by a reduction projection exposure apparatus. FIG. 7A is a plan view of a main part of the wafer 8, and FIG. 7B is a cross-sectional view taken along line AA of FIG. The wafer 8 serving as a projection target substrate is made of, for example, silicon single crystal, and an insulating film 9a is deposited on a main surface thereof. A conductor film 10a is deposited on the entire surface of the insulating film 9a. Further, on the conductive film 10a, a normal positive resist film 11a having ArF sensitivity is deposited to a thickness of, for example, about 300 nm.

  As the projection light of the reduction projection exposure apparatus, for example, ArF excimer laser light having a wavelength of 193 nm was used, the numerical aperture NA of the projection lens was, for example, 0.68, and the coherency σ of the light source was, for example, 0.7. The alignment between the reduction projection exposure apparatus and the mask PM1 was performed by detecting the mark pattern 4b of the mask PM1. For the alignment here, for example, helium-neon (He-Ne) laser light having a wavelength of 633 nm was used. In this case, since the contrast of the light transmitted through the mark pattern 4b can be sufficiently obtained, the relative alignment between the mask PM1 and the exposure apparatus could be easily and accurately performed.

  Thereafter, the integrated circuit pattern on the mask PM1 was projected onto the main surface of the wafer 8 by a normal exposure method. Then, the resist pattern 11a1 shown in FIG. 8 was formed through ordinary heat treatment and development steps. 8A is a plan view of a main part of the wafer 8, and FIG. 8B is a cross-sectional view taken along line AA of FIG. The region RE indicates a region where the light-shielding pattern 3a formed of the resist film is transferred. Thereafter, by using the resist pattern 11a1 as an etching mask, the conductor film 10a was subjected to an etching process to form a conductor film pattern 10a1 as shown in FIG. 9A is a plan view of a main part of the wafer 8, and FIG. 9B is a cross-sectional view taken along line AA of FIG. As a result, almost the same pattern transfer characteristics as those at the time of exposure using the ordinary mask were obtained. For example, a 0.19 μm line and space could be formed with a depth of focus of 0.4 μm.

  FIG. 10 shows an example of a reduction projection exposure apparatus used in this exposure processing. Exposure light emitted from a light source 12a of the reduction projection exposure apparatus 12 irradiates the mask PM1 via a fly-eye lens 12b, an illumination shape adjustment aperture 12c, condenser lenses 12d1 and 12d2, and a mirror 12e. As the exposure light source, for example, KrF, ArF excimer laser, F2 laser light, or the like is used as described above. The mask PM1 is placed on the reduction projection exposure apparatus 12 with the main surface on which the light-shielding patterns 2a and 2b are formed facing downward (toward the wafer 8). Therefore, the exposure light is emitted from the back side of the mask PM1. Thereby, the mask pattern drawn on the mask PM1 is projected onto the wafer 8 as the sample substrate via the projection lens 12f. The pellicle PE is provided on the main surface of the mask PM1 in some cases. The mask PM1 is vacuum-sucked in the mounting portion 5 of the mask stage 12h controlled by the mask position control means 12g, is positioned by the position detection means 12i, and is positioned between the center thereof and the optical axis of the projection lens 12f. Has been made exactly.

  The wafer 8 is vacuum-sucked on the sample stage 12j. The sample stage 12j is mounted on a Z stage 12k movable in the optical axis direction of the projection lens 12f, that is, in the Z axis direction, and further mounted on an XY stage 12m. The Z stage 12k and the XY stage 12m are driven by the respective driving units 12p1 and 12p2 in response to a control command from the main control system 12n, and can be moved to desired exposure positions. The position is accurately monitored by the laser length measuring device 12r as the position of the mirror 12q fixed to the Z stage 12k. Further, a normal halogen lamp, for example, is used as the position detecting means 12i. That is, there is no need to use a special light source for the position detection means 12i (no need to introduce new or difficult techniques), and it is possible to use the same reduction projection exposure apparatus as before. Therefore, the use of the novel mask PM1 as in the present embodiment does not increase the product cost. Further, the main control system 12n is electrically connected to a network device, and can remotely monitor the state of the reduced projection exposure apparatus 12, for example. As the exposure method, for example, either a step-and-repeat exposure method or a step-and-scanning exposure method may be used.

  Next, a case where the technical idea of the present invention is applied to a manufacturing process of a semiconductor integrated circuit device having a twin-well type CMIS (Complimentary MIS) circuit will be described with reference to FIGS.

FIG. 11 is a cross-sectional view of a main part of the wafer 8 during the manufacturing process. The wafer 8 is made of, for example, a thin plate having a substantially circular flat shape. The semiconductor substrate 8s forming the wafer 8 is made of, for example, n ⁻ -type Si single crystal, and, for example, an n-well NWL and a p-well PWL are formed thereon. For example, phosphorus (P) or arsenic (As) is introduced into the n-well NWL. Further, for example, boron is introduced into the p-well PWL.

  On the main surface of the semiconductor substrate 8s, for example, a field insulating film 9b for isolation made of a silicon oxide film is formed by a LOCOS (Local Oxidization of Silicon) method or the like. Note that the separating portion may be a groove type. That is, the isolation portion may be formed by embedding an insulating film in a groove dug in the thickness direction of the semiconductor substrate 8s. In the active region surrounded by the field insulating film 9b, nMISQn and pMISQp are formed.

  The gate insulating films 9c of the nMISQn and the pMISQp are made of, for example, a silicon oxide film, and are formed by a thermal oxidation method or the like. The gate electrodes 10b of the nMISQn and the pMISQp are formed by depositing a conductor film for forming a gate made of, for example, low-resistance polysilicon on the main surface of the wafer 8 by a CVD method or the like, and then applying the film to the above-mentioned reduction projection exposure apparatus. It is formed by pattern processing using a photolithography technique using the photomask 12 and the photomask PM1 and a normal etching technique. Although not particularly limited, the gate length is, for example, about 0.18 μm.

  The semiconductor region 13 forming the source or drain of nMISQn is formed in a self-aligned manner with respect to the gate electrode 10b by introducing, for example, phosphorus or arsenic into the semiconductor substrate 8s by using the gate electrode 10b as a mask. Have been. The semiconductor region 14 forming the source or drain of the pMISQp is formed in a self-aligned manner with respect to the gate electrode 10b by introducing, for example, boron into the semiconductor substrate 8s by ion implantation or the like using the gate electrode 10b as a mask. Have been.

  However, the gate electrode 10b is not limited to being formed of, for example, a single film of low-resistance polysilicon, and can be variously changed. For example, the gate electrode 10b may be formed of tungsten silicide or cobalt silicide on the low-resistance polysilicon film. Or a so-called polycide structure provided with a simple silicide layer. For example, a metal antinode such as tungsten is provided on a low-resistance polysilicon film via a barrier conductor film such as titanium nitride or tungsten nitride. A so-called polymetal structure.

  First, as shown in FIG. 12, an interlayer insulating film 9d made of, for example, a silicon oxide film is deposited on such a semiconductor substrate 8s by a CVD method or the like, and then a polysilicon film is deposited on the upper surface thereof by a CVD method or the like. . Subsequently, after patterning the polysilicon film by a photolithography technique and a normal etching technique using the reduction projection exposure apparatus 12 and the mask PM1, an impurity is introduced into a predetermined region of the patterned polysilicon film. As a result, a wiring 10c and a resistor 10d made of a polysilicon film are formed.

  Thereafter, as shown in FIG. 13, an SOG (Spin On Glass) film 9e made of, for example, a silicon oxide film is deposited on the semiconductor substrate 8s by a coating method or the like, and then the semiconductor region 13 is formed on the interlayer insulating film 9d and the SOG film 9e. , 14 and a part of the wiring 10c are exposed by a photolithography technique using the reduced projection exposure apparatus 12 and the mask PM1 and a normal etching technique. Furthermore, after depositing a metal film made of, for example, aluminum (Al) or an Al alloy on the semiconductor substrate 8s by a sputtering method or the like, the metal film is formed by photolithography using the above-described reduced projection exposure apparatus 12 and the mask PM1. By patterning by a normal etching technique, a first layer wiring 10e is formed as shown in FIG. Thereafter, the second layer wiring and thereafter are formed in the same manner as the first layer wiring 10e, and the semiconductor integrated circuit device is manufactured. Here, in each of the photolithography steps, a mask pattern (a light-shielding pattern and a light-transmitting pattern) corresponding to a pattern to be formed is formed.

  Next, an application example of a method for manufacturing a semiconductor integrated circuit device using the mask PM1 of the present embodiment will be described. Here, a method of coping with the case where the pattern of the semiconductor integrated circuit device is partially corrected or changed will be described.

  During the development or manufacture of a semiconductor integrated circuit device, a part of the integrated circuit pattern may be modified or changed. In such a case, with a normal mask, a new mask substrate is prepared, a metal film is deposited thereon, and the metal film is patterned. For this reason, the work of the correction and the change is troublesome and time-consuming and time-consuming. Moreover, if there is a defect in the pattern of the manufactured mask, the mask cannot be used generally depending on the degree of the defect, so that the mask must be discarded, and a new A mask substrate must be prepared and the mask must be remanufactured from the beginning. This may result in wasteful and uneconomical work.

  On the other hand, when the mask PM1 of the present embodiment is used, the following measures can be taken. First, the light-shielding pattern 3a formed of the resist film on the mask PM1 in FIG. 1 is removed as shown in FIG. FIG. 15A is a plan view of the mask PM1 after removing the light-shielding pattern 3a, and FIG. 15B is a cross-sectional view taken along line AA of FIG. On the mask PM1, the light-shielding patterns 2a and 2b formed of metal are left, but the light-shielding pattern 3a in the region RE is removed, and the region RE is a light transmitting region.

  The light-shielding pattern 3a made of a resist film was peeled off with, for example, an n-methyl-2-pyrrolidone organic solvent. In addition, the light-shielding pattern 3a may be peeled off using a heated amine-based organic solvent or acetone. It is also possible to remove with a tetramethylammonium hydroxide (TMAH) aqueous solution, ozone sulfuric acid or a mixed solution of hydrogen peroxide and concentrated sulfuric acid. When a TMAH aqueous solution is used, its concentration is preferably about 5%, since the resist film (light-shielding pattern 3a) can be peeled off without attacking the metal (light-shielding patterns 2a and 2b).

  As another method for removing the resist film (light-shielding pattern 3a), an oxygen plasma ashing method can be used. This method is particularly effective when the resist film (light-shielding pattern 3a) on the mask PM1 is subjected to the above-described hardening process of the resist film. This is because the resist film (light-shielding pattern 3a) subjected to the hardening treatment is hardened and may not be sufficiently removed by the above-described chemical removal method.

  Further, the light shielding pattern 3a may be mechanically peeled off by peeling. That is, after the adhesive tape is attached to the surface of the mask PM1 on which the light-shielding pattern 3a is formed, the light-shielding pattern 3a is peeled off by peeling off the adhesive tape. In this case, almost no organic solvent is used, and there is no need to form a vacuum, so that the light-shielding pattern 3a can be peeled off relatively easily and in a short time.

  After the step of removing the resist film (light-shielding pattern 3a), a foreign substance on the surface of the mask PM1 is removed by performing a cleaning process. In this cleaning, for example, a combination of ozone sulfuric acid cleaning and brush cleaning processing is used. However, the method is not limited to this method as long as it has a high foreign matter removing ability and does not attack metal (light shielding patterns 2a and 2b). Can be changed.

  Thereafter, as shown in FIG. 16, a group of desired light-shielding patterns 3a having a different shape from the group of light-shielding patterns 3a shown in the area RE of FIG. The method of forming the light-shielding pattern 3a is the same as that described in the method of manufacturing the mask PM1, and a description thereof will be omitted. FIG. 17 shows a case where the pattern of the mask PM1 is transferred onto a wafer using the reduction projection exposure apparatus 12 or the like (see FIG. 10). FIG. 17A is a plan view of a main part of the wafer 8, and FIG. 17B is a cross-sectional view taken along line AA of FIG. In this manner, a group of conductor film patterns 10a1 having different shapes from those shown in FIG. 9 can be formed in the region RE.

  As described above, in the case of the mask PM1 of the present embodiment, since the light-shielding pattern 3a of a part of the mask PM1 is formed of the resist film, the pattern of the part (region RE) of the mask PM1 is modified or changed. In this case, the light-shielding pattern 3a may be removed and the light-shielding pattern 3a may be formed again in the same manner as in photolithography generally performed in the manufacturing process of a semiconductor integrated circuit device. This can be performed in a very short time. That is, the manufacturing period of the mask PM1 can be significantly reduced. Therefore, by using this mask PM1 for development and manufacture of a semiconductor integrated circuit device, it is possible to greatly reduce the time for development and manufacture of the semiconductor integrated circuit device.

  Further, when modifying or changing the pattern of the mask PM1, there is no need to prepare a new mask substrate 1 or to recreate it from the beginning. Moreover, if a defect exists in the light-shielding pattern 3a of the manufactured mask, the light-shielding pattern 3a may be removed again and the pattern may be processed again. Therefore, the number of steps for manufacturing the mask PM1 can be significantly reduced, and the material required for manufacturing the mask PM1 can be extremely reduced. Therefore, the manufacturing cost of the mask PM1 can be significantly reduced. Therefore, the cost of the semiconductor integrated circuit device can be significantly reduced by using the mask PM1 for the development and manufacture of the semiconductor integrated circuit device.

  18 to 20 show examples of semiconductor chips 8c1 to 8c3 of a semiconductor integrated circuit device which are effective by applying the technical idea of the present invention. The semiconductor chip is a small piece of semiconductor having a rectangular shape cut out of the wafer 8. Note that a region where a light-shielding pattern is formed of a resist film on the mask is hatched.

  On the semiconductor chip 8c1 in FIG. 18, circuit areas such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), DSP (Digital Signal Processor), microprocessor, MPEG (Moving Picture Experts Group), and Logic are arranged. The case where it has been illustrated is illustrated. Since the Logic is easily changed according to a customer's request or the like, a light-shielding pattern on a mask for forming a pattern of the Logic circuit region is formed by a resist film. That is, in the region RE of the mask PM1, a mask pattern for forming a pattern of a Logic circuit region is formed by a resist film (light shielding pattern 3a). A light-shielding pattern on the mask PM1 for forming a pattern in the other circuit area is formed of metal.

  The case where circuit areas such as a PCI control circuit, an I / F control circuit, an MCU, a program ROM, a data RAM (such as an SRAM), a custom logic circuit, and the like are arranged on the semiconductor chip 8c2 in FIG. 19 is illustrated. Among these, a light-shielding pattern on a mask for forming a pattern of the I / F control circuit, the program ROM, and the custom logic circuit is formed by a resist film. That is, three regions RE of the mask PM1 are provided, and a mask pattern for forming a pattern of the I / F control circuit, the program ROM, and the custom logic circuit is formed by a resist film (light shielding pattern 3a) in each of the three regions RE. A light-shielding pattern on the mask PM1 for forming a pattern in the other circuit area is formed of metal. In the I / F control circuit, for example, IEEE (Eye Triple E) 1394, USB (Universal Serial Bus), SCSI (Small Computer System Interface), AGP (Accelerated Graphics Port), Ether (Ether), Fiber-channel ( This is because the pattern shape is different when the interface standard is different, such as in a fiber channel. In the program ROM, it is necessary to rewrite the program as described later. Here, it can be exemplified that a light-shielding pattern on a mask is formed of a resist film for an eye (memory cell) portion of a ROM. Another reason is that a circuit pattern of a custom logic circuit may be changed according to a customer's request, as represented by a gate array or a standard cell, for example.

  20 illustrates a case where a CPU (Central Processing Unit), a memory, an application logic circuit, a custom I / O (Input / Output) circuit, an analog circuit, and a custom logic circuit are arranged on the semiconductor chip 8c3 in FIG. . Among them, a light-shielding pattern on a mask for forming a pattern of a custom I / O circuit and a custom logic circuit is formed by a resist film. That is, two regions RE of the mask PM1 are provided, and a mask pattern for forming a pattern of the custom I / O circuit and the pattern of the custom logic circuit is formed with a resist film (light shielding pattern 3a) in each of the regions. A light-shielding pattern on the mask PM1 for forming a pattern in the other circuit area is formed of metal. The custom I / O circuit is for the same reason as the above-mentioned I / F control circuit.

(Embodiment 2)
In the second embodiment, a modified example of the mask will be described. Otherwise, it is the same as the first embodiment.

  A mask PM2 shown in FIG. 21 is a mask in the case where the peripheral contour of the semiconductor chip becomes a light-shielding portion, and exemplifies a mask in the case of forming a line pattern on a wafer using a positive resist film. FIG. 21A is a plan view of the mask PM2, and FIG. 21B is a cross-sectional view taken along line AA of FIG.

  The light shielding patterns 2a and 3a in the integrated circuit pattern area on the mask PM2 are the same as those in the first embodiment. The pattern transferred onto the wafer using the mask PM2 is the same as that shown in FIGS. Here, a band-shaped light-shielding pattern 2c made of, for example, a metal is formed around the integrated circuit pattern area of the mask PM2 so as to surround it. The light-shielding film is removed from most of the outside to become a light transmitting region. The mark patterns 4a and 4b in the peripheral area of the mask PM2 are formed of a metal light shielding pattern. Therefore, since the contrast of the detection light can be sufficiently obtained, the detection sensitivity and the detection accuracy of the mark can be improved.

  The light-shielding patterns 2a and 2c and the mark patterns 4a and 4b are formed of, for example, the same metal material in the same pattern processing step. In forming the light shielding patterns 2a and 2c and the mark patterns 4a and 4b on the mask substrate 1, a negative resist film is used as an etching mask. This is because the mask PM2 can be created by Q-TAT. That is, if the resist film is left outside the integrated circuit pattern region, as described above, foreign matter is generated. Therefore, it is necessary to remove the resist film outside the resist film. When a film is formed, most of the inside and the outer periphery of the integrated circuit pattern region must be drawn by an electron beam, which takes time. However, if a negative resist film is used, the light-shielding patterns 2a, 2c and the mark patterns 4a, 4b having relatively small areas may be drawn in the main surface of the mask substrate 1, and the drawing area can be reduced. Drawing time can be shortened.

  The base of the pellicle attachment frame PEf of the pellicle PE is joined in a state of being in direct contact with the mask substrate 1. Therefore, peeling of the pellicle pasting frame PEf can be prevented as in the first embodiment. The mounting unit 5 of the exposure apparatus is also in direct contact with the mask substrate 1. Therefore, similarly to the first embodiment, it is possible to suppress or prevent the generation of foreign matter due to the resist peeling or the like.

  The method of changing the light shielding pattern 3a of the mask PM2 is the same as in the first embodiment. The following is a brief description with reference to FIGS. 22 and 23. 22A and 23A are plan views of the mask PM2, and FIG. 22B is a cross-sectional view taken along line AA of FIG.

  First, the light-shielding pattern 3a in the region RE of the mask PM2 shown in FIG. 21 is removed in the same manner as in the first embodiment as shown in FIG. The light-shielding pattern 2a and the light-shielding pattern 2c of the element transfer regions D1 to D3 are left because they are formed of metal. Subsequently, as shown in FIG. 23, a light-shielding pattern 3a having a shape different from that shown in FIG. 21 is formed of a resist film in the region RE of the mask PM2 in the same manner as in the first embodiment. Here, a negative resist was used as a resist film for forming the light-shielding pattern 3a as described above.

  According to the second embodiment, the same effects as those of the first embodiment can be obtained.

(Embodiment 3)
In the third embodiment, a modified example of the mask will be described. Otherwise, it is the same as the first embodiment.

  The mask PM3 illustrated in FIG. 24 illustrates a mask when a line pattern is formed on a wafer using a negative resist film. FIG. 24A is a plan view of the mask PM3, and FIG. 24B is a cross-sectional view taken along line AA of FIG.

  The main surface of the mask substrate 1 of the mask PM3 is almost entirely covered with a light-shielding film 2d formed of metal. The light shielding film 2d is made of the same material as the light shielding patterns 2a to 2c. In the element transfer regions D1 to D3 in the integrated circuit pattern region of the mask PM3, a part of the light shielding film 2d is removed to form the light transmission pattern 16a. In the region RE in the integrated circuit pattern region, the light-shielding film 2d is partially removed in a plane rectangular shape to form a light-transmitting opening region, and is instead covered with a light-shielding film 3b formed of a resist film. I have. Then, a part of the light shielding film 3b is removed to form the light transmission pattern 16b. A part of the outer periphery of the light shielding film 3b of the resist film is stacked on a part of the light shielding film 2d. The resist material of the light shielding film 3b is the same as the resist material of the light shielding pattern 3a described in the first embodiment. Here, a case where the light transmission patterns 16a and 16b are transferred as a line pattern on a wafer is illustrated. That is, the patterns of the light transmission patterns 16a and 16b are transferred onto the wafer. Further, the mark patterns 4a and 4b of the mask PM3 are formed by light transmission patterns as in the first embodiment. That is, it is formed by removing a part of the light shielding film 2d. Therefore, since the contrast of the detection light can be sufficiently obtained, the detection sensitivity and the detection accuracy of the mark can be improved.

  When processing the light shielding film 2d on the mask substrate 1 (that is, forming the light transmission pattern 16a, the light transmission opening area of the area RE, and the mark patterns 4a and 4b), a positive resist film is used. This is because the mask PM3 can be created by Q-TAT. That is, if a negative resist film is used here, most of the inside and outside of the integrated circuit pattern region must be drawn by an electron beam, which takes time.

  The base of the pellicle attachment frame PEf of the pellicle PE is joined in a state of being in direct contact with the light shielding film 2d formed of metal on the mask substrate 1. Therefore, peeling of the pellicle pasting frame PEf can be prevented as in the first and second embodiments. The mounting section 5 of the exposure apparatus is also in a state of being in direct contact with the light shielding film 2d formed of metal. Therefore, similarly to the first and second embodiments, it is possible to suppress or prevent the generation of foreign matter due to the resist peeling or the like.

  The method of changing the light transmission pattern 16b of the mask PM3 is the same as in the first and second embodiments. This will be briefly described with reference to FIGS. 25 and 26. 25A and FIG. 26A are plan views of the mask PM3, and FIG. 25B is a cross-sectional view taken along line AA of FIG.

  First, the light shielding film 3b formed of the resist film in the region RE of the mask PM3 shown in FIG. 24 is removed in the same manner as in the first and second embodiments as shown in FIG. The region 16c is exposed. At this time, since the metal light-shielding film 2d is left, the light transmission patterns 16a of the element transfer regions D1 to D3 remain as shown in FIG. The light transmission opening area 16c is opened, for example, in a plane rectangular shape, and the main surface of the mask substrate 1 is exposed from the area.

  Subsequently, a resist film for forming a light-shielding pattern is applied on the main surface of the mask PM3 (the surface on which the light-shielding film 2d is formed). As this resist film, a negative resist film was used. This is because the mask PM3 can be created by Q-TAT. In other words, if a positive resist film is used, electron beams must be drawn inside and outside the integrated circuit pattern area, which takes a long time. However, if a negative resist film is used, the drawing area can be reduced and the drawing time can be reduced. This is because it can be shortened. Subsequently, a pattern is drawn by irradiating an electron beam or the like to a portion of the resist film where the light-shielding region is to be formed, and development processing is performed. As shown in FIG. 26, the light-shielding film 3b and a part thereof are formed in the region RE. Is formed to form a light transmission pattern 16b.

  In the third embodiment, the same effects as those of the first and second embodiments can be obtained.

(Embodiment 4)
In the fourth embodiment, a case will be described in which the present invention is applied to a so-called overlay exposure technique in which one or a group of patterns on a wafer is formed by overlapping and exposing a plurality of masks. Otherwise, it is the same as the first to third embodiments.

  FIG. 27 shows an example of the first mask PM41 used in the fourth embodiment. In the integrated circuit pattern area of the mask PM41, for example, a planar inverted L-shaped light transmission opening area 16d is formed. A metal light-shielding pattern 2a for transferring an integrated circuit pattern onto a wafer is formed in the light-transmitting opening region 16d. Here, a mask PM41 for transferring a line pattern onto a wafer is illustrated. Most of the periphery of the light transmission opening region 16d is covered with a metal light shielding film 2e over the outer periphery of the mask substrate 1. The region RE is also covered with the light shielding film 2e. In the first mask PM41, the mark pattern 4b and the pellicle are the same as in the third embodiment.

  In the semiconductor integrated circuit device, the mask PM41 is used as a mask for transferring a pattern of a circuit (see FIGS. 18 to 20) composed of a fixed pattern group in which pattern correction or change is basically not performed. Here, the light-shielding pattern 2a and the light-shielding film 2e are made of the same material, but here, the material of the light-shielding pattern 2a and the light-shielding film 2e may not be made of a material other than chromium or chromium oxide. This is because the mask PM41 is used in the same manner as a normal mask. That is, since the pattern is not changed, the light-shielding pattern 2a and the light-shielding film 2e only need to have the resistance required for a normal mask. Of course, the light shielding pattern of the mask PM41 may be formed by a resist film.

  FIG. 28 shows an example of the second mask PM42 used in the fourth embodiment. In the mask PM42, for example, a light transmission opening area 16e having a rectangular shape in a plane is formed in the area RE of the integrated circuit pattern area. The light-shielding pattern 3a of the resist film for transferring the integrated circuit pattern onto the wafer is formed in the light transmission opening area 16e. Here, a mask PM42 for transferring a line pattern onto a wafer is illustrated. Most of the periphery of the light transmission opening region 16e is covered with a metal light shielding film 2f over the outer periphery of the mask substrate 1. The light-shielding film 2f is made of the same material as the light-shielding pattern 2a described in the first embodiment and the like. In the second mask PM41, the mark pattern 4b and the pellicle are the same as in the third embodiment.

  The mask PM42 is used as a mask for transferring a pattern of a circuit (see FIGS. 18 to 20) composed of a pattern group in which a pattern is corrected or changed in the semiconductor integrated circuit device. The manner of correcting and changing the light-shielding pattern 3a in the second mask PM42 is the same as in the first to third embodiments. This will be briefly described with reference to FIGS. 29 and 30. 29A and 30A are plan views of the mask PM42, and FIG. 29B is a cross-sectional view taken along line AA of FIG.

  First, the light-shielding pattern 3a formed by the resist film in the region RE of the mask PM42 shown in FIG. 28 is removed in the same manner as in the first to third embodiments as shown in FIG. At this time, the metal light shielding film 2f is left. Subsequently, a resist film for forming a light-shielding pattern is applied on the main surface (the surface on which the light-shielding film 2f is formed) of the mask PM42. As this resist film, a negative resist film was used. This is because the mask PM1 can be created by Q-TAT. That is, if the resist film is left outside the integrated circuit pattern region, it causes the generation of foreign matter as described above. Therefore, it is necessary to remove the resist film outside the resist film. Therefore, if a positive resist film is used here, most of the outer periphery of the integrated circuit pattern region must be drawn by an electron beam, which takes time. However, if a negative resist film is used, only the area of the light-shielding pattern 3a having a relatively small area needs to be drawn in the main surface of the mask substrate 1, so that the drawing area can be reduced and the drawing time can be shortened. Subsequently, a pattern is drawn by irradiating an electron beam or the like on a portion of the resist film where a light-shielding region is to be formed, and is subjected to a development process, so that the light-shielding pattern shown in FIG. A light-shielding pattern 3a having a shape different from that of 3a is formed. Of course, even if all the light-shielding portions (light-shielding patterns and light-shielding regions) of the masks PM41 and PM42 are made of metal such as chrome, only the change of the mask PM42 is sufficient, so that Q-TAT can be achieved in mask manufacturing. It becomes possible.

  A method of transferring a pattern onto a wafer using such first and second masks PM41 and PM42 will be described with reference to FIG. 7 and the like, for example, as follows.

  First, as shown in FIG. 7, after a positive resist film 11a is applied on the conductor film 10a formed on the wafer 8, the first mask PM41 shown in FIG. The mask pattern is transferred by the reduction projection exposure apparatus 12 shown in FIG. At this time, since the exposure light is transmitted through the light transmission opening area 16d of the first mask PM41, the area corresponding to the light transmission opening area 16d in the resist film 11a is exposed. However, since the region RE of the first mask PM41 is covered with the light shielding film 2e, the region corresponding to the region RE in the resist film 11a is not exposed.

  Subsequently, without removing the resist film 11a, the mask pattern of the second mask PM42 shown in FIG. 28 is transferred to the resist film 11a by the reduction projection exposure apparatus 12 shown in FIG. At this time, only the region corresponding to the region RE of the second mask PM42 in the resist film 11a is exposed, contrary to the first mask PM41.

  Thereafter, a resist pattern reflecting the mask patterns of the first and second masks PM41 and PM42 is formed on the conductor film 10a by performing development processing or the like on the resist film 11a. Thereafter, the conductor film 10a is subjected to an etching process using the resist pattern as an etching mask to form a conductor film pattern. If any modification or change occurs in the region RE of the second mask PM42 during the development or manufacturing process of the semiconductor integrated circuit device, the light-shielding pattern 3a on the second mask PM42 may be re-created as described above.

  According to the fourth embodiment, the following effects can be obtained in addition to the effects obtained in the first to third embodiments.

  That is, in the case where the light-shielding pattern 2a with little correction or change and the light-shielding pattern 3a with correction or change are formed on the same mask, when the pattern is corrected or changed, a fine pattern without correction or change is formed. Since the light-shielding pattern 2a is also subjected to the stripping process and the cleaning process of the resist film (light-shielding pattern 3a), the light-shielding pattern 2a may be deteriorated or peeled off. On the other hand, in the fourth embodiment, the mask is divided into a first mask PM41 for transferring a pattern with little correction or change and a second mask PM42 for transferring a pattern with correction or change. Accordingly, when the pattern is corrected or changed, the fine light-shielding pattern 2a having no correction or change need not be subjected to the resist film peeling process or the cleaning process, so that the light-shielding pattern 2a is deteriorated or peeled. Nothing to do. In addition, since the second mask PM42 does not have the fine light-shielding pattern 2a, the light-shielding pattern 3a can be peeled or cleaned without concern for deterioration or peeling of the light-shielding pattern 2a. Therefore, the life and reliability of the mask can be improved.

(Embodiment 5)
Embodiment 5 describes a modification of the mask, and describes a case where the present invention is applied to a translucent phase shift mask (the halftone mask).

  FIG. 31 shows a mask PM5 of the fifth embodiment. A halftone pattern 3c for transferring the integrated circuit pattern is formed in a part of the light transmitting region of the integrated circuit pattern region of the mask PM5. The halftone pattern 3c is formed of the resist film 3 on which the light-shielding pattern 3a described in the first embodiment and the like is formed. However, the halftone pattern 3c is translucent to the exposure light and the phase of the exposure light is inverted. It is adjusted to the film thickness to be made. The halftone pattern 3c is formed on the same surface of the mask substrate 1 as the light-shielding patterns 2a and 2b.

  FIG. 31B shows a state where the phase of the exposure light irradiated from the back surface side of the mask PM5 of the fifth embodiment is inverted. The phase of the exposure light that has passed through the halftone pattern 3c is inverted by 180 degrees with respect to the exposure light that has passed through the transparent portion (light transmission region). That is, the phases of the exposure light are reversed. The transmittance of the halftone pattern 3c is a light intensity of about 2 to 10% of the exposure light before transmitting the halftone pattern 3c. Therefore, the halftone pattern 3c substantially acts as a light-shielding portion, but has an effect of sharpening the boundary of the transferred pattern. The pattern processing method and the pattern changing method of the halftone pattern 3c are the same as the pattern processing method and the changing method of the light shielding pattern 3a of the first to fourth embodiments.

  When an ArF excimer laser is used as an exposure light source, absorption in a resist film serving as a mask is large. Therefore, in order to simultaneously realize the transmittance of about 2 to 10% and the phase inversion, it is necessary to form a halftone pattern 3c. Adjustment is required for the resist film. On the other hand, when F2 laser light having a wavelength of 157 nm is used as an exposure light source, absorption in the resist film is reduced, which is advantageous for simultaneously realizing the transmittance of about 2 to 10% and the phase inversion.

  Also in the fifth embodiment, the same effects as those in the first to fourth embodiments can be obtained.

(Embodiment 6)
The sixth embodiment describes a modification of the mask of the fifth embodiment.

  In the fifth embodiment, since the phase difference is set according to the thickness of the halftone pattern, the thickness needs to be within a predetermined range, and the intensity of light transmitted through the halftone pattern of the resist film is required. Setting may be difficult.

  Therefore, in the sixth embodiment, the phase difference of the light is not set only by the thickness of the halftone pattern of the resist film. , The thickness of the mask substrate in the groove forming portion) to adjust the phase difference. This makes it possible to obtain the following effects in addition to the effects obtained in the fifth embodiment. That is, it is possible to easily set the intensity of light transmitted through the halftone pattern. Further, it is possible to increase the range of selection of the material for forming the halftone pattern.

  FIG. 32A shows a specific example of the mask PM6 of the sixth embodiment. In this mask PM6, the halftone pattern 3d of the resist film is made of the same material as the halftone pattern 3c of the fifth embodiment, but the thickness thereof is formed of a semitransparent film thinner than the halftone pattern 3c. The phase inversion of the transmitted light is realized by the thickness of the halftone pattern 3d and the thickness of the mask substrate 1a at the portion of the groove 18 formed in the mask substrate 1a.

  The halftone pattern 3d is formed of, for example, a novolak resin having a thickness of about 50 nm. As a result, the transmittance of the halftone pattern 3d was 5%. However, the transmittance is not limited to 5% and can be variously changed. For example, the transmittance can be selected according to the purpose within a range of about 2 to 20%. The phase inversion in this case was about 90 degrees. For this reason, a groove 18 having a depth of about 90 nm is dug in the mask substrate 1 so that a total of about 180 degrees of phase inversion can be obtained in the exposure light transmitted through the mask PM6. The film thickness of the halftone pattern 3d is not limited to the above-described one, but can be variously changed, and may be adjusted so that the phase is inverted according to the refractive index of the material, the exposure wavelength, and the like.

  The method of forming such a mask PM6 is, for example, as follows. First, light-shielding patterns 2a and 2b and a halftone pattern 3d are formed on a mask substrate 1 as shown in FIG. Subsequently, using the light-shielding patterns 2a and 2b and the halftone pattern 3d as an etching mask, the mask substrate 1 exposed therefrom is selectively etched away by the above-described depth. Thus, the groove 18 shown in FIG. 32A is formed in a self-aligned manner with respect to the halftone pattern 17b. Thus, in the sixth embodiment, the mask PM6 having the halftone pattern 3d having a transmittance of, for example, 5% could be manufactured. In the example of FIG. 32A, in order to simplify the manufacturing process of the mask, the mask substrate 1 in the region of the mark pattern 4b is also etched away and dug in forming the groove 18; The mask substrate 1 may not be removed by etching. Further, in the case where the halftone pattern 3d is corrected or changed in the mask PM6, it is performed before the groove 18 is formed.

  Also in the sixth embodiment, the same effects as those in the first to fifth embodiments can be obtained.

(Embodiment 7)
The seventh embodiment describes a modified example of the masks of the fifth and sixth embodiments.

  In the seventh embodiment, in order to solve the problem described in the sixth embodiment, instead of adjusting the phase of the exposure light only by the halftone pattern, the phase of the exposure light It is adjusted by providing another film that overlaps. As a result, according to the seventh embodiment, similarly to the sixth embodiment, it is possible to easily set the intensity of light transmitted through the halftone pattern. Further, it is possible to increase the range of selection of the material for forming the halftone pattern.

  FIG. 33A shows a specific example of the mask PM7 in the seventh embodiment. In the mask PM7, a transparent phase adjusting film 19 made of, for example, a silicon oxide film is provided between the mask substrate 1 and the halftone pattern 3d of the same resist film as in the sixth embodiment, and the halftone pattern 3d The phase inversion is realized by adjusting the film thickness of the phase adjustment film 19 and the phase adjustment film 19.

  The method of forming such a mask PM7 is, for example, as follows. First, as shown in FIG. 33B, a phase adjusting film 19 made of, for example, a silicon oxide film is formed on the main surface of the mask substrate 1 by a sputtering method, a CVD (Chemical Vapor Deposition) method, a coating method, or the like. Subsequently, light-shielding patterns 2a and 2b and a halftone pattern 3d are formed thereon similarly to the fifth and sixth embodiments. Thereafter, as described above, only the halftone pattern 3d has a phase reversal of about 90 degrees, so that the phase adjustment film 19 under the halftone pattern 3d and the light-shielding patterns 2a and 2b is used as an etching mask, for example, by 90 nm. Digging to the extent, a total phase inversion of about 180 degrees was obtained. At this time, the mask substrate 1 may be used as an etching stopper. Thus, the mask PM7 shown in FIG. 33A is manufactured. Also in the seventh embodiment, a halftone mask PM7 having a transmittance of, for example, 5% could be manufactured. The film thickness of the halftone pattern 3d is not limited to this as in the sixth embodiment. Also, in the seventh embodiment, the phase adjustment film 19 in the mark pattern 4b region is removed by etching when the phase adjustment film 19 is patterned in order to simplify the manufacturing process of the mask. It is also possible not to remove the 19 parts by etching. Further, in this case, it is preferable to correct or change the halftone pattern 3d of the mask PM7 before performing the etching process on the phase adjustment film 19.

  Also in the seventh embodiment, the same effects as in the first to sixth embodiments can be obtained.

(Embodiment 8)
The eighth embodiment describes a modification of the mask and the method of manufacturing the mask according to the fifth to seventh embodiments.

  An example of a method for manufacturing a mask according to the eighth embodiment will be described with reference to FIG.

  First, as shown in FIG. 34A, the light-shielding patterns 2a and 2b, the mark pattern 4b, and the like are formed on the main surface of the mask substrate 1 in the same manner as in the first to seventh embodiments. Subsequently, as shown in FIG. 34B, a resist film 20 transparent to exposure light is applied on the main surface of the mask substrate 1 so as to cover the light-shielding patterns 2a and 2b and the main surface of the mask substrate 1. Further, a resist film 3 having a light-shielding property as used in the fifth embodiment was formed as a thin film thereon to be translucent. Here, as the transparent resist film 20, for example, PGMA24 (polyglycidyl methacrylate) showing a positive type is used. Further, the light-shielding resist film 3 was formed of, for example, a novolak resin having a thickness of about 50 nm and showing a negative type. Thereafter, a desired integrated circuit pattern was drawn on the resist film 3 using an electron beam or the like. Again, the antistatic treatment was performed. Thereafter, a normal development process is performed to develop the resist film 3, thereby forming a halftone pattern 3e formed of the resist film 3 as shown in FIG.

  Next, a normal exposure process is performed on the main surface of the mask substrate 1 to expose a portion of the resist film 20 that is exposed from the halftone pattern 3e having a light-shielding property, and then a development process is performed. As shown in (1), a phase adjustment film composed of the resist film 20 is formed in a self-alignment manner with the halftone pattern 3e. Thus, a mask PM8 was manufactured.

  In the mask PM8, a resist film 20 (phase adjustment film) is provided only under the halftone pattern 3e. The phase adjustment of the exposure light transmitted through the mask PM8 is adjusted by the film thickness of the halftone pattern 3e and the resist film 20 (phase adjustment film). As a result, the light transmitted through the laminated pattern region of the halftone pattern 3e and the resist film 20 (phase adjustment film) and the light transmitted only through the mask substrate 1 could be inverted in phase by 180 degrees. The transmittance of the laminated pattern area was about 5%. That is, similarly to the sixth and seventh embodiments, the mask PM8 having the halftone pattern 3e having a transmittance of, for example, 5% could be manufactured. In this case, the correction or change of the halftone pattern 3e may be performed after the resist film 20 is patterned. That is, when the pattern is changed, both the halftone pattern 3e and the resist film 20 may be removed, and the application of the resist film 20 may be performed again.

  Also in the eighth embodiment, the same effects as in the first to seventh embodiments can be obtained.

(Embodiment 9)
The ninth embodiment describes a modified example of the mask, and describes a combination example of a normal halftone mask and a halftone mask using a resist film as in the fifth to eighth embodiments. Is what you do.

  FIG. 35 shows a specific example of the mask PM9 of the ninth embodiment. The mask PM9 exemplifies a mask for transferring a line pattern such as a wiring to a wafer in a halftone pattern. Here, in the integrated circuit pattern region on the main surface of the mask substrate 1, a normal halftone pattern 21a made of, for example, MoSiOx or MoSiON and a halftone pattern 3c made of the resist film described in the fifth to eighth embodiments are used. Are patterned. The film thickness of the halftone pattern 3c was set to a film thickness necessary for phase inversion and a film thickness satisfying a desired light shielding property as in the case of the fifth to eighth embodiments. Therefore, the phase difference of the transmitted light is not limited to 180 degrees, but can be variously selected, such as 540 degrees and 900 degrees.

  FIG. 35B shows a state of the phase inversion of the exposure light irradiated from the back side of the mask PM9. The phase of the exposure light that has passed through the halftone patterns 3c and 21a is inverted by 180 degrees with respect to the exposure light that has passed through the transparent portion (light transmission region). That is, the phases of the exposure light are reversed.

  Next, an example of a method for manufacturing the mask PM9 will be described with reference to FIG.

  First, as shown in FIG. 36A, a halftone film 21 made of, for example, MoSiOx or MoSiON is deposited on the main surface of the mask substrate 1 by, for example, a sputtering method or a CVD method. A light shielding film 2 made of a metal for a light shielding film is deposited by a sputtering method or the like. Subsequently, the light-shielding film 2 and the halftone film 21 are patterned by a normal photolithography technique and an etching technique, so that the halftone pattern 21a, the light-shielding pattern 2b, and the mark pattern 4b are formed as shown in FIG. To form Thereafter, as shown in FIG. 36C, a resist film 22 is formed so as to cover the light-shielding pattern 2b other than the formation region of the halftone pattern 21a, and the light-shielding film 2 exposed therefrom is used as an etching mask. By removing, the halftone pattern 21a is exposed as shown in FIG. Thereafter, as shown in FIG. 36E, a resist film 3 for a light-shielding mask is applied, and then a predetermined position is irradiated with an electron beam or the like, so that a half of the resist film 3 shown in FIG. The tone pattern 3c is formed. The method of correcting and changing the halftone pattern 3c is the same as in the first embodiment.

  Also in the ninth embodiment, the same effects as in the first to seventh embodiments can be obtained.

(Embodiment 10)
The tenth embodiment describes a modification of the mask, and describes a combination example of the Levenson-type phase shift mask and the light-shielding pattern mask using the resist film of the first to fourth embodiments. Things.

  FIG. 37 shows a specific example of the mask PM10 of the tenth embodiment. Here, a mask PM10 for transferring a line pattern such as a wiring on a wafer is illustrated. In the integrated circuit pattern region on the main surface of the mask PM10, a Levenson-type phase shift pattern region (left side in FIG. 37A) and a light-shielding pattern 3a of the resist film described in the first to fourth embodiments and the like are formed. An area (the right side in FIG. 37A) is arranged.

  In the Levenson-type phase shift pattern region, a plurality of metal light-shielding patterns 2a, a light transmission pattern 16f adjacent to the light-shielding pattern 2a, and a phase shifter 22a disposed on one of the adjacent light transmission patterns 16f are provided. Is arranged. The phase shifter 22a is, for example, a groove-type shifter. As the groove-type shifter, a structure in which a part in the width direction of the groove is overhanged below the light-shielding pattern 2a may be employed. Thereby, the pattern transfer accuracy can be improved. FIG. 37 (b) shows how the phase of the exposure light irradiated from the back side of the mask PM10 is inverted. The phase of the exposure light that has passed through the phase shifter 22a is inverted by 180 degrees with respect to the exposure light that has passed through the light transmission pattern 16f without the phase shifter 22a. That is, the phases of the exposure light are reversed. On the other hand, the light-shielding pattern 3a is the same as that described in the first embodiment. Therefore, the light-shielding pattern 3a can be easily modified or changed.

  Such a mask PM10 is preferably applied to a semiconductor integrated circuit device having a memory such as a DRAM. 2. Description of the Related Art In a semiconductor integrated circuit device having a memory such as a DRAM, miniaturization of elements and wiring in a memory cell region has been advanced. For this reason, when forming a word line, a data line, or a hole pattern, the pattern may not be transferred unless a Levenson-type phase shift mask is used. On the other hand, the Levenson-type phase shift mask may not be used in the peripheral circuit area other than the memory cell area and other logic circuit areas, but the patterns of the peripheral circuit and the logic circuit are variously changed according to customer requirements and product specifications. In some cases. The mask PM10 can cope with both requirements. That is, a fine element or wiring pattern can be transferred on the memory cell area side, and circuits other than the memory cell area can flexibly face various pattern shape changes in a short time. Since the correction and the change can be performed from the stage after forming the groove for the phase shifter, the mask manufacturing time can be shortened. Otherwise, in Embodiment 10, the same effects as in Embodiments 1 to 9 can be obtained.

(Embodiment 11)
The eleventh embodiment describes a modified example of the mask, and includes the ordinary Levenson-type phase shift mask and the Levenson-type phase shift mask constituted by the light-shielding pattern of the resist film of the first to fourth embodiments. The following describes an example of a combination with.

  FIG. 38 shows a specific example of the mask PM11 according to the eleventh embodiment, and illustrates the mask PM11 for transferring a line pattern such as wiring on a wafer. In the integrated circuit pattern region on the main surface of the mask PM11, a Levenson-type phase shift pattern region (left side in FIG. 38) and the Levenson-type light-shielding pattern 3a of the resist film described in the first to fourth embodiments and the like are used. A phase shift pattern area (right side in FIG. 38) is arranged.

  The phase shift pattern region of the Levenson on the left side of FIG. 38 is the same as that of the tenth embodiment, and a description thereof will be omitted. On the right side of FIG. 38, a phase shifter 22b formed of a photosensitive transparent film such as a photosensitive SOG film is patterned. A light-shielding pattern 3a of a resist film is formed so as to cover the side surface and the vicinity of the side surface of the phase shifter 22b. The light shielding pattern 3a forms a light transmitting pattern 16g that exposes a part of the main surface of the mask substrate 1 and a light transmitting pattern 16h that exposes a part of the upper surface of the phase shifter 22b. The phases of the lights transmitted through the adjacent light transmission patterns 16g and 16h are inverted by 180 degrees.

  In order to manufacture such a mask PM11, first, light-shielding patterns 2a and 2b made of metal are formed on the main surface of the mask substrate 1 in the same manner as a normal mask, and then a predetermined portion of the main surface of the mask substrate 1 is formed. A phase shifter 22a is formed by digging a groove. Subsequently, a phase shifter 22b is formed by applying a photosensitive SOG film or the like on the main surface of the mask substrate 1 and patterning it by photolithography. After that, a resist film for forming the light-shielding film is applied on the main surface of the mask substrate 1, and the light-shielding pattern 3a is formed by patterning the resist film by photolithography.

  In the eleventh embodiment, the same effects as those in the first to ninth embodiments can be obtained.

(Embodiment 12)
The twelfth embodiment describes a modification of the mask, and describes an example of a combination of a normal mask and the Levenson-type phase shift mask constituted by the light-shielding pattern of the resist film of the eleventh embodiment. Things.

  FIG. 39 shows a specific example of the mask PM12 of the eleventh embodiment, and illustrates the mask PM12 for transferring a line pattern such as a wiring on a wafer. In the integrated circuit pattern area on the main surface of the mask PM12, a pattern area of a normal mask (the left side in FIG. 39) and the Levenson-type phase shift pattern composed of the light-shielding pattern 3a of the resist film described in the eleventh embodiment are used. An area (right side in FIG. 39) is arranged. The method of manufacturing the mask PM12 is almost the same as that of the eleventh embodiment, except that there is no step of forming the groove type phase shifter 22a.

  Also in the twelfth embodiment, the same effects as in the first to ninth embodiments can be obtained.

(Embodiment 13)
In the thirteenth embodiment, a modification of the mask will be described.

  As described above, in the mask of the present embodiment, since the pattern on the mask is removed, a certain degree of resistance is required for the light-shielding pattern formed of metal. Therefore, in the thirteenth embodiment, a protective film is formed on the surface of the light-shielding pattern formed of metal.

  FIG. 40A shows a specific example of a cross section of the mask PM13 of the thirteenth embodiment. A thin protective film 23 made of, for example, silicon oxide or the like is provided on the surfaces of the metal light-shielding patterns 2a and 2b formed on the mask substrate 1 (that is, the upper surface and side surfaces of the light-shielding patterns 2a and 2b) and the main surface of the mask substrate 1. Is attached. Accordingly, the light-shielding patterns 2a and 2b can be protected when the resist film (light-shielding pattern 3a) of the mask PM13 is peeled off and washed. Therefore, the resistance of the light-shielding patterns 2a and 2b can be improved. In particular, when the light-shielding pattern 2a for transferring a fine integrated circuit pattern is formed, this structure in which the protective film 23 covers the entire surface of the light-shielding pattern 2a is used to improve the peeling resistance of the light-shielding pattern 2a. preferable. The protection film 23 is formed by, for example, the CVD method or the sputtering after pattern processing of the light shielding patterns 2a and 2b. The light-shielding pattern 3a of the resist film is pattern-formed on the protective film 23. FIG. 40B shows a state in which the light shielding pattern 3a has been removed. In order to form a new light-shielding pattern, a resist film for forming a light-shielding pattern may be applied in the same manner as in the first embodiment, and the pattern may be drawn using an electron beam or the like. This structure can be applied to any of the masks according to the first to twelfth embodiments.

  In the thirteenth embodiment, in addition to the effects obtained in the first to twelfth embodiments, it is possible to obtain an effect that the life of the mask PM13 can be improved.

(Embodiment 14)
The fourteenth embodiment describes a modification of the thirteenth embodiment.

  FIG. 41A shows a specific example of a cross section of the mask PM14 of the fourteenth embodiment. In the fourteenth embodiment, the case where the protective film 23 is applied only to the upper surfaces of the light shielding patterns 2a and 2b is illustrated. In this case, the protective film 23 is formed by depositing a light-shielding film on the mask substrate 1 by a sputtering method, and then depositing the protective film 23 thereon by a CVD method or a sputtering method, and further patterning the light-shielding film. Are formed at the same time when the light shielding patterns 2a and 2b are formed. Otherwise, the configuration is the same as that of the thirteenth embodiment. FIG. 41B shows a state in which the light shielding pattern 3a has been removed. Also in this case, the durability of the light shielding patterns 2a and 2b can be improved, and the life of the mask PM14 can be improved.

(Embodiment 15)
The fifteenth embodiment describes a modification of the mask.

  According to the study of the present inventors, after forming a light-shielding pattern of a resist film for forming the integrated circuit pattern and the mark pattern on the main surface of the mask substrate, the light-shielding pattern covering the light-shielding pattern is formed on the main surface. It has been found that forming a protective film is also effective. Thereby, the mechanical strength of the light shielding pattern formed by the resist film can be improved. Further, by blocking oxygen with the protective film, it is possible to prevent a change in film quality of the light-shielding pattern formed by the resist film.

  FIG. 42 shows a specific example thereof. A protective film 24 made of, for example, a silicon oxide film or a coated silicon compound is formed on the entire main surface of the mask substrate 1 constituting the mask PM15. When the protective film 24 is a silicon oxide film or the like, it may be formed by, for example, a sputtering method or a CVD method. When the protective film 24 is made of a coating silicon compound, it is preferable to perform a heat treatment at about 100 to 200 ° after the coating.

  Further, in mask PM15 of the fifteenth embodiment, protective film 24 is deposited on the entire main surface of mask substrate 1 so as to cover light-shielding patterns 2a, 2b, 3a. That is, when the mask PM15 is mounted on an inspection apparatus, an exposure apparatus, or the like, the protective film 24 of the mask PM15 comes into contact with a mounting portion of the inspection apparatus, the exposure apparatus, or the like. Therefore, as in the first to fourteenth embodiments, the mounting portion 5 of the inspection device or the exposure device does not directly contact the pattern of the resist film on the mask substrate 1 (the light-shielding pattern 3a or the like). It is possible to prevent the resist film from being peeled off or scraped, and to prevent the generation of foreign substances due to the peeling or the scraping. Note that this structure can be applied to the photomasks of Embodiments 1 to 14.

(Embodiment 16)
In the sixteenth embodiment, a problem that occurs when a metal light-shielding pattern and a resist film light-shielding pattern are formed on a mask and a means for solving the problem will be described.

  FIG. 43A is a plan view of a main part of a mask for transferring a plurality of line patterns adjacent to each other on a wafer, and shows a light shielding pattern 2a of a metal for transferring the line pattern and a light shielding pattern 3a of a resist film. The connection part is shown. FIG. 43B is a cross-sectional view taken along line AA of FIG.

  Here, a case where the light-shielding patterns 2a and 3a overlap without displacement is illustrated. However, since the light-shielding patterns 2a and 3a are separately patterned, they cannot always be arranged with good alignment. As shown in FIG. 44A, the light-shielding patterns 2a and 3a are shifted in the width direction of the pattern. In some cases. When the pattern is shifted in this way, there arises a problem that the adjacent pattern interval d1 cannot be secured. Further, as shown in FIG. 44B, even in the overlapping portion of the isolated light shielding patterns 2a and 3a, there is a case where the respective patterns are largely shifted in the width direction and a sufficient connection state cannot be secured. .

  Therefore, as shown in FIG. 45, in the mask PM16 of the sixteenth embodiment, even if the metal light-shielding pattern 2a and the resist light-shielding pattern 3a should be connected to each other, the predetermined condition is satisfied. In this case, the light-shielding pattern 2a of the metal and the light-shielding pattern 3a of the resist film are arranged separately.

  FIG. 46A shows a case in which the positional relationship between the metal light-shielding pattern 2a and the light-shielding pattern 3a of the resist film is shifted in the pattern width direction in the mask PM16 of the sixteenth embodiment. I have. FIG. 46B is a plan view showing a case where the conductive film pattern 10a1 on the wafer 8 is formed using the mask PM16. FIG. 46C is a sectional view taken along line AA of FIG. By the way, since the conductor film patterns 10a1 and 10a1 must be originally connected, as shown in FIGS. 47A to 47C, the conductor film patterns 10a1 and 10a1 are connected by the upper conductor film pattern 10f. I made it. FIG. 47A shows a case where the relative positional relationship between the conductor film patterns 10a1 and 10a1 is good, FIG. 47B shows a case where the conductor film patterns 10a1 and 10a1 are deviated, and FIG. 47C shows AA of FIGS. FIG. 3 shows a sectional view of the line. Each of the conductive film patterns 10a1 and 10a1 is electrically connected to the conductive film pattern 10f through a through hole 25 formed in the insulating film 9b and is electrically connected to each other.

(Embodiment 17)
The seventeenth embodiment describes another means for solving the problem described in the sixteenth embodiment.

  In the seventeenth embodiment, in both or one of the light-shielding pattern of the metal and the light-shielding pattern of the resist film, the connection portion is wider than the other pattern portions. FIG. 48 shows a specific example thereof. FIG. 48A is a plan view of a main part of the mask PM17, and FIG. 48B is a cross-sectional view taken along line AA of FIG. Here, the end of the metal light-shielding pattern 2a is wider than other portions. The end of the light-shielding pattern 3a of the resist film overlaps the wide portion of the metal light-shielding pattern 2a. Thus, even if the relative position between the metal light-shielding pattern 2a and the resist film light-shielding pattern 3a is slightly shifted, a sufficient overlapping amount of the respective patterns can be secured. FIG. 49 shows a pattern transferred by the mask PM17. A wide portion is formed at a connection portion between the conductive film pattern 10a1 transferred by the metal light-shielding pattern 2a and the conductive film pattern 10a1 transferred by the resist film light-shielding pattern 3a, but both are connected as designed. I have. FIG. 49A is a plan view of a main part of the wafer, and FIG. 49B is a cross-sectional view taken along line AA of FIG.

  As another method, the overlapping amount of the light-shielding patterns 2a and 3a may be equal to or more than the pattern alignment accuracy.

(Embodiment 18)
The eighteenth embodiment describes a modification of the seventeenth embodiment.

  In the eighteenth embodiment, as shown in FIG. 50, in both the metal light-shielding pattern 2a of the mask PM18 and the light-shielding pattern 3a of the resist film, the connecting portions are widened. FIG. 50 (a) shows a case where the light shielding patterns 2a and 3a are arranged with good alignment, and FIG. 50 (b) shows a case where the light shielding patterns 2a and 3a are arranged shifted in the width direction. Also in this case, even if the relative position between the metal light-shielding pattern 2a and the resist film light-shielding pattern 3a is slightly displaced, it is possible to sufficiently secure the overlapping amount of each pattern. Further, in this case, since the thickening amount of the end portions of the light-shielding patterns 2a and 3a can be reduced, it can be used for transfer of a transfer pattern having a narrow adjacent pitch.

(Embodiment 19)
In the nineteenth embodiment, a case where the technical idea of the present invention is applied to the manufacture of an ASIC (Application Specific IC) such as a gate array or a standard cell will be described.

  FIG. 51 shows a configuration example of the semiconductor chip 8c4 of the nineteenth embodiment. On the main surface of the semiconductor chip 8c4, a memory unit, an IF control unit, a CPU unit, an application logic circuit, and an analog unit are arranged. In the semiconductor chip 8c4, a plurality of input / output circuit regions 26 are arranged on the outer periphery of these circuit groups along the outer periphery of the semiconductor chip 8c4. In each input / output circuit area 26, an input circuit, an output circuit, an input / output dual method circuit, and the like are arranged. Further, a bonding pad BP is arranged on the outer periphery for each input / output circuit region 25.

  Of these, the IF control unit and the application logic circuit are likely to be modified or changed due to a customer request or the like. Therefore, the portion is formed into a gate array, and a light-shielding pattern on a mask for transferring the portion is formed of a resist film as described in the first to eighteenth embodiments. Further, a light-shielding pattern on a mask for transferring a pattern in the other circuit region was formed of metal.

  FIG. 52A is a plan view of a basic cell BC arranged in the IF control unit and the application logic circuit, and FIG. 52B is a cross-sectional view of FIG. In the area where the IF control unit and the application logic circuit are formed, for example, a plurality of basic cells BC are laid all over the surface (so-called SOG structure: Sea Of Gate). The basic cell UC is composed of, for example, two nMISQn and two pMISQp. The gate electrode 10b is shared by the nMISQn and the pMISQp, and is arranged over both regions. The power supply wiring 10VDD is a power supply wiring on the high potential side (for example, about 3.3V or 1.8V), and the power supply wiring 10VSS is a power supply wiring on the low potential side (for example, about 0V). The power supply lines 10VDD and 10VSS are arranged so as to cross the gate electrode 10b and extend in the extending direction of the n-well NWL and the p-well PWL. Note that the vertical structures of nMISQn and pMISQp have been described in the first embodiment, and a description thereof will be omitted.

  The steps up to the stage of such a basic cell BC are formed. Further, since the shape of the pattern up to the stage of the basic cell BC is determined, the pattern of the basic cell BC is formed by a normal mask. A desired circuit is constituted by the arrangement of the upper wiring layer, the contact holes and the through holes. FIG. 52 (c) shows a cross-sectional view after forming a first layer wiring 10e, a second layer wiring 10g, and a third layer wiring 10h. The second layer wiring 10g is electrically connected to the first layer wiring 10e through a through hole 27a formed in the interlayer insulating film 9f. The third layer wiring 10h is electrically connected to the second layer wiring 10g through a through hole 27b formed in the interlayer insulating film 9g. The pattern shapes of the first to third layer wirings 10e, 10g, and 10h, and the arrangement of the contact holes 15 and the through holes 27a and 27b may be variously changed according to customer requirements. Uses a mask having a light-shielding pattern formed of a resist film.

  Next, an example of changing the pattern on the mask will be described.

  FIG. 53 illustrates a NAND circuit ND formed using the basic cell BC. FIG. 53A shows a symbol diagram of the NAND circuit ND, FIG. 53B shows its circuit diagram, and FIG. 53C shows its layout plan view. Here, a NAND circuit ND having two inputs I1 and I2 and one output F is illustrated.

  As shown in FIG. 53 (c), wirings 10i, 10i connected to inputs I1, I2 are electrically connected to gate electrodes 10b, 10b through contact holes 15a, 15a, respectively. The power supply wiring 10VDD is electrically connected to the semiconductor regions 14 of both pMISQp through the contact holes 15b and 15c. Wiring 10j is electrically connected to semiconductor region 14 shared by both pMISQp through contact hole 15d. The wiring 10j is electrically connected to the semiconductor region 13 of one nMISQn through the contact hole 15e. Further, the power supply wiring 10VSS is electrically connected to one nMISQn semiconductor region 13 through the contact hole 15f. In FIG. 53, the planar shape of the contact holes 15a to 15f is shown as a quadrangle, but actually, it is generally a substantially circular shape.

  FIGS. 54A and 54B show an example of a plan view of a main part of a pattern in a mask for transferring a pattern of a contact hole and a wiring of the NAND circuit ND. Since the masks in FIGS. 54A and 54B are separate, the XY axes are displayed so that the positional relationship between them can be understood.

  FIG. 54A illustrates a pattern of a mask PM19C for transferring the contact holes 15a to 15f of FIG. 53C onto a wafer. The light shielding film 3f is formed of the same resist material as the light shielding pattern 3a described in the first embodiment and the like. In the light shielding film 3f, the light shielding film 3f is partially removed, and fine light transmission patterns 16g having a square planar shape are opened at a plurality of locations. The light transmission pattern 16g is a pattern that forms the contact holes 15a to 15f. When transferring the pattern on the mask onto the wafer, a positive resist film is used on the wafer.

  FIG. 54B illustrates a pattern of a mask PM19L for transferring the wirings 10i and 10j and the power supply wirings 10VDD and 10VSS of FIG. 53C onto a wafer. The light shielding film 3g is formed of the same resist material as the light shielding pattern 3a described in the first embodiment and the like. The light-shielding film 3g is partially removed from the light-shielding film 3g, and light-transmitting patterns 16h are opened at a plurality of locations. The light transmission pattern 16h is a pattern for forming the wirings 10i and 10j and the power supply wirings 10VDD and 10VSS. When transferring the pattern on the mask onto the wafer, a negative resist film is used on the wafer.

  FIG. 55 illustrates a two-input NOR circuit NR formed using the basic cell BC. FIG. 55A shows a symbol diagram of the NOR circuit NR, FIG. 55B shows its circuit diagram, and FIG. 55C shows its layout plan view. Here, portions different from the NAND circuit configuration of FIG. 53 (c) will be described.

  As shown in FIG. 55 (c), power supply wiring 10VDD is electrically connected to semiconductor region 14 of one pMISQp through contact hole 15b. Wiring 10k is electrically connected to semiconductor region 14 of one pMISQp through contact hole 15g. The wiring 10k is electrically connected to the shared semiconductor region 13 of both nMISQn through the contact hole 15h. Further, the power supply wiring 10VSS is electrically connected to the semiconductor regions 13 of both nMISQn through the contact holes 15f and 15i. Although the planar shape of the contact holes 15a, 15b, 15f, and 15g to 15i is shown in FIG. 55 as a quadrangle, it is generally generally circular.

  FIGS. 56A and 56B show an example of a plan view of a main part of a pattern in a mask for transferring a pattern of a contact hole and a wiring of the NOR circuit NR. Since the masks in FIGS. 56 (a) and 56 (b) are separate, the XY axes are displayed so that the positional relationship between them can be understood.

  FIG. 56A illustrates a pattern of a mask PM19C for transferring the contact holes 15a, 15b, 15f, 15g to 15i of FIG. 55C onto a wafer. The light shielding film 3h is formed of the same resist material as the light shielding pattern 3a described in the first embodiment and the like. In the light shielding film 3h, the light shielding film 3h is partially removed, and fine light transmission patterns 16i having a planar square shape are opened at a plurality of locations. The light transmission pattern 16i is a pattern that forms the contact holes 15a, 15b, 15f, and 15g to 15i. When transferring the pattern on the mask onto the wafer, a positive resist film is used on the wafer.

  FIG. 56B illustrates a pattern of a mask PM19L for transferring the wirings 10i and 10k and the power supply wirings 10VDD and 10VSS of FIG. 55C onto a wafer. The light shielding film 3i is formed of the same resist material as the light shielding pattern 3a described in the first embodiment and the like. The light-shielding film 3i is partially removed from the light-shielding film 3i, and light-transmitting patterns 16j are opened at a plurality of locations. The light transmission pattern 16j is a pattern for forming the wirings 10i and 10k and the power supply wirings 10VDD and 10VSS. When transferring the pattern on the mask onto the wafer, a negative resist film is used on the wafer.

  Such pattern change of the masks PM19C and PM19L in FIGS. 54 and 56 may be performed in the same manner as described in the first embodiment and the like. For example, in order to change the pattern for the NAND circuit of the mask PM19C in FIG. 54 to the pattern for the NOR circuit of the mask PM19C in FIG. 56, the light-shielding film 3f on the mask PM19C in FIG. The light-shielding film 3h and the light-transmitting pattern 16i of the mask PM19C in FIG. 56 are formed by newly applying the resist film for forming the light-shielding film and drawing a pattern for the NOR circuit on the resist film by an electron beam or ultraviolet rays. It may be formed. That is, it is possible to easily change the pattern from the NAND circuit to the NOR circuit and vice versa from the NOR circuit to the NAND circuit in a short time. Therefore, the development and manufacturing time of a semiconductor integrated circuit device using the mask can be greatly reduced. Further, since the material cost and the process cost can be reduced, the cost of the semiconductor integrated circuit device can be significantly reduced. For this reason, it is possible to realize a cost reduction even for a semiconductor integrated circuit device manufactured in small quantities.

  As described above, also in the nineteenth embodiment, the same effects as those in the first embodiment and the like can be obtained.

(Embodiment 20)
In the twentieth embodiment, a case where the technical idea of the present invention is applied to, for example, the manufacture of a mask ROM will be described.

  In the mask ROM, a large-capacity memory can be realized because a memory cell is formed by one MIS. Further, since a write operation is not required, the entire circuit configuration can be simplified. However, since the contents of the memory change according to the customer's request, the TAT becomes longer than other ROMs (for example, an EEPROM (Electric Erasable Programmable Read Only Memory)). In addition, since a different mask must be created for each of a variety of ROM codes of a customer, there is a problem that the product cost is increased in small-quantity production. Therefore, in the twentieth embodiment, based on the base data, various patterns involving changes in the memory cell area are transferred using a mask that uses the resist film as a light-shielding pattern, thereby changing the memory contents. I did it. In the mask, a pattern for transferring a pattern in a region other than the memory cell region was formed by a light-shielding pattern made of metal. Of course, all of the integrated circuit patterns may be formed by light-shielding patterns made of a resist film.

  FIG. 57 shows base data of a mask ROM, (a) is a layout plan view of a memory cell region, (b) is a circuit diagram thereof, and (c) is a sectional view taken along line AA of (a). Is shown. Here, a mask ROM of the ion implantation program system is illustrated. Data line 10m is electrically connected to semiconductor region 13 through contact hole 15j. The gate electrode 10b is formed by a part of the word line WL. One nMOS Qn near the intersection of the data line 10m and the word line WL forms one memory cell. In this ion implantation program type ROM, the threshold voltage of nMISQn is set to a high type (high enough to prevent conduction even when the word line WL is at high level) depending on whether an impurity is introduced into the channel region of nMISQn forming the memory cell. ) And a type having a low threshold voltage (the word line WL is at a high level and conducting), and these are made to correspond to information “0” and “1”. For the transfer of the pattern of the base data, a mask using the metal as a light-shielding pattern was used. Of course, the pattern of the base data may be formed by a light shielding pattern made of a resist film.

  Next, an example of a method of rewriting information in the mask ROM will be described with reference to FIGS. 58 to 59, (a) is a plan view of a main part of a mask, (b) is a layout plan view of a memory cell area of a mask ROM showing a pattern for writing information of a memory, and (c) is FIG. 57 shows a cross-sectional view of a portion corresponding to the line AA of FIG. 57 (a) during an information writing step.

  First, in FIG. 58, an opening pattern 28a shown in (b) is formed on the database using the mask PM20 shown in (a), and as shown in (c), the semiconductor substrate 8s exposed from the opening pattern 28a is formed. A case where memory information is written by ion implantation of an impurity is illustrated. The light shielding film 3j of the mask PM20 is made of the same resist material as the light shielding pattern 3a of the first embodiment. A part of the light-shielding film 3j is removed to open a light-transmitting pattern 16k having a planar rectangular shape. The light transmission pattern 16k is a pattern for forming an opening pattern 28a in the resist film 11b on the wafer 8. The resist film 11b uses a positive resist. Note that the impurity implantation step for writing information is performed before the formation step of the gate electrode 10b (that is, the word line WL). As the impurity, if it is desired to increase the threshold value of nMISQn, for example, boron may be introduced, and if it is desired to decrease the threshold value of nMISQn, for example, phosphorus or arsenic may be introduced.

  Next, in FIG. 59, the opening patterns 28b and 28c shown in (b) are formed on the database using the mask PM20 shown in (a) and exposed from the opening patterns 28b and 28c as shown in (c). The case where memory information is written by ion-implanting impurities into the semiconductor substrate 8s to be formed is illustrated. The light shielding film 3k of the mask PM20 is made of the same resist material as the light shielding pattern 3a of the first embodiment. A part of the light-shielding film 3k is removed to open two light-transmitting patterns 16m and 16n in a planar square shape. The light transmission patterns 16m and 16n are patterns for forming opening patterns 28b and 28c in the resist film 11b on the wafer 8.

  Next, in FIG. 60, an opening pattern 28d shown in (b) is formed on the database using the mask PM20 shown in (a), and the semiconductor substrate 8s exposed from the opening pattern 28d as shown in (c). The case where memory information is written by ion-implanting an impurity into the substrate is illustrated. The light shielding film 3m of the mask PM20 is made of the same resist material as the light shielding pattern 3a of the first embodiment. A part of the light-shielding film 3m is removed to open the light transmission pattern 16pm. The light transmission pattern 16p is a pattern for forming an opening pattern 28d in the resist film 11b on the wafer 8.

  Such a pattern change of the mask PM20 in FIGS. 58 to 60 may be performed in the same manner as described in the first embodiment and the like. For example, to change the pattern of the mask PM20 in FIG. 58 to the pattern of the mask PM20 in FIG. 59, after removing the light-shielding film 3j on the mask PM20 in FIG. 58, a new light-shielding film is formed on the mask substrate. By applying a resist film and irradiating a predetermined position of the resist film with an electron beam or an ultraviolet ray, the light shielding film 3k and the light transmission patterns 16m and 16n of the mask PM20 in FIG. 59 may be formed. Thus, a wide variety of mask ROMs can be efficiently manufactured. In addition, the TAT of various types of mask ROMs can be significantly reduced. Further, since the material cost and the process cost can be reduced, the cost of the mask ROM can be significantly reduced even in small-scale production.

  As described above, also in the twentieth embodiment, the same effects as in the first embodiment and the like can be obtained.

(Embodiment 21)
The twenty-first embodiment is a modification of the twentieth embodiment, and describes an information rewriting method different from the mask ROM of the twentieth embodiment.

  FIG. 61 shows base data of the mask ROM of the twenty-first embodiment. FIG. 61 (a) is a layout plan view of a memory cell region, FIG. 61 (b) is a circuit diagram thereof, and FIG. FIG. 2 shows a cross-sectional view taken along line A. Here, a mask ROM of a contact hole program system is illustrated. In this contact hole program type ROM, programming is performed in a layout manner of contact holes (broken lines in FIG. 61B) connecting the semiconductor region 13 and the data lines 10m. Also in the twenty-first embodiment, the transfer of the pattern of the base data uses a mask using the metal as a light-shielding pattern.

  Next, an example of a method of rewriting information in a mask ROM will be described with reference to FIGS. 62, 64, and 65, (a) is a plan view of a main part of a mask, (b) is a layout plan view of a memory cell region of a mask ROM showing a pattern for writing information of a memory, (C) is a circuit diagram thereof, and (d) is a cross-sectional view taken along line AA of (b).

  First, in FIG. 62, a contact hole 15k shown in (b) is formed on the database using the mask PM21 shown in (a), and a semiconductor region of a predetermined nMISQn is formed as shown in (c) and (d). 13 illustrates a case where the memory information is written by connecting the data line 13 and the data line 10m.

  The light shielding film 3p of the mask PM21 is made of the same resist material as the light shielding pattern 3a of the first embodiment. A part of the light-shielding film 3p is removed to open a light transmitting pattern 16m having a planar rectangular shape. The light transmission pattern 16m is a pattern for forming an opening pattern for forming the contact hole 15k in the resist film on the wafer 8. The method for forming the contact hole 15k is the same as that described in the first embodiment and the like. The brief description is as follows. First, as shown in FIG. 63 (a), after a positive resist film 11b is applied on the insulating film 9d, a pattern is transferred to the resist film 11b using the mask PM21 shown in FIG. The opening pattern 28e is formed by performing the steps described above. Subsequently, by performing an etching process using the resist film 11b as an etching mask, as shown in FIG. 63B, a contact hole 15k such that a part of the semiconductor substrate 8s is exposed is formed in the insulating film 9d. I do.

  Next, in FIG. 64, two contact holes 15m and 15n shown in (b) are formed on the database using the mask PM21 shown in (a), and as shown in (c) and (d), The case where memory information is written by connecting the semiconductor region 13 of a predetermined nMISQn and the data line 10m is illustrated. The light shielding film 3q of the mask PM21 is made of the same resist material as the light shielding pattern 3a of the first embodiment. A part of the light-shielding film 3q is removed to open a light transmission pattern 16q having a rectangular shape in a plane. This light transmission pattern 16q is a pattern for forming opening patterns for forming contact holes 15m and 15n and word line contact holes in the resist film on the wafer 8. The method of forming the contact holes 15m and 15n and the word line contact hole is the same as that described with reference to FIGS.

  Next, in FIG. 65, three contact holes 15k, 15m, and 15n shown in (b) are formed on the database using the mask PM21 shown in (a), and as shown in (c) and (d). FIG. 2 illustrates a case where memory information is written by connecting a semiconductor region 13 of a predetermined nMISQn and a data line 10m. The light shielding film 3r of the mask PM21 is made of the same resist material as the light shielding pattern 3a of the first embodiment. A part of the light-shielding film 3r is removed to open a light-transmitting pattern 16r having a planar rectangular shape. The light transmission pattern 16r is a pattern for forming contact holes 15k, 15m, 15n and opening patterns for forming word line contact holes in the resist film on the wafer 8. The method of forming the contact holes 15k, 15m, 15n and the word line contact holes is the same as that described with reference to FIGS.

  Such pattern change of the mask PM21 in FIGS. 62, 64 and 65 may be performed in the same manner as described in the first embodiment and the like. For example, in order to change the pattern of the mask PM21 in FIG. 62 to the pattern of the mask PM21 in FIG. 64, after removing the light shielding film 3p on the mask PM21 in FIG. A light-shielding film 3q and a light-transmitting pattern 16q of the mask PM21 shown in FIG. 64 may be formed by applying a resist film and irradiating a predetermined position of the resist film with an electron beam or an ultraviolet ray. Thus, similarly to the twentieth embodiment, a wide variety of mask ROMs can be manufactured efficiently. In addition, the TAT of various types of mask ROMs can be significantly reduced. Further, since the material cost and the process cost can be reduced, the cost of the mask ROM can be significantly reduced even in small-scale production.

  As described above, also in the twenty-first embodiment, the same effects as those of the first embodiment can be obtained.

(Embodiment 22)
The twenty-second embodiment is a modification of the twentieth embodiment, and describes a mask ROM having a structure different from that of the twentieth embodiment.

  FIG. 66 shows a part of a NAND type mask ROM according to the twenty-second embodiment. A plurality of nMISQn forming a memory cell are connected in parallel via a semiconductor region 13. As the program method, an ion implantation method is employed. That is, the nMISQn (memory cell) of the ion-implanted portion becomes the depletion type, and the nMISQn (memory cell) of the non-ion-implanted portion becomes the enhancement type, which correspond to information “0” and “1”, respectively. It has become.

  FIG. 66 illustrates a case where an impurity is introduced into the channel region of nMISQnd to be a depletion type. An opening pattern 28f indicating a pattern for writing information of the memory indicates an opening pattern of an ion implantation mask when a program (impurity ion implantation) is performed on the nMISQnd. Note that the semiconductor region 13VSS also has a function as a power supply line on the low potential (for example, 0V = GND) side.

  The method for changing the pattern on the mask and the method for selectively introducing impurities into the wafer for programming in the twenty-second embodiment are the same as those in the twentieth embodiment, and therefore description thereof will be omitted.

  Also in the twenty-second embodiment, the same effects as in the twenty-first embodiment can be obtained.

Embodiment 23
In the present embodiment, a case will be described in which the characteristics of a semiconductor integrated circuit device are adjusted using a mask having the above-described resist film as a light-shielding pattern.

  FIG. 67 and FIG. 68 show circuits in the semiconductor integrated circuit device formed on the wafer and for adjusting the characteristics thereof.

  FIG. 67 is a circuit diagram of characteristic adjustment using a plurality of resistors R1 to Rn connected in series. By changing the connection state between a terminal Ta connected to a circuit (for example, a CPU or the like of a semiconductor integrated circuit device) and terminals Tb1 to Tbn connected to the resistors R1 to Rn by a connection portion J1, the resistance value of the entire circuit is changed. It is supposed to change.

  FIG. 68 is a circuit diagram of the characteristic adjustment using a plurality of capacitors C1 to Cn connected in series. By changing the connection state between the terminal Ta connected to the circuit and the terminals Tb1 to Tbn connected to the respective C1 to Cn by the connection portion J1, the capacitance value of the entire circuit is changed.

  At the time of development of a semiconductor integrated circuit device, for example, characteristics of the semiconductor integrated circuit device such as signal timing adjustment may be adjusted by variously changing the values of the resistance and the capacitance as described above. When a normal mask is used for transferring such a pattern, as can be seen from the circuit diagrams of FIGS. 67 and 68, the changed portion (connection portion J1) itself is small even though it is small. The mask must be remanufactured. Therefore, it takes time to manufacture the mask, and the development period of the semiconductor integrated circuit device is lengthened. In addition, the cost of the semiconductor integrated circuit device increases because waste is increased and the material cost and the process cost increase.

  Therefore, in the present embodiment, a portion of the mask where the connection portion J1 is transferred is formed by forming a resist film by a light-shielding pattern. FIG. 69 (a) schematically shows a plan view of the terminals Ta, Tb1 to Tbn formed on the wafer. Here, the terminal Ta is not connected to any of the terminals Tb1 to Tbn. FIG. 69 (b) shows a light shielding pattern 2g on the mask PM23 for transferring the terminals Ta, Tb1 to Tbn of (a). The light-shielding pattern 2g is made of the same metal as the light-shielding pattern 2a described in the first embodiment and the like. This is used as base data. Here, for example, as shown in FIG. 70A, when it is desired to connect the terminal Ta and the terminal Tb1, as shown in FIG. 70B, the main surface of the mask PM1 of the mask PM23 (light shielding of metal). On the surface on which the pattern 2g is formed), the light-shielding pattern 3s of the resist film may be formed at a position corresponding to the connection portion J1 of the terminals Ta and Tb1. The resist material, forming method, and changing method of the light-shielding pattern 3s are the same as those described in the first embodiment. Therefore, the connection between the terminal Ta and the terminals Tb1 to Tbn can be easily changed in a short time and at low cost. Therefore, the development time of the semiconductor integrated circuit device can be significantly reduced. Further, the cost of the semiconductor integrated circuit device can be reduced.

  Also in the twenty-third embodiment, it is possible to obtain the same effects as those of the first embodiment.

(Embodiment 24)
In the present embodiment, a technique for making a logic circuit of a semiconductor integrated circuit device redundant using a mask that uses a resist film as a light-shielding pattern will be described.

  FIG. 71 illustrates a redundant circuit formed on a wafer. The connection state between the terminals Tc1 to Tc3 is changed depending on how the connection portion J2 is connected to perform redundancy. Note that INV is an inverter circuit.

  Even in such a redundant circuit configuration, if a normal mask is used when transferring a pattern, the mask must be re-manufactured for redundancy even though the changed portion (connection portion J2) itself is small. For this reason, since it takes time to manufacture the mask, the development and manufacturing period of the semiconductor integrated circuit device is lengthened. In addition, the cost of the semiconductor integrated circuit device increases because waste is increased and the material cost and the process cost increase.

  Therefore, in the present embodiment, the resist film is formed by a light-shielding pattern at the portion where the connection portion J2 is transferred in the mask. FIG. 72A schematically shows a plan view of the terminal Tc1 to Tc3 formed on the wafer. Here, the terminal Tc2 is not connected to any of the terminals Tc1 and Tc3. FIG. 72 (b) shows a metal light-shielding pattern 2g on the mask PM24 for transferring the terminals Tc1 to Tc3 of (a). This is used as base data. Here, for example, when it is desired to connect the terminal Tc1 and the terminal Tc2 as shown in FIG. 73 (a), as shown in FIG. 73 (b), the main surface of the mask substrate 1 of the mask PM24 (metal light shielding) On the surface on which the pattern 2g is formed), a light-shielding pattern 3s of a resist film may be formed at a position corresponding to the connection portion J2 of the terminals Tc1 and Tc2. The resist material, forming method, and changing method of the light shielding pattern 3s are the same as those described in the first embodiment. For this reason, the connection change of the terminals Tc1 to Tc3 can be easily performed in a short time and at low cost. Therefore, the development and manufacturing time of the semiconductor integrated circuit device can be significantly reduced. Further, the cost of the semiconductor integrated circuit device can be reduced.

  According to the twenty-fourth embodiment, the same effects as those of the first embodiment can be obtained.

(Embodiment 25)
In this embodiment, an example of a series of flows in a manufacturing process of the mask described in the above embodiment and a manufacturing process of a semiconductor integrated circuit device using the mask will be described.

  In a normal mask manufacturing process, a mask (blanks) manufacturing process in which a light-shielding film such as chromium or the above-mentioned translucent film (halftone film) is formed on the entire main surface of a mask substrate, Can be divided into a mask manufacturing process for forming a pattern for forming a semiconductor integrated circuit. Sometimes the two are manufactured in separate departments.

  In the mask manufacturing process of the present embodiment, a mask blank manufacturing process, a common light-shielding pattern for forming a pattern commonly used by various projection exposure apparatuses on a peripheral portion of a mask substrate, and a common device for forming an integrated circuit pattern It is divided into a pattern forming step and a resist pattern forming step. Each process may be manufactured by a different department and a different company.

  For example, FIG. 74A shows a step of forming the common light-shielding pattern and the common device pattern. Various common patterns can be prepared for each semiconductor integrated circuit device to be manufactured or for a projection exposure apparatus used in the exposure processing. First, a common light-shielding pattern (corresponding to the light-shielding patterns 2a and 2b in the mask PM1 and the like in FIG. 1) is formed (step 100). Subsequently, the presence or absence of a defect is inspected (step 101). Here, if there is no defect, it is stocked as a completed common mask at the stage of forming the common light shielding pattern and the common device pattern (step 102). On the other hand, if there is a defect, correction and the like are performed (step 103), and stock is provided after the correction (step 102).

  As described above, in the mask manufacturing according to the present embodiment, since the mask substrate can be stocked during the manufacturing process of the mask, the time for manufacturing and developing the semiconductor integrated circuit device can be greatly reduced. In the case of a normal mask, the substrate cannot be stocked in the process of the mask substrate, and therefore, from deposition of a light-shielding film or the like (mask blanks manufacturing process) to patterning of a predetermined pattern must be performed consistently. On the other hand, in the present embodiment, masks manufactured up to the manufacturing process of the common light-shielding pattern and the common device pattern can be stocked. For this reason, in the development and manufacture of a semiconductor integrated circuit device, when forming a specific integrated circuit pattern (device pattern), the manufacture of the mask can be started from the stock stage, so that the mask manufacturing time is reduced. Can be shortened. Therefore, the step of forming the integrated circuit pattern can be completed in a short time. Therefore, as described above, the technical idea of the present invention is particularly suitable for, for example, manufacturing a mask for a logic device having a high frequency of product type development. In the case of the mask in the stage of FIG. 74A, since the metal film in the region RE is removed, there is no problem even if there is a defect such as a pinhole in the region. Therefore, quality control of the mask blanks can be eased, and the yield of the mask blanks can be greatly improved.

  Next, FIG. 74B shows a step of forming a light-shielding pattern using a resist film on the common mask. First, a light-shielding pattern (corresponding to the light-shielding pattern 3a in the mask PM1 or the like in FIG. 1) of a resist film for device manufacture is formed in the integrated circuit pattern region of the common mask as described above (step 104). Subsequently, an inspection such as a defect inspection or a dimension inspection is performed on the mask substrate (step 105). If the inspection passes, the mask is completed (step 106). However, as a result of the inspection, the rejected photomask which is out of the standard is removed from the light-shielding pattern of the resist film (Step 107) and reused (Step 108). As described above, in the present embodiment, the common mask can be reused. That is, when a light-shielding pattern for device manufacture is formed of a metal film, it is difficult to remove and reuse the light-shielding pattern from the viewpoint of ensuring the quality of the mask. On the other hand, the removal and reuse of the resist film as in the present embodiment does not take much time and can be easily performed without deteriorating the quality of the mask. Therefore, resources can be effectively used.

  Next, FIG. 74C shows a step of transferring a pattern onto a wafer by using the completed mask in a manufacturing process of a semiconductor integrated circuit device. Here, the integrated circuit pattern is transferred onto the wafer using the completed mask (step 109). When the mask is deteriorated and cannot be used or when a part of the semiconductor integrated circuit device is changed, the mask is sent again to the resist removal / reproduction step (step 108) and reused as a common mask. I do.

  As described above, according to the present embodiment, the mask can be reused from the manufacturing of the mask to the manufacturing process of the semiconductor integrated circuit device. Therefore, the development and manufacturing period of the semiconductor integrated circuit device can be shortened. Further, since unnecessary materials and steps can be reduced, the cost of the semiconductor integrated circuit device can be significantly reduced.

(Embodiment 26)
In the present embodiment, an application example in a manufacturing process of a semiconductor integrated circuit device using the mask will be described.

  Here, a case where trimming is performed for each lot will be described. That is, the average characteristic variation information of the characteristics of a large number of lots of semiconductor integrated circuit devices in mass production is fed back to the wiring layer forming process of the subsequent lot of semiconductor integrated circuit devices, and the wiring is corrected, whereby the semiconductor integrated circuit is corrected. Adjust the characteristics of the device. This wiring correction is performed using a mask having a light-shielding pattern of a resist film.

  FIG. 75 illustrates the flow. In an element forming step 301, a predetermined integrated circuit element is formed on a wafer. In a subsequent wiring layer forming step (step 302), an integrated circuit is formed by forming wiring on the wafer. Here, all the wiring layers of the semiconductor integrated circuit device are formed, and after the manufacture of the semiconductor integrated circuit device is completed, the electrical characteristics of each semiconductor integrated circuit device on the wafer are tested (step 303). At that time, the obtained average characteristic variation information of the characteristics of the semiconductor integrated circuit device is fed back to the wiring layer forming process of the semiconductor integrated circuit device following the tested lot. Based on the information, the size, shape, and the like of the wiring forming pattern on the mask are changed (step 304). As the mask, the mask using the resist film described in the above embodiment as a light-shielding pattern is used. Then, using the mask, a wiring layer of a semiconductor integrated circuit device of a subsequent lot is formed. Thus, trimming of the semiconductor integrated circuit device for each lot is performed.

  This makes it possible to provide a highly reliable semiconductor integrated circuit device with uniform electric characteristics in a short period of time. Further, when changing the pattern of the mask for trimming, useless materials and useless processes can be omitted, so that a highly reliable semiconductor integrated circuit device can be provided at low cost.

(Embodiment 27)
This embodiment describes a modification of the twenty-sixth embodiment. Here, the characteristic test of the semiconductor integrated circuit device is performed in the middle of the wiring layer forming step, and the obtained information is fed forward to the subsequent wiring layer forming step to adjust the characteristics of the semiconductor integrated circuit device. Is what you do.

  FIG. 76 illustrates the flow. First, after the element forming step (step 301), a wiring layer forming step (step 302a) is performed. Here, before reaching the final wiring layer forming step (after the wiring layer forming step is still present), an electrical characteristic test is performed on the semiconductor integrated circuit device on the wafer (step 303). At this time, based on the obtained characteristic information of the semiconductor integrated circuit device, the size, shape, and the like of the wiring forming pattern on the mask used in the subsequent final wiring layer forming step (Step 302b) are changed (Step 304). The final wiring layer refers to, for example, a layer forming a bonding pad functioning as an external terminal of a semiconductor chip or a wiring layer immediately before the layer. As the mask, the mask using the resist film described in the above embodiment as a light-shielding pattern is used. Then, the pattern of the final wiring layer on the wafer is formed using the mask. By performing trimming of the semiconductor integrated circuit device in this manner, it is possible to obtain the same effect as in the twenty-sixth embodiment.

  The technical idea of the invention in the present embodiment is to test the characteristics of a semiconductor integrated circuit device during a wiring layer forming step, and transmit the measured characteristic information to a subsequent wiring layer forming step. Based on the above, the trimming is performed using the mask, and the information is not limited to being transmitted to the final wiring layer forming step. For example, the characteristic information may be transmitted to a subsequent wiring layer forming step other than the final wiring layer, or may be transmitted to a plurality of wiring layer forming steps. Also, for example, in a so-called wafer process package technique in which a sealing step is performed at a wafer stage, there is a structure in which rewiring is performed after bonding pads are formed, and the above-described characteristic information is transmitted to the rewiring layer forming step. The trimming may be performed using the mask in the rewiring layer forming step.

(Embodiment 28)
In the twenty-eighth embodiment, a case will be described in which customer information is formed on a wafer using a light-shielding pattern of a resist film on a mask.

  In a manufacturing process of a semiconductor integrated circuit device, information such as a customer name, a number, a lot number, a manufacturing date, a product type, a grade or a version is written on a part of a wafer or a semiconductor chip as much as possible. Is preferred. By doing so, the electrical characteristics of the manufactured product, the pattern change status, and the like can be understood, and the characteristics test and selection of the semiconductor integrated circuit device can be easily performed. However, with a normal mask, it takes time and cost to manufacture the mask, so that it is not possible to write very detailed information. Therefore, in the present embodiment, the customer information is transferred using a mask using the light-shielding pattern of the resist film. This makes it possible to transfer detailed customer information onto a wafer in a short time and at low cost.

  FIG. 77 shows the flow of the manufacturing process of the semiconductor integrated circuit device. In the wiring forming step 302, customer information is transferred using a mask using a light-shielding pattern of a resist film. Upon completion of the wafer (step 303), customer information is optically read and information is managed. Thereafter, a final test is performed through an assembly process 304 (process 305). At this time, by automatically referring to the customer information, a test program suitable for the semiconductor integrated circuit device is automatically recognized and an operation test of the circuit is performed. Therefore, a more accurate test can be performed.

  FIG. 78A is a plan view of a main part of the wafer 8. The customer information is formed in the semiconductor chip 8c (area 30a) or in a cutting area between adjacent semiconductor chips 8c (area 30b). FIGS. 78 (b) and (c) illustrate customer information patterns formed in the area 30a or the area 30b. FIG. 78D illustrates a cross-sectional view taken along line AA of FIG. FIG. 78 (b) shows a barcode formed by arranging a plurality of conductor film patterns 10n in parallel. FIG. 78 (c) shows characters and numerals formed by the conductor film pattern 10p. The conductor film patterns 10n and 10p are formed simultaneously with the wiring pattern.

  FIG. 79 shows an example of a mask used to form the conductive film pattern 10n in FIG. 78 (b). FIG. 79A illustrates a case where a light shielding pattern 3t for forming customer information is formed of a resist film on a part of the mask PM2 of the second embodiment. The light shielding pattern 3t is formed of the same material at the same forming step as the light shielding pattern 3a. FIG. 79 (b) illustrates a case where a light transmission pattern 16s for forming customer information is formed on a part of the mask PM3 of the third embodiment. The light transmission pattern 16s is formed by removing a part of the light shielding film 3u. The light shielding film 3u is formed of the same material at the same forming step as the light shielding film 3b. The light transmission pattern 16s of the light shielding film 3u is formed at the same time when the light transmission pattern 16b is formed on the light shielding film 3b.

  Further, a simple circuit pattern may be formed by a light-shielding pattern of a resist so that a binary signal of “0” and “1” can be read from a predetermined bonding pad (or a lead pin after packaging) of the semiconductor chip. . Thus, in the test process of the semiconductor integrated circuit device after the assembly process, the customer information can be electrically read from the semiconductor integrated circuit device, so that a test program suitable for the semiconductor integrated circuit device is automatically recognized. Thus, an operation test of the circuit can be performed. The configuration of the above circuit depends on whether or not connection is made between a bonding pad (or a lead) and a power supply terminal (high potential or low potential (0 V)) in the semiconductor chip, or is connected to a power supply terminal of either high or low. "1" or "0" is assigned to the pad (or lead) depending on whether or not to do so. The connection pattern portion is formed by the light-shielding pattern of the resist film as described in Embodiments 23 and 24. Thereby, information can be easily written and rewritten on the mask. Of course, the binary signal for the customer information may be output to the lead by forming a simple circuit on the semiconductor chip with the light shielding pattern of the resist film.

  As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the wiring has a normal wiring structure has been described. However, the present invention is not limited to this. For example, a conductive film may be embedded in a wiring or a hole groove formed in an insulating film. The wiring may be formed by a so-called Dashiman method or a dual damascene method.

  Further, in the above-described embodiment, a case has been described in which a semiconductor substrate made of a single semiconductor is used as a semiconductor integrated circuit substrate. However, the present invention is not limited to this. For example, a thin semiconductor layer is provided on an insulating layer. An SOI (Silicon On Insulator) substrate or an epitaxial substrate having an epitaxial layer provided on a semiconductor substrate may be used.

  In the case where the mark pattern is formed of a resist film in the above-described embodiment, mark detection light (for example, probe light of a defect inspection device (light having a wavelength longer than the exposure wavelength, for example, a wavelength of 500 nm: information An absorbing material that absorbs the detection light)) may be added.

  In the above description, the case where the invention made by the present inventor is mainly applied to the manufacture of a semiconductor integrated circuit device, which is the application field in the background, has been described.However, the invention is not limited to this. The present invention is also applicable to a method of manufacturing another electronic device (electronic circuit device) such as a magnetic head.

  INDUSTRIAL APPLICATION This invention is applicable to the manufacturing industry of a semiconductor integrated circuit and precision equipment.

1A is a plan view of a photomask according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line AA in FIG. FIG. 4 is an explanatory diagram schematically showing a holding unit of the photomask when a predetermined pattern is drawn on the photomask. (A)-(c) is sectional drawing in the manufacturing process of the photomask of FIG. FIG. 3 is a graph showing the spectral transmittance of a typical electron beam resist film. (A)-(c) is a modification of the manufacturing process of the photomask of FIG. 1, and is a cross-sectional view during the manufacturing process. (A)-(c) is a modification of the manufacturing process of the photomask of FIG. 1, and is a cross-sectional view during the manufacturing process. 2A and 2B are manufacturing steps of a semiconductor integrated circuit device using the photomask of FIG. 1, wherein FIG. 2A is a plan view of a main part of a semiconductor wafer, and FIG. 2B is a cross-sectional view taken along line AA of FIG. 7A is a step following FIG. 7, wherein FIG. 8A is a plan view of a main part of the semiconductor wafer, and FIG. 8B is a cross-sectional view taken along line AA of FIG. 8A is a process subsequent to FIG. 8, wherein FIG. 9A is a plan view of a main part of the semiconductor wafer, and FIG. 9B is a cross-sectional view taken along line AA of FIG. FIG. 2 is an explanatory diagram of an example of a reduced projection exposure apparatus used in the present embodiment. FIG. 2 is a cross-sectional view of a principal part during a manufacturing step of a specific semiconductor integrated circuit device using the photomask of FIG. 1. FIG. 12 is an essential part cross sectional view of the specific semiconductor integrated circuit device during a manufacturing step using the photomask following FIG. 11; FIG. 13 is an essential part cross sectional view of the concrete semiconductor integrated circuit device during a manufacturing step using the photomask following FIG. 12; 14 is a fragmentary cross-sectional view of a specific semiconductor integrated circuit device during a manufacturing step using a photomask following that of FIG. 13; FIG. 2A is a plan view of the photomask of FIG. 1 in a process of modifying and changing a light-shielding pattern formed of a resist film, and FIG. 2B is a cross-sectional view taken along line AA of FIG. 15A is a plan view of the photomask of FIG. 1 in a step of correcting and changing a light-shielding pattern formed of a resist film, and FIG. 15B is a cross-sectional view taken along a line AA in FIG. FIG. 17A is a plan view of a semiconductor wafer showing a pattern transferred by the photomask of FIG. 16, and FIG. 17B is a cross-sectional view taken along line AA of FIG. FIG. 9 is a plan view of an example of a semiconductor chip that is effective when the photomask of the present embodiment is used during development or manufacture. FIG. 13 is a plan view of another example of a semiconductor chip that is effective when the photomask of the present embodiment is used during development or manufacture. FIG. 11 is a plan view of still another example of a semiconductor chip that is effective when the photomask of the present embodiment is used during development or manufacture. (A) is a plan view of a photomask according to another embodiment of the present invention, and (b) is a cross-sectional view taken along line AA of (a). FIG. 22A is a plan view of the photomask of FIG. 21 in a process of modifying and changing a light-shielding pattern formed of a resist film, and FIG. 21B is a cross-sectional view taken along line AA of FIG. 2A is a plan view of the photomask of FIG. 1 in a process of modifying and changing a light-shielding pattern formed of a resist film, and FIG. 2B is a cross-sectional view taken along line AA of FIG. (A) is a plan view of a photomask according to another embodiment of the present invention, and (b) is a cross-sectional view taken along line AA of (a). 24A is a plan view of the photomask of FIG. 24 in a process of modifying and changing a light-shielding pattern formed of a resist film, and FIG. 24B is a cross-sectional view taken along line AA of FIG. 2A is a plan view of the photomask of FIG. 1 in a process of modifying and changing a light-shielding pattern formed of a resist film, and FIG. 2B is a cross-sectional view taken along line AA of FIG. (A) is a plan view of a first photomask according to another embodiment of the present invention, and (b) is a cross-sectional view taken along line AA of (a). (A) is a plan view of a second photomask according to another embodiment of the present invention, and (b) is a cross-sectional view taken along line AA of (a). FIG. 29A is a plan view of the photomask of FIG. 28 in a process of modifying and changing a light-shielding pattern formed of a resist film, and FIG. 28B is a cross-sectional view taken along line AA of FIG. FIG. 29A is a plan view of the photomask of FIG. 28 in a process of modifying and changing a light-shielding pattern formed of a resist film, and FIG. 28B is a cross-sectional view taken along line AA of FIG. (A) is a cross-sectional view of a photomask according to another embodiment of the present invention, and (b) is a cross-sectional view of the photomask showing a state of phase inversion of exposure light transmitted through each part of the photomask of (a). is there. FIG. 9A is a cross-sectional view of a photomask according to another embodiment of the present invention, and FIG. 9B is a cross-sectional view of the photomask of FIG. FIG. 9A is a cross-sectional view of a photomask according to another embodiment of the present invention, and FIG. 9B is a cross-sectional view of the photomask of FIG. (A)-(d) is sectional drawing during the manufacturing process of the photomask which is another embodiment of this invention. (A) is a cross-sectional view of a photomask according to another embodiment of the present invention, and (b) is a cross-sectional view of the photomask showing a state of phase inversion of exposure light transmitted through each part of the photomask of (a). is there. (A)-(e) is sectional drawing in the manufacturing process of the photomask of FIG. (A) is a cross-sectional view of a photomask according to another embodiment of the present invention, and (b) is a cross-sectional view of the photomask showing a state of phase inversion of exposure light transmitted through each part of the photomask of (a). is there. FIG. 9 is a cross-sectional view of a photomask according to another embodiment of the present invention. FIG. 9 is a cross-sectional view of a photomask according to another embodiment of the present invention. FIG. 7A is a cross-sectional view of a photomask according to another embodiment of the present invention, and FIG. 7B is a cross-sectional view of the photomask of FIG. FIG. 7A is a cross-sectional view of a photomask according to another embodiment of the present invention, and FIG. 7B is a cross-sectional view of the photomask of FIG. (A) is a cross-sectional view of a photomask according to another embodiment of the present invention, and (b) is an explanatory diagram when the photomask of (a) is mounted on an exposure apparatus. (A) is a plan view of a connection portion between a light-shielding pattern made of a metal of a photomask and a light-shielding pattern made of a resist film according to another embodiment of the present invention, and (b) is a cross-sectional view taken along line AA of (a). It is. (A) and (b) are explanatory views in the case where a position shift occurs between a light-shielding pattern made of metal and a light-shielding pattern made of a resist film in a photomask according to another embodiment of the present invention. (A) is a plan view of a connection portion between a light-shielding pattern made of a metal of a photomask and a light-shielding pattern made of a resist film according to another embodiment of the present invention, and (b) is a cross-sectional view taken along line AA of (a). It is. (A) is an explanatory view showing the case where the positions of the light-shielding pattern made of metal and the light-shielding pattern made of the resist film are shifted in the photomask of FIG. 45, and (b) is transferred to a semiconductor wafer using the photomask of (a). (C) is a cross-sectional view taken along line AA of (b). (A) and (b) are main part plan views of the semiconductor wafer also showing the upper pattern layer of FIG. 46 (b), and (c) is a cross-sectional view taken along line AA of (a) and (b). is there. (A) is a plan view of a connection portion between a light-shielding pattern made of a metal of a photomask and a light-shielding pattern made of a resist film according to another embodiment of the present invention, and (b) is a cross-sectional view taken along line AA of (a). It is. 49A is a plan view of a pattern transferred to a semiconductor wafer using the photomask of FIG. 48, and FIG. 49B is a cross-sectional view taken along line AA of FIG. (A) is a plan view of a main part of a connection portion between a light-shielding pattern made of a metal of a photomask and a light-shielding pattern made of a resist film according to another embodiment of the present invention. FIG. 9 is a plan view of a main part showing a case where a light-shielding pattern formed by a resist film is misaligned. FIG. 11 is a plan view of a semiconductor chip according to another embodiment of the present invention. (A) is a plan view of a basic cell in the semiconductor chip of FIG. 51, (b) is a cross-sectional view of a main part of (a), and (c) is a cross-sectional view of a main part of the semiconductor chip when a wiring layer is formed in (b). FIG. 51A is a symbol diagram of a NAND circuit formed on the semiconductor chip of FIG. 51, FIG. 52B is a circuit diagram of FIG. 51A, and FIG. 53C is a plan view of a principal part showing a pattern layout of FIG. (A) and (b) of FIG. 53 are photomasks of another embodiment of the present invention, and are plan views of main parts of the photomask used when transferring the circuit pattern of FIG. 53. 51A is a symbol diagram of a NOR circuit formed on the semiconductor chip of FIG. 51, FIG. 52B is a circuit diagram of FIG. 51A, and FIG. 53C is a plan view of a principal part showing a pattern layout of FIG. (A) and (b) are plan views of a main part of a photomask according to another embodiment of the present invention, which is used when the circuit pattern of FIG. 55 is transferred. 2A is a plan view of a main part of a mask ROM, FIG. 2B is a circuit diagram of FIG. 2A, and FIG. 2C is a cross-sectional view taken along line AA of FIG. (A) is a photomask of another embodiment of the present invention, and is a plan view of a main portion of a photomask used when a pattern for writing data is transferred onto a semiconductor wafer by ion implantation into a mask ROM of FIG. FIG. 2B is a plan view of a main part of the semiconductor wafer showing a position of a pattern transferred by the photomask of FIG. 2A, and FIG. 2C is a cross-sectional view of the semiconductor wafer showing a state of data writing in FIG. is there. (A) is a photomask of another embodiment of the present invention, and is a plan view of a main portion of a photomask used when a pattern for writing data is transferred onto a semiconductor wafer by ion implantation into a mask ROM of FIG. FIG. 2B is a plan view of a main part of the semiconductor wafer showing a position of a pattern transferred by the photomask of FIG. 2A, and FIG. 2C is a cross-sectional view of the semiconductor wafer showing a state of data writing in FIG. is there. (A) is a photomask of another embodiment of the present invention, and is a plan view of a main portion of a photomask used when a pattern for writing data is transferred onto a semiconductor wafer by ion implantation into a mask ROM of FIG. FIG. 2B is a plan view of a main part of the semiconductor wafer showing a position of a pattern transferred by the photomask of FIG. 2A, and FIG. 2C is a cross-sectional view of the semiconductor wafer showing a state of data writing in FIG. is there. (A) is a plan view of a main part of another mask ROM, (b) is a circuit diagram of (a), and (c) is a cross-sectional view taken along line AA of (a). (A) is a photomask of another embodiment of the present invention, and is a plan view of a main part of a photomask used when a contact hole pattern for writing data to a mask ROM of FIG. 61 is transferred onto a semiconductor wafer. (B) is a main part plan view of a semiconductor wafer showing a position of a pattern transferred by the photomask of (a), (c) is a circuit diagram of (b), and (d) is an AA of (b) It is sectional drawing of a line. FIGS. 63 (a) and (b) are cross-sectional views of main parts of a semiconductor wafer for describing a method of forming the contact holes of FIG. (A) is a photomask of another embodiment of the present invention, and is a plan view of a main part of a photomask used when a contact hole pattern for writing data to a mask ROM of FIG. 61 is transferred onto a semiconductor wafer. (B) is a main part plan view of a semiconductor wafer showing a position of a pattern transferred by the photomask of (a), (c) is a circuit diagram of (b), and (d) is an AA of (b) It is sectional drawing of a line. (A) is a photomask of another embodiment of the present invention, and is a plan view of a main part of a photomask used when a contact hole pattern for writing data to a mask ROM of FIG. 61 is transferred onto a semiconductor wafer. (B) is a main part plan view of a semiconductor wafer showing a position of a pattern transferred by the photomask of (a), (c) is a circuit diagram of (b), and (d) is an AA of (b) It is sectional drawing of a line. (A) is a main part plan view of a mask ROM according to another embodiment of the present invention, (b) is a circuit diagram of (a), and (c) is a cross-sectional view taken along line AA of (a). . FIG. 14 is an explanatory diagram of characteristic adjustment of a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 14 is an explanatory diagram of characteristic adjustment of a semiconductor integrated circuit device according to another embodiment of the present invention. (A) is an explanatory view schematically showing a pattern of the terminal of FIG. 67 or FIG. 68 on a semiconductor wafer, and (b) is a plan view of a main part of a photomask used for transferring the pattern of (a). 68A is an explanatory view of a pattern of the terminal shown in FIG. 67 or FIG. 68 on a semiconductor wafer, and FIG. 67B is a plan view of a main part of a photomask used for transferring the pattern of FIG. FIG. 14 is an explanatory diagram of a redundant configuration of a semiconductor integrated circuit device according to another embodiment of the present invention. 71A is an explanatory view schematically showing a terminal pattern of FIG. 71 on a semiconductor wafer, and FIG. 72B is a plan view of a main part of a photomask used for transferring the pattern of FIG. 71A is an explanatory diagram of a terminal pattern of FIG. 71 on a semiconductor wafer, and FIG. 71B is a plan view of a main part of a photomask used for transferring the pattern of FIG. (A)-(c) is explanatory drawing of an example of a series of flows in the photomask used in the manufacturing process of the semiconductor integrated circuit device which is another embodiment of the invention. It is an explanatory view of a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention. It is an explanatory view of a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention. It is an explanatory view of a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention. (A) is a plan view of a main part of a semiconductor wafer during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention, and (b) and (c) describe information transferred onto the semiconductor wafer. FIG. 2D is a plan view of a main part of a semiconductor wafer showing an example, and FIG. 2D is a cross-sectional view taken along line AA in FIG. (A) and (b) are plan views of a main part of a photomask according to another embodiment of the present invention, which is used when transferring the information of FIG. 78 (b).

Explanation of reference numerals

Reference Signs List 1 mask substrate 2 light shielding film 2a light shielding pattern 2b light shielding pattern 2c light shielding pattern 2d light shielding film 2e light shielding film 2f light shielding film 2g light shielding pattern 3 resist film 3a light shielding pattern 3b light shielding film 3c halftone pattern 3d halftone pattern 3e halftone pattern 3f to 3i Light-shielding films 3j, 3k, 3m Light-shielding films 3p to 3r Light-shielding films 3s Light-shielding patterns 3t Light-shielding patterns 3u Light-shielding films 4a Mark patterns 4b Mark patterns 5 Mounting portions 5A Regions 6a Resist films 7a Transparent conductive films 7b Water-soluble conductive organic films 8 Semiconductors Wafer 8s semiconductor substrate 8c1-8c3 semiconductor chip 9a insulating film 9b field insulating film 9c gate insulating film 9d interlayer insulating film 9e SOG film 9f interlayer insulating film 10a conductive film 10a1 conductive film pattern 10b gate electrode 10c wiring 10d resistance 10 First layer wiring 10f Conductive film pattern 10g Second layer wiring 10h Third layer wiring 10i to 10k Wiring 10VDD Power supply wiring 10VSS Power supply wiring 10m Data line 10n Conductive film pattern 11a Resist film 11a1 Resist pattern 12 Reduction projection exposure apparatus 12a Light source 12b Fly Eye lens 12c Illumination shape adjustment aperture 12d1, 12d2 Condenser lens 12e Mirror 12f Projection lens 12g Mask position control means 12h Mask stage 12i Position detection means 12j Sample stage 12k Z stage 12m XY stage 12n Main control system 12p1, 12p2 Drive means 12q mirror 12r Laser length measuring device 13 Semiconductor region 14 Semiconductor region 15 Contact holes 15a to 15i Contact holes 15j Contact holes 15k, 15m, 15n Contact holes 6a Light transmission pattern 16b Light transmission pattern 16c Light transmission opening area 16d Light transmission opening area 16e Light transmission opening area 16f Light transmission patterns 16g-16j Light transmission patterns 16k Light transmission patterns 16m, 16n, 16p-16r Light transmission patterns 16s Light transmission Pattern 18 Groove 19 Phase adjustment film 20 Resist film 21 Halftone film 21a Halftone pattern 22a, 22b Phase shifter 23 Protective film 24 Protective film 25 Through hole 26 Input / output circuit regions 27a, 27b Through holes 28a to 28e Opening pattern 200 Mask holding Part 200a three-point pin 200b pressing pin 200m mark pattern PM1 to PM3, PM4 to PM21, PM23, PM24 photomask PM41 first photomask PM42 second photomask PM19C Mask PM19L photomask WL the word line PE pellicle PEf pellicle sticking frame EA ground NWL n-well PWL p-well Qp pMIS
Qn nMIS
D1 to D3 Element transfer area BC Basic cell ND NAND circuit NR NOR circuit INV Inverter circuit R1 to Rn Resistance C1 to Cn Capacitor Ta Terminal Tb1 to Tbn Terminal Tc1 to Tc3 Terminal J1, J2 Connection

Claims (9)

A method for manufacturing a photomask, comprising the following steps:
(A) forming a light-shielding pattern made of a metal for transferring an integrated circuit pattern on a mask substrate;
(B) depositing a first resist film on the mask substrate;
(C) depositing a second resist film on the first resist film;
(D) forming a light-shielding pattern by patterning the second resist film;
(E) patterning the first resist film using the light-shielding pattern formed of the second resist film as an etching mask;   2. The method for manufacturing a photomask according to claim 1, wherein the first resist film is a phase adjustment film that causes a phase difference in transmitted light.   A photomask comprising a mask substrate having a light-shielding pattern made of a metal for transferring an integrated circuit pattern and a halftone pattern made of a resist film for transferring the integrated circuit pattern.   A mask substrate, a light-shielding pattern made of a metal for transferring an integrated circuit pattern, a phase shifter for transferring the integrated circuit pattern, and a resist provided so as to surround the periphery of the phase shifter for the pattern for transferring the integrated circuit pattern. A photomask having a light-shielding pattern made of a film.   A photomask comprising a mask substrate having a light-shielding pattern made of a resist film for transferring an integrated circuit pattern and a halftone pattern for transferring the integrated circuit pattern made of a material different from that of the resist film.   A photomask, comprising: a mask substrate having a halftone pattern formed of a resist film for transferring an integrated circuit pattern and the halftone pattern formed of a material different from the resist film for transferring an integrated circuit pattern.   A photomask comprising a mask substrate having a Levenson-type phase shift pattern for transferring an integrated circuit pattern and a light-shielding pattern formed of a resist film for transferring an integrated circuit pattern.   A mask substrate, a Levenson-type phase shift pattern for transferring an integrated circuit pattern, a phase shifter for transferring the integrated circuit pattern, and a resist provided so as to surround the periphery of the phase shifter, the pattern for transferring the integrated circuit pattern. A photomask having a light-shielding pattern made of a film.   A light-shielding pattern made of a metal for transferring an integrated circuit pattern on a mask substrate; and a resist pattern which is a pattern for transferring the integrated circuit pattern, wherein a second resist film is stacked on a first resist film. And a halftone pattern is formed by one of the first and second resist films.

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