JP2004221338A - Semiconductor substrate with through electrode, method for manufacturing the same, and electronic device - Google Patents

Semiconductor substrate with through electrode, method for manufacturing the same, and electronic device Download PDF

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JP2004221338A
JP2004221338A JP2003007127A JP2003007127A JP2004221338A JP 2004221338 A JP2004221338 A JP 2004221338A JP 2003007127 A JP2003007127 A JP 2003007127A JP 2003007127 A JP2003007127 A JP 2003007127A JP 2004221338 A JP2004221338 A JP 2004221338A
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semiconductor substrate
insulating layer
main surface
electrode
filling portion
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JP4060195B2 (en
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Satoshi Yamamoto
敏 山本
Isao Takizawa
功 滝沢
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Fujikura Ltd
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Fujikura Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor substrate by which the manufacturing cost can be reduced and products are also manufactured with a high yield, a semiconductor substrate with a through electrode that is manufactured by the method, and an electronic device using the same. <P>SOLUTION: The method for manufacturing the semiconductor substrate 6 with a through electrode includes a step where a micro hole 2 of the semiconductor substrate 1 made only on one main surface of the semiconductor substrate 1 is filled with a conductive substance to form a filled part 4, a step where the other main surface 1b of the semiconductor substrate 1 is etched to protrude the filled part 4 from the other main surface 1b thereof, a step where an insulation layer 32 is formed in a smaller thickness than a projecting height of the filled part 4 from the other main surface 1b, and the step where the section of the filled part 4 projecting from the insulation layer 32 is ground to make the filled part 4 to be an electrode penetrating the semiconductor substrate 1. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、電子デバイスや光デバイスなどの配線や、デバイスを積層溶接する際の配線層として好適に利用できる貫通電極を有する半導体基板の製造方法、及びそれにより製造された貫通電極付き半導体基板に関する。
【０００２】
【従来の技術】
半導体基板を積層した状態でデバイス内部に実装する場合、この半導体基板に貫通電極を設けることによって、電極間の配線の少スペース化が可能となり、電子デバイスや光デバイスなどの小型化、高機能化が実現できる。
図２は、半導体基板１１に形成された貫通電極の一例を示す断面図である。この貫通電極は、シリコンなどからなる半導体基板１１の２つの主面を貫通するように形成された微細孔１２内に、金属などの導電性物質１４が充填されたものである。
【０００３】
図３は、従来の貫通電極付き半導体基板の製造方法の一例を工程順に示す断面図である（特願２００２−３２４１３５号）。
まず図３（ａ）に示されたように、半導体基板１０１の一方の主面１０１ａのみに開口した非貫通の微細孔１０２を形成する。次に図３（ｂ）に示されたように、微細孔１０２の内壁と半導体基板１０１の２つの主面１０１ａ，１０１ｂに絶縁層１３１を形成する。そして、図３（ｃ）に示されたように、微細孔１０２内に金属などの導電性物質を充填して固化し、充填部１０４を形成する。
次に、図３（ｄ）に示されたように、半導体基板１０１の他方の主面１０１ｂをエッチングして２点鎖線部を除去し、充填部１０４が半導体基板１０１の他方の主面１０１ｂから５μｍ程度突出した状態とする。そして、図３（ｅ）に示されたように、半導体基板１０１の他方の主面１０１ｂ上に、充填部１０４の突出高さよりも厚く絶縁層１３２を形成する。通常、絶縁層１３２の厚さは６μｍ程度である。
その後、絶縁層１３２全面を研磨して、図３（ｆ）に示されたように２点鎖線部を除去し、導電性物質１０４を露出させて貫通電極とする。
【０００４】
【発明が解決しようとする課題】
上記した従来の方法では、図３（ｆ）に示されたように、充填部１０４のうち、半導体基板１０１の他方の主面１０１ｂから突出した部分も含めて絶縁層１３２全面を研磨するため、表面に研磨ムラが生じ易い。このため、研磨ムラを考慮して、予め絶縁層１３２を半導体基板１０１の他方の主面上に６μｍ程度と厚く形成しておく必要がある（図３（ｅ））。
例えば、ＣＶＤ法などにより絶縁層１３２を形成する場合、絶縁層１３２を厚くするためにはプロセス時間を長くする必要がある。また、絶縁層１３２に係る材料費が増加し、製造コストが高くなってしまう。
更に、絶縁層１３２が厚いほど、絶縁層１３２と半導体基板１０１との熱膨張係数の差によって半導体基板１０１に反りが生じ易くなり、絶縁層１３２を精度良く研磨することが難しくなる。このため、貫通電極付き半導体基板の歩留まりを大きく低下させることとなる。
【０００５】
本発明の目的は、上記した事情に鑑みなされたものである。すなわち絶縁層の形成に係る時間の短縮と材料費の削減が実現でき、また歩留まり良く製造でき、かつ絶縁層と半導体基板との熱膨張係数の差によって生じる半導体基板の反りがほとんど無く、また研磨ムラのない絶縁層が形成された貫通電極付き半導体基板が製造できる製造方法と、それにより製造された貫通電極付き半導体基板、及びそれを用いた電子機器を提供することを目的とする。
【０００６】
【課題を解決するための手段】
請求項１に係る発明は、一方の主面のみに開口した微細孔を有する半導体基板の微細孔内に導電性物質を充填して充填部を形成する工程と、半導体基板の他方の主面をエッチングして、充填部が半導体基板の他方の主面から突出した状態とする工程と、エッチング後の半導体基板の他方の主面上に、該他方の主面からの充填部の突出高さ寸法よりも小さい厚さ寸法で絶縁層を形成する工程と、充填部のうち、前記絶縁層から突出した部分が無くなるように加工して、前記充填部と絶縁層の表面を同一の高さとする工程とを少なくとも有することを特徴とする貫通電極付き半導体基板の製造方法である。
請求項２に係る発明は、前記半導体基板の他方の主面をエッチングする工程にて、半導体基板の他方の主面からの充填部の突出高さ寸法Ｔ１が５μｍ≦Ｔ１≦２０μｍとなる状態とし、前記絶縁層を形成する工程にて、エッチング後の半導体基板の他方の主面上に、絶縁層の厚さ寸法Ｔ２が０．３μｍ≦Ｔ２＜５μｍとなるように絶縁層を形成することを特徴とする請求項１に記載の貫通電極付き半導体基板の製造方法である。
請求項３に係る発明は、請求項１又は２に記載の方法で製造されたことを特徴とする貫通電極付き半導体基板である。
請求項４に係る発明は、請求項３に記載の半導体基板を有することを特徴とする電子装置である。
【０００７】
【発明の実施の形態】
［貫通電極付き半導体基板の製造方法、貫通電極付き半導体基板］
図１は、本実施形態の貫通電極付き半導体基板の製造方法の一例を工程順に示す断面図である。
まず、一方の主面１ａのみに開口した非貫通の微細孔２を有する半導体基板１を以下の方法により用意する。
半導体基板１として、厚さが３５０μｍのシリコン基板を用い、ＤＲＩＥ法（ＤＲＩＥ：Ｄｅｅｐ−Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）を用いた方法により、前記半導体基板１の一方の主面１ａに、直径が５０μｍ、深さが３００μｍ程度の微細孔２を形成する。ここで、ＤＲＩＥ法を用いた方法とは、エッチングガスとして六フッ化硫黄（ＳＦ６）を用い、高密度プラズマによるエッチングと、基板壁面へのパッシベーション製膜とを交互に行うこと（Ｂｏｓｃｈプロセス）によって、半導体基板１を深堀エッチングして、半導体基板１の一方の主面１ａに微細孔２を形成する方法である。
ここで、本実施形態では、半導体基板１の２つの主面のうち、非貫通の微細孔２が開口している主面を一方の主面１ａとし、微細孔２が開口していない主面を他方の主面１ｂと言う。また図１は、誇張して描いており、半導体基板１や各層の厚さ、微細孔２などの寸法比は、実際のものと一致していない。
【０００８】
なお、半導体基板１として、シリコン基板を採用しているが、例えばガリウム砒素（ＧａＡｓ）などの半導体材料からなるもの、エポキシ樹脂などの有機材料やガラスなどと、半導体材料からなる基板とを積層一体化したものなども採用可能である。半導体基板１の厚さは、５０μｍ〜１ｍｍ程度のものが使用できる。
また、微細孔２の直径は、５μｍ〜２００μｍ程度であり、深さは半導体基板１を貫通しなければ、半導体基板１の厚さなどに応じて適宜設定される。微細孔２の断面形状（軸方向に垂直な断面の形状）も、円形、楕円形、三角形、矩形（四角形を含む）などいかなる形状であっても良い。
この微細孔２を形成する方法としては、前記したＤＲＩＥ法を用いた方法以外に、水酸化カリウム（ＫＯＨ）水溶液などのエッチング溶液を用いたウエットエッチング法，マイクロドリルによる機械加工法，光誘起電解研磨法なども採用可能である。
【０００９】
次に、半導体基板１を熱酸化処理によって、図１（ｂ）に示されたように、微細孔２の内壁と半導体基板１の２つの主面上に酸化シリコン（ＳｉＯ２）からなる絶縁層３１を形成する。ここで、図１中では、絶縁層を厚く描いているが、実際はきわめて薄いものである。
微細孔２の内壁と半導体基板１の２つの主面上に絶縁層３１を形成する方法は、熱酸化処理以外に、プラズマＣＶＤ法により酸化シリコン（ＳｉＯ２）を形成する方法や、絶縁樹脂をコーティングして樹脂層とする方法なども適用できる。
【００１０】
そして、溶融金属吸引法などによって、図１（ｃ）に示されたように、微細孔２内に導電性物質として金−錫合金（Ａｕ（８０重量％）−Ｓｎ（２０重量％））を充填する。
溶融金属吸引法としては、一例を以下に示す。導電性物質の金−錫合金（Ａｕ（８０重量％）−Ｓｎ（２０重量％））を溶融状態で貯留した溶融金属槽と、前記半導体基板１とを減圧チャンバーに収容し、この減圧チャンバー内を減圧する。減圧状態を保ったまま、半導体基板１を溶融金属槽の溶融状態の導電性物質中に浸漬する。この溶融状態の導電性物質への半導体基板１の浸漬は、その一方の主面１ａを上側として、一方の主面１ａが露出しないように半導体基板１全体を溶融状態の導電性物質中に埋没させることで行い、次いで減圧チャンバー内を加圧することによって、半導体基板１に形成された微細孔２内に溶融状態の導電性物質を流入、充填させることができる。
そして、半導体基板１を溶融状態の導電性物質から引き上げ、導電性物質を冷却固化することによって、微細孔２内に導電性物質として金−錫合金（Ａｕ（８０重量％）−Ｓｎ（２０重量％））が充填された状態となる。この微細孔２内に充填され、固化した導電性物質が充填部４となる。
【００１１】
なお、導電性物質は、特に限定されず、異なる組成の金−錫合金や、錫（Ｓｎ），インジウム（Ｉｎ）などの金属、また錫−鉛（Ｓｎ−Ｐｂ）合金系，錫（Ｓｎ）基，鉛（Ｐｂ）基，金（Ａｕ）基，インジウム（Ｉｎ）基，アルミニウム（Ａｌ）基などのハンダを使用しても構わない。
この微細孔２に導電性物質を充填する方法は、前記した方法以外に、印刷法によりペースト状の導電性物質を微細孔２周辺に転写し、更に減圧して微細孔２内充填する方法や、メッキ法などが適用できる。
【００１２】
次に、前記微細孔２内に導電性物質からなる充填部４が充填された半導体基板１（図１（ｃ））の他方の主面１ｂをある程度研磨した後、六フッ化硫黄（ＳＦ６）を用いたドライエッチングによって、半導体基板１の他方の主面１ｂのうち、シリコン（Ｓｉ）部分をエッチングする。以上により、図１（ｄ）の２点鎖線で示された部分が除去されて、微細孔２に充填された充填部４が半導体基板１の他方の主面１ｂから突出した状態とする。
本実施形態では、半導体基板１の他方の主面１ｂからの充填部４の突出高さ寸法Ｔ１は８μｍである。また、充填部４と絶縁層３１のうち、半導体基板１の他方の主面１ｂから突出した部分を凸部５と言う。
なお、この半導体基板１の他方の主面１ｂをエッチングする工程は、まず半導体基板１の他方の主面１ｂ上の絶縁層３１をエッチングして除去し、次いで六フッ化硫黄（ＳＦ６）を用いたドライエッチングによって、半導体基板１の他方の主面１ｂのうち、シリコン（Ｓｉ）部分をエッチングする方法であってもよい。
【００１３】
そして、テトラエトキシシラン（ＴＥＯＳ）を原料としてプラズマＣＶＤ法により酸化珪素（ＳｉＯ２）からなる絶縁層３２を半導体基板１の他方の主面１ｂ上に形成する。このとき図１（ｅ）に示されたように、絶縁層３２の厚さ寸法Ｔ２が、充填部４の突出高さ寸法Ｔ１よりも小さくなるように絶縁層３２を形成する。本実施形態では、厚さ寸法Ｔ２が３μｍとなるように絶縁層３２を形成する。
【００１４】
次に、充填部４のうち、前記絶縁層３２から突出した部分が無くなるように加工して、前記充填部４と絶縁層３２の表面を同一の高さとする。この加工工程では、例えば凸部５とこの凸部５の上面と側面に形成された絶縁層３２のうち、半導体基板１の他方の主面１ｂ上の絶縁層３２から突出した部分を研磨して図１（ｆ）の２点鎖線で示された部分を除去する方法が採用できる。
これにより、充填部４は絶縁層３２から露出し、半導体基板１を貫通する貫通電極となり、貫通電極付き半導体基板６が製造できる。
なお、本発明において、充填部４と絶縁層３２が同一な高さとは、必ずしも完全な水平面を意味しない。充填部４のうち、前記絶縁層３２から突出した部分を研磨などの加工をした後において、充填部４の表面が多少ドーム状を呈する場合も含むものである。
【００１５】
本実施形態では、前述したように、半導体基板１の他方の主面１ｂをエッチングし、微細孔２に充填された充填部４が半導体基板１の他方の主面１ｂから突出した状態とした後に、この充填部４の突出高さ寸法Ｔ１よりも小さい厚さ寸法Ｔ２で絶縁層３２を形成する。
この半導体基板１の他方の主面１ｂからの充填部４の突出高さ寸法Ｔ１を５μｍ≦Ｔ１≦２０μｍとし、かつ半導体基板１の他方の主面１ｂに形成する絶縁層３２の厚さ寸法Ｔ２を０．３μｍ≦Ｔ２＜５μｍとすることが好ましい。
半導体基板１の他方の主面１ｂからの充填部４の突出高さ寸法Ｔ１は、更に好ましくは７μｍ≦Ｔ１≦１０μｍである。また絶縁層３２の厚さ寸法Ｔ２は、更に好ましくは１μｍ≦Ｔ２≦３μｍである。
【００１６】
以上により、次の工程にて充填部４のうち、絶縁層３２から突出した部分のみを研磨などの加工を行うことによって、充填部４と絶縁層３２の表面を同一の高さとすることができ、充填部４を絶縁層３２から露出させることができる。このため、絶縁層３２の表面に研磨ムラを生じさせることなく研磨できる。また研磨によって貫通電極となる充填部４の露出表面を平滑とすることも容易である。これにより歩留まり良く貫通電極付き半導体基板６を製造できる。
【００１７】
また、前記したように絶縁層３２の表面に研磨ムラを生じさせることなく研磨できるため、従来のように研磨ムラを考慮して、予め半導体基板１の他方の主面１ｂ上に絶縁層３２を厚く形成する必要が無く、絶縁層３２の厚さ寸法Ｔ２を小さくすることができ、これにより絶縁層３２の形成に係る時間を短縮できる。また材料費の削減が実現できる。
更に、前記したように絶縁層３２の厚さ寸法Ｔ２を小さくできるため、絶縁層３２と半導体基板１との熱膨張係数の差によって熱応力が生じにくい。このため、熱応力によって半導体基板１に反りが生じにくく、精度良く研磨することが可能となる。このため例えば充填部４と絶縁層３２の表面を同一の高さとすることが容易に実現できる。また、研磨によって貫通電極となる充填部４の露出表面を平滑とすることも容易に実現できる。更に、貫通電極付き半導体基板６の製造歩留まりを著しく向上させることができる。
【００１８】
半導体基板１の他方の主面１ｂからの充填部４の突出高さ寸法Ｔ１が５μｍ未満の場合、絶縁層３２の厚さ寸法Ｔ２と接近するため、ムラのない研磨が困難となる。
また、半導体基板１の他方の主面１ｂからの充填部４の突出高さ寸法Ｔ１が２０μｍよりも大きい場合、半導体基板１の他方の主面１ｂのエッチングに要する時間が長くなり、好ましくない。
【００１９】
また、絶縁層３２の厚さ寸法Ｔ２が０．３μｍ未満の場合、絶縁層３２の絶縁耐圧が低い。また、絶縁層３２が剥離しやすく、例えば次の工程にて、充填部４のうち、前記絶縁層３２から突出した部分が無くなるように研磨などの加工を行う際、この突出した部分以外の絶縁層３２が剥離する場合があり、十分な電気絶縁性が安定して得られず、歩留まりが悪くなるため好ましくない。
絶縁層３２の厚さ寸法Ｔ２が５μｍ以上の場合、絶縁層３２と半導体基板１との熱膨張係数の差によって半導体基板１に反りが生じることとなり、好ましくない。
【００２０】
以上の本実施形態の製造方法によって製造された貫通電極付き半導体基板６は、絶縁層３２の表面に研磨ムラがない。また、絶縁層３２と半導体基板１との熱膨張係数の差によって生じる半導体基板１の反りがほとんど無く、貫通電極となる充填部４の露出表面が平滑に研磨されており、高い接続信頼性が実現できる。
【００２１】
［電子装置］
本実施形態の電子装置は、前述した本実施形態の貫通電極付き半導体基板を用いた装置，機器，部品類の総称であり、例えば携帯電話，電子計算機，各種電気通信装置（光通信用も含む），ＩＣカード類など種々存在する。
本実施形態の貫通電極付き半導体基板を用いることによって、電極間の接続信頼性に優れた電子装置が実現できる。また、デバイスの更なる小型化、高機能化が実現できる。
【００２２】
【発明の効果】
以上詳細に説明したように、本発明の貫通電極付き半導体基板の製造方法によれば、半導体基板の他方の主面をエッチングし、微細孔に充填された充填部が半導体基板の他方の主面から突出した状態とした後に、この充填部の突出高さ寸法よりも小さい厚さ寸法で絶縁層を形成することによって、充填部のうち、絶縁層から突出した部分のみの研磨によって、充填部と絶縁層の表面を同一の高さとし、この充填部を他方の主面の表面から露出させて貫通電極とすることができる。
このため、絶縁層の表面に研磨ムラを生じさせることなく研磨できる。また研磨によって貫通電極となる充填部の露出表面を平滑とすることも容易である。これにより歩留まり良く貫通電極付き半導体基板を製造できる。
【００２３】
また絶縁層の表面に研磨ムラを生じさせることなく研磨できるため、研磨ムラを考慮して、予め半導体基板の他方の主面上に絶縁層を厚く形成する必要が無く、絶縁層の厚さ寸法を小さくすることができる。これにより絶縁層の形成に係る時間を短縮できる。また材料費の削減が実現できる。更に、前記したように絶縁層を厚く設ける必要が無いため、絶縁層と半導体基板との熱膨張係数の差によって熱応力が生じにくい。このため、熱応力によって半導体基板に反りが生じにくく、精度良く研磨することが可能となる。このため例えば充填部と絶縁層の表面を同一の高さとすることが容易に実現できる。また、貫通電極付き半導体基板の製造歩留まりを著しく向上させることができる。
【００２４】
本発明の貫通電極付き半導体基板は、前記した本発明の方法により製造されたものであり、絶縁層の表面に研磨ムラがない。また、絶縁層と半導体基板との熱膨張係数の差によって生じる半導体基板の反りがほとんど無く、貫通電極となる充填部の露出表面が平滑に研磨されており、高い接続信頼性が実現できる。
【００２５】
また、本発明の電子装置は、前記本発明の貫通電極付き半導体基板を有するものであり、電極間の接続信頼性に優れた電気特性が実現できる。また、デバイスの更なる小型化、高機能化が実現できる。
【図面の簡単な説明】
【図１】本実施形態の貫通電極付き半導体基板の製造方法の一例を工程順に示す断面図である。
【図２】貫通電極付き半導体基板の要部断面図である。
【図３】従来の貫通電極付き半導体基板の製造方法の一例を工程順に示す断面図である。
【符号の説明】
１‥‥半導体基板、１ａ‥‥半導体基板の一方の主面、１ｂ‥‥半導体基板の他方の主面、２‥‥微細孔、４‥‥充填部、５‥‥凸部、６‥‥貫通電極付き半導体基板、３１，３２‥‥絶縁層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor substrate having a through electrode that can be suitably used as a wiring for an electronic device or an optical device, or a wiring layer when the devices are stacked and welded, and a semiconductor substrate with a through electrode manufactured by the method. .
[0002]
[Prior art]
When a semiconductor substrate is mounted inside a device in a stacked state, by providing a through-electrode on this semiconductor substrate, it is possible to reduce the space for wiring between the electrodes, and to reduce the size and function of electronic devices and optical devices. Can be realized.
FIG. 2 is a cross-sectional view illustrating an example of the through electrode formed on the semiconductor substrate 11. The through electrode is a material in which a conductive substance 14 such as a metal is filled in a fine hole 12 formed to penetrate two main surfaces of a semiconductor substrate 11 made of silicon or the like.
[0003]
FIG. 3 is a cross-sectional view showing an example of a conventional method for manufacturing a semiconductor substrate with through electrodes in the order of steps (Japanese Patent Application No. 2002-324135).
First, as shown in FIG. 3A, a non-penetrating fine hole 102 opened only on one main surface 101a of the semiconductor substrate 101 is formed. Next, as shown in FIG. 3B, an insulating layer 131 is formed on the inner wall of the fine hole 102 and the two main surfaces 101a and 101b of the semiconductor substrate 101. Then, as shown in FIG. 3C, the conductive material such as a metal is filled in the fine holes 102 and solidified to form a filling portion 104.
Next, as shown in FIG. 3D, the other main surface 101b of the semiconductor substrate 101 is etched to remove the two-dot chain line portion, and the filling portion 104 is removed from the other main surface 101b of the semiconductor substrate 101. It is in a state of protruding about 5 μm. Then, as shown in FIG. 3E, an insulating layer 132 is formed on the other main surface 101b of the semiconductor substrate 101 so as to be thicker than the protruding height of the filling portion 104. Usually, the thickness of the insulating layer 132 is about 6 μm.
Thereafter, the entire surface of the insulating layer 132 is polished to remove the two-dot chain line as shown in FIG. 3F, exposing the conductive material 104 to form a through electrode.
[0004]
[Problems to be solved by the invention]
In the above-described conventional method, as shown in FIG. 3F, the entire surface of the insulating layer 132 including the portion of the filling portion 104 protruding from the other main surface 101b of the semiconductor substrate 101 is polished. Polishing unevenness easily occurs on the surface. Therefore, in consideration of polishing unevenness, it is necessary to previously form the insulating layer 132 on the other main surface of the semiconductor substrate 101 as thick as about 6 μm (FIG. 3E).
For example, when the insulating layer 132 is formed by a CVD method or the like, the process time needs to be increased in order to increase the thickness of the insulating layer 132. In addition, the material cost of the insulating layer 132 increases, and the manufacturing cost increases.
Furthermore, as the insulating layer 132 is thicker, the semiconductor substrate 101 is likely to be warped due to a difference in thermal expansion coefficient between the insulating layer 132 and the semiconductor substrate 101, and it is difficult to accurately polish the insulating layer 132. For this reason, the yield of the semiconductor substrate with a through electrode is greatly reduced.
[0005]
An object of the present invention has been made in view of the above circumstances. That is, the time required for forming the insulating layer can be shortened and the material cost can be reduced, the production can be performed with high yield, and the semiconductor substrate is hardly warped due to the difference in thermal expansion coefficient between the insulating layer and the semiconductor substrate. It is an object of the present invention to provide a manufacturing method capable of manufacturing a semiconductor substrate with a through electrode on which an insulating layer having no unevenness is formed, a semiconductor substrate with a through electrode manufactured by the method, and an electronic device using the same.
[0006]
[Means for Solving the Problems]
The invention according to claim 1 includes a step of forming a filling portion by filling a conductive substance in the fine holes of a semiconductor substrate having fine holes opened only on one main surface, and forming the other main surface of the semiconductor substrate. Etching to make the filling portion protrude from the other main surface of the semiconductor substrate; and, on the other main surface of the semiconductor substrate after etching, a protrusion height dimension of the filling portion from the other main surface. Forming an insulating layer with a smaller thickness dimension, and processing the filling portion so as to eliminate a portion protruding from the insulating layer so that the surface of the filling portion and the surface of the insulating layer have the same height. And a method for manufacturing a semiconductor substrate with a through electrode.
Invention, in the step of etching the other main surface of the semiconductor substrate, the projecting height dimension T 1 of the filling part of the other main surface of the semiconductor substrate is 5μm ≦ T 1 ≦ 20μm according to claim 2 a state at the step of forming the insulating layer, the semiconductor substrate on the other on the main surface after the etching, the insulating layer so that the thickness dimension T 2 of the insulating layer is 0.3μm ≦ T 2 <5μm The method for manufacturing a semiconductor substrate with through electrodes according to claim 1, wherein the semiconductor substrate is formed.
According to a third aspect of the present invention, there is provided a semiconductor substrate with a through electrode manufactured by the method according to the first or second aspect.
According to a fourth aspect of the present invention, there is provided an electronic device including the semiconductor substrate according to the third aspect.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
[Method of manufacturing semiconductor substrate with through electrode, semiconductor substrate with through electrode]
FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor substrate with through electrodes according to the present embodiment in the order of steps.
First, a semiconductor substrate 1 having a non-penetrating fine hole 2 opened only on one main surface 1a is prepared by the following method.
A silicon substrate having a thickness of 350 μm is used as the semiconductor substrate 1, and a diameter of 50 μm and a depth of 50 μm are formed on one main surface 1 a of the semiconductor substrate 1 by a method using a DRIE method (DRIE: Deep-Reactive Ion Etching). Form micropores 2 of about 300 μm. Here, the method using the DRIE method means that sulfur hexafluoride (SF 6 ) is used as an etching gas, and etching by high-density plasma and passivation film formation on a substrate wall surface are alternately performed (Bosch process). In this method, the semiconductor substrate 1 is deeply etched to form fine holes 2 in one main surface 1a of the semiconductor substrate 1.
Here, in the present embodiment, of the two main surfaces of the semiconductor substrate 1, the main surface where the non-penetrating fine holes 2 are open is defined as one main surface 1 a, and the main surface where the fine holes 2 are not open Is referred to as the other main surface 1b. FIG. 1 is exaggeratedly drawn, and the dimensional ratios of the semiconductor substrate 1, the thickness of each layer, the fine holes 2, and the like do not match the actual ones.
[0008]
Although a silicon substrate is used as the semiconductor substrate 1, for example, a substrate made of a semiconductor material such as gallium arsenide (GaAs), an organic material such as an epoxy resin or glass, and a substrate made of a semiconductor material are integrally laminated. It is also possible to adopt a modified version. The thickness of the semiconductor substrate 1 can be about 50 μm to 1 mm.
The diameter of the fine hole 2 is about 5 μm to 200 μm, and the depth is appropriately set according to the thickness of the semiconductor substrate 1 if it does not penetrate the semiconductor substrate 1. The cross-sectional shape (shape of a cross-section perpendicular to the axial direction) of the fine hole 2 may be any shape such as a circle, an ellipse, a triangle, and a rectangle (including a square).
As a method of forming the fine holes 2, in addition to the method using the above-described DRIE method, a wet etching method using an etching solution such as an aqueous solution of potassium hydroxide (KOH), a machining method using a micro drill, a photo-induced electrolytic method A polishing method or the like can also be adopted.
[0009]
Next, as shown in FIG. 1B, the semiconductor substrate 1 is thermally oxidized to form an insulating layer made of silicon oxide (SiO 2 ) on the inner wall of the fine hole 2 and the two main surfaces of the semiconductor substrate 1. 31 are formed. Here, although the insulating layer is drawn thick in FIG. 1, it is actually extremely thin.
As a method of forming the insulating layer 31 on the inner wall of the fine hole 2 and on the two main surfaces of the semiconductor substrate 1, besides the thermal oxidation treatment, a method of forming silicon oxide (SiO 2 ) by a plasma CVD method, or a method of forming an insulating resin. A method of coating to form a resin layer can also be applied.
[0010]
Then, as shown in FIG. 1 (c), a gold-tin alloy (Au (80% by weight) -Sn (20% by weight)) is used as a conductive material in the fine holes 2 by a molten metal suction method or the like. Fill.
An example of the molten metal suction method is shown below. A molten metal bath containing a conductive material of a gold-tin alloy (Au (80% by weight) -Sn (20% by weight)) in a molten state and the semiconductor substrate 1 are accommodated in a reduced pressure chamber. Reduce the pressure. While maintaining the reduced pressure state, the semiconductor substrate 1 is immersed in a molten conductive material in a molten metal bath. The immersion of the semiconductor substrate 1 in the molten conductive material is performed by immersing the entire semiconductor substrate 1 in the molten conductive material such that one main surface 1a is on the upper side and one main surface 1a is not exposed. Then, by pressurizing the inside of the decompression chamber, the conductive material in a molten state can flow into and fill the micropores 2 formed in the semiconductor substrate 1.
Then, by pulling up the semiconductor substrate 1 from the molten conductive material and cooling and solidifying the conductive material, the gold-tin alloy (Au (80% by weight) -Sn (20% by weight) %)). The conductive material filled and solidified in the fine holes 2 becomes the filling portion 4.
[0011]
The conductive substance is not particularly limited, and may be a gold-tin alloy having a different composition, a metal such as tin (Sn) or indium (In), a tin-lead (Sn-Pb) alloy, or tin (Sn). , Lead (Pb), gold (Au), indium (In), and aluminum (Al) based solder.
In addition to the above-described method, a method of filling the fine holes 2 with a conductive material may be a method of transferring a paste-like conductive material to the vicinity of the fine holes 2 by a printing method, further reducing the pressure, and filling the inside of the fine holes 2. , Plating method and the like can be applied.
[0012]
Next, after polishing the other main surface 1b of the semiconductor substrate 1 (FIG. 1C) in which the filling portion 4 made of a conductive substance is filled in the micropores 2 to some extent, sulfur hexafluoride (SF 6 ), The silicon (Si) portion of the other main surface 1b of the semiconductor substrate 1 is etched. As described above, the portion indicated by the two-dot chain line in FIG. 1D is removed, and the filling portion 4 filled in the fine hole 2 is made to protrude from the other main surface 1b of the semiconductor substrate 1.
In the present embodiment, the protrusion height T1 of the filling portion 4 from the other main surface 1b of the semiconductor substrate 1 is 8 μm. Further, a portion of the filling portion 4 and the insulating layer 31 that protrudes from the other main surface 1b of the semiconductor substrate 1 is referred to as a convex portion 5.
In the step of etching the other main surface 1b of the semiconductor substrate 1, first, the insulating layer 31 on the other main surface 1b of the semiconductor substrate 1 is removed by etching, and then sulfur hexafluoride (SF 6 ) is removed. A method of etching a silicon (Si) portion of the other main surface 1b of the semiconductor substrate 1 by the used dry etching may be used.
[0013]
Then, an insulating layer 32 made of silicon oxide (SiO 2 ) is formed on the other main surface 1 b of the semiconductor substrate 1 by plasma CVD using tetraethoxysilane (TEOS) as a raw material. As this time shown in FIG. 1 (e), the thickness T 2 of the insulating layer 32 to form the insulating layer 32 to be smaller than the projecting height dimension T 1 of the filling unit 4. In the present embodiment, the thickness T 2 is an insulating layer 32 such that the 3 [mu] m.
[0014]
Next, the filling portion 4 is processed so that a portion protruding from the insulating layer 32 is eliminated, so that the surface of the filling portion 4 and the surface of the insulating layer 32 have the same height. In this processing step, for example, among the protrusions 5 and the insulating layer 32 formed on the upper surface and side surfaces of the protrusions 5, a portion protruding from the insulating layer 32 on the other main surface 1 b of the semiconductor substrate 1 is polished. A method of removing a portion shown by a two-dot chain line in FIG.
Thereby, the filling portion 4 is exposed from the insulating layer 32 and becomes a through electrode penetrating the semiconductor substrate 1, so that the semiconductor substrate 6 with the through electrode can be manufactured.
In the present invention, the same height of the filling portion 4 and the insulating layer 32 does not necessarily mean a complete horizontal plane. After the portion of the filling portion 4 protruding from the insulating layer 32 is processed by polishing or the like, the surface of the filling portion 4 may have a somewhat dome shape.
[0015]
In the present embodiment, as described above, after the other main surface 1b of the semiconductor substrate 1 is etched to make the filling portion 4 filled in the micro holes 2 project from the other main surface 1b of the semiconductor substrate 1, , an insulating layer 32 with a small thickness dimension T 2 than the projecting height dimension T 1 of the filling unit 4.
The height T 1 of the protrusion of the filling portion 4 from the other main surface 1 b of the semiconductor substrate 1 is set to 5 μm ≦ T 1 ≦ 20 μm, and the thickness of the insulating layer 32 formed on the other main surface 1 b of the semiconductor substrate 1 it is preferable that the dimension T 2 and 0.3μm ≦ T 2 <5μm.
The protruding height T 1 of the filling portion 4 from the other main surface 1 b of the semiconductor substrate 1 is more preferably 7 μm ≦ T 1 ≦ 10 μm. The thickness T 2 of the insulating layer 32, more preferably from 1μm ≦ T 2 ≦ 3μm.
[0016]
As described above, in the next step, only the portion of the filling portion 4 protruding from the insulating layer 32 is subjected to processing such as polishing, so that the surface of the filling portion 4 and the surface of the insulating layer 32 can be made the same height. The filling portion 4 can be exposed from the insulating layer 32. Therefore, polishing can be performed without causing polishing unevenness on the surface of the insulating layer 32. Also, it is easy to smooth the exposed surface of the filling portion 4 to be a through electrode by polishing. As a result, the semiconductor substrate 6 with through electrodes can be manufactured with good yield.
[0017]
In addition, since the polishing can be performed without causing polishing unevenness on the surface of the insulating layer 32 as described above, the insulating layer 32 is previously formed on the other main surface 1b of the semiconductor substrate 1 in consideration of the polishing unevenness as in the related art. thick there is no need to form, it is possible to reduce the thickness T 2 of the insulating layer 32, thereby shortening the time required for the formation of the insulating layer 32. In addition, material costs can be reduced.
Furthermore, since it is possible to reduce the thickness dimension T 2 of the insulating layer 32 as described above, thermal stress is less likely to occur by the difference in thermal expansion coefficient between the insulating layer 32 and the semiconductor substrate 1. Therefore, the semiconductor substrate 1 is hardly warped due to thermal stress, and can be polished with high accuracy. Therefore, for example, it is easy to realize that the surface of the filling portion 4 and the surface of the insulating layer 32 have the same height. In addition, it is possible to easily realize that the exposed surface of the filling portion 4 serving as the through electrode is smoothened by polishing. Furthermore, the production yield of the semiconductor substrate 6 with the through electrodes can be significantly improved.
[0018]
If the other projecting height T 1 of the filling unit 4 from the main surface 1b of the semiconductor substrate 1 is less than 5 [mu] m, for accessing the thickness T 2 of the insulating layer 32, it is difficult to polish without unevenness.
Also, when the other of the projecting height T 1 of the filling unit 4 from the main surface 1b of the semiconductor substrate 1 is larger than 20 [mu] m, the time becomes longer required for etching the other main surface 1b of the semiconductor substrate 1, is not preferred .
[0019]
Further, the thickness T 2 of the insulating layer 32 is of less than 0.3 [mu] m, the breakdown voltage of the insulating layer 32 is low. In addition, when the insulating layer 32 is easily peeled off, for example, in the next step, when performing processing such as polishing so that the portion of the filling portion 4 that protrudes from the insulating layer 32 is eliminated, insulating portions other than the protruding portion are removed. In some cases, the layer 32 is peeled off, and sufficient electrical insulation cannot be stably obtained, and the yield is unfavorably reduced.
If the thickness T 2 of the insulating layer 32 is not less than 5 [mu] m, it will be warped to the semiconductor substrate 1 by the difference in thermal expansion coefficient between the insulating layer 32 and the semiconductor substrate 1, which is not preferable.
[0020]
The semiconductor substrate 6 with through electrodes manufactured by the manufacturing method of the present embodiment described above has no polishing unevenness on the surface of the insulating layer 32. Further, the semiconductor substrate 1 hardly warps due to the difference in thermal expansion coefficient between the insulating layer 32 and the semiconductor substrate 1, and the exposed surface of the filling portion 4 serving as a through electrode is polished smoothly, so that high connection reliability is obtained. realizable.
[0021]
[Electronic device]
The electronic device of the present embodiment is a general term for devices, devices, and components using the above-described semiconductor substrate with a through electrode of the present embodiment. For example, mobile phones, electronic computers, various telecommunication devices (including optical communication devices) ) And IC cards.
By using the semiconductor substrate with a through electrode of the present embodiment, an electronic device having excellent connection reliability between electrodes can be realized. Further, further miniaturization and higher functionality of the device can be realized.
[0022]
【The invention's effect】
As described in detail above, according to the method for manufacturing a semiconductor substrate with through electrodes of the present invention, the other main surface of the semiconductor substrate is etched, and the filled portion filled in the fine holes is formed on the other main surface of the semiconductor substrate. By forming the insulating layer with a thickness smaller than the height of the protrusion of the filling portion after the protrusion from the filling portion, by polishing only the portion of the filling portion that protrudes from the insulating layer, The surface of the insulating layer may have the same height, and the filling portion may be exposed from the surface of the other main surface to form a through electrode.
Therefore, polishing can be performed without causing uneven polishing on the surface of the insulating layer. In addition, it is easy to smooth the exposed surface of the filling portion that becomes a through electrode by polishing. Thereby, a semiconductor substrate with a through electrode can be manufactured with good yield.
[0023]
In addition, since polishing can be performed without causing polishing unevenness on the surface of the insulating layer, it is not necessary to previously form a thick insulating layer on the other main surface of the semiconductor substrate in consideration of polishing unevenness. Can be reduced. Thus, the time required for forming the insulating layer can be reduced. In addition, material costs can be reduced. Further, since there is no need to provide a thick insulating layer as described above, thermal stress is less likely to occur due to a difference in thermal expansion coefficient between the insulating layer and the semiconductor substrate. Therefore, the semiconductor substrate is unlikely to warp due to thermal stress, and can be polished with high accuracy. Therefore, for example, it is easy to realize that the surface of the filling portion and the surface of the insulating layer have the same height. Further, the production yield of the semiconductor substrate with the through electrode can be significantly improved.
[0024]
The semiconductor substrate with a through electrode according to the present invention is manufactured by the method of the present invention described above, and has no polishing unevenness on the surface of the insulating layer. In addition, the semiconductor substrate hardly warps due to the difference in thermal expansion coefficient between the insulating layer and the semiconductor substrate, and the exposed surface of the filling portion serving as a through electrode is polished smoothly, so that high connection reliability can be realized.
[0025]
Further, an electronic device according to the present invention includes the semiconductor substrate with a through electrode according to the present invention, and can realize electrical characteristics excellent in connection reliability between electrodes. Further, further miniaturization and higher functionality of the device can be realized.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor substrate with through electrodes of the present embodiment in the order of steps.
FIG. 2 is a sectional view of a main part of a semiconductor substrate with a through electrode.
FIG. 3 is a cross-sectional view illustrating an example of a conventional method for manufacturing a semiconductor substrate with through electrodes, in the order of steps.
[Explanation of symbols]
1 {semiconductor substrate, 1a} one main surface of semiconductor substrate, 1b {other main surface of semiconductor substrate, 2} micropore, 4 filling portion, 5 convex portion, 6 through Semiconductor substrate with electrodes, 31, 32 ‥‥ insulating layer

Claims (4)

一方の主面のみに開口した微細孔を有する半導体基板の微細孔内に導電性物質を充填して充填部を形成する工程と、
半導体基板の他方の主面をエッチングして、充填部が半導体基板の他方の主面から突出した状態とする工程と、
エッチング後の半導体基板の他方の主面上に、該他方の主面からの充填部の突出高さ寸法よりも小さい厚さ寸法で絶縁層を形成する工程と、
充填部のうち、前記絶縁層から突出した部分が無くなるように加工して、前記充填部と絶縁層の表面を同一の高さとする工程とを少なくとも有することを特徴とする貫通電極付き半導体基板の製造方法。A step of forming a filled portion by filling a conductive substance into the fine holes of a semiconductor substrate having fine holes opened only on one main surface,
A step of etching the other main surface of the semiconductor substrate so that the filling portion protrudes from the other main surface of the semiconductor substrate;
Forming an insulating layer on the other main surface of the semiconductor substrate after the etching with a thickness smaller than a protrusion height of the filling portion from the other main surface;
Of the filling portion, at least a step of processing the filling portion and the surface of the insulating layer to have the same height so that a portion protruding from the insulating layer is eliminated. Production method. 前記半導体基板の他方の主面をエッチングする工程にて、半導体基板の他方の主面からの充填部の突出高さ寸法Ｔ１が５μｍ≦Ｔ１≦２０μｍとなる状態とし、前記絶縁層を形成する工程にて、エッチング後の半導体基板の他方の主面上に、絶縁層の厚さ寸法Ｔ２が０．３μｍ≦Ｔ２＜５μｍとなるように絶縁層を形成することを特徴とする請求項１に記載の貫通電極付き半導体基板の製造方法。In the step of etching the other main surface of the semiconductor substrate, the projecting height dimension T 1 of the filling portion from the other main surface of the semiconductor substrate is set to 5 μm ≦ T 1 ≦ 20 μm, and the insulating layer is formed. claims in the step of the semiconductor substrate on the other on the main surface after the etching, the thickness T 2 of the insulating layer and forming an insulating layer so as to 0.3μm ≦ T 2 <5μm Item 2. The method for manufacturing a semiconductor substrate with a through electrode according to Item 1. 請求項１又は２に記載の方法で製造されたことを特徴とする貫通電極付き半導体基板。A semiconductor substrate with a through electrode, manufactured by the method according to claim 1. 請求項３に記載の半導体基板を有することを特徴とする電子装置。An electronic device comprising the semiconductor substrate according to claim 3.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014152399A (en) * 2013-02-12 2014-08-25 Astrium Gmbh Method for operating electrolytic cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014152399A (en) * 2013-02-12 2014-08-25 Astrium Gmbh Method for operating electrolytic cell

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