JP2004221191A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device by which a residue generated when a wiring groove is formed in a dual damascene method can be reduced. <P>SOLUTION: The bottom of a groove 12a formed at when a machining is stopped is irradiated with the plasma of a gas containing fluorine by stopping the machining once without forming the wiring groove 12 to an interlayer insulating film 3 by one-time machining. Accordingly, the residue 15 composed of an Si compound or the like existing on the bottom of the groove 12a at the point of time is removed. The residue is removed in this manner, and the wiring groove 12 is formed by machining. The residue can be generated by further machining in this case, but an SiC film 2 is formed generally between the film 3 and a Cu wiring 1 positioned at the lower section of the film 3 by the dual damascene method, and the residue is removed when the film 2 is machined. Consequently, the lowering of a yield, the increase of the resistivity of the wiring, the deterioration of a reliability or the like can be avoided. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device employing a dual damascene method.
[0002]
[Prior art]
It is known that with the miniaturization of semiconductor integrated circuits, the RC delay of wiring is a main factor limiting the device speed.
For this reason, recently, Cu is mainly used as a wiring material. However, it is difficult to transfer the wiring pattern to Cu itself. For this reason, in forming a Cu wiring, a damascene method in which a wiring groove (trench) pattern is transferred to an interlayer insulating film and Cu is buried therein to form a wiring pattern is effective. Further, the damascene method is classified into a single damascene method in which Cu of a groove and Cu of a via (Via) are separately formed, and a dual damascene method in which a groove and a via are simultaneously formed.
[0003]
On the other hand, as for the material of the interlayer insulating film, a low dielectric constant film having a lower dielectric constant than a conventional oxide film is used in order to solve the problem of RC delay. The material of the low dielectric constant film is roughly classified into two types: an inorganic material and an organic material. These are generally used properly to satisfy the requirements of each device characteristic.
[0004]
When an organic low-dielectric-constant film is used as an interlayer insulating film, an interlayer structure generally uses a pre-groove hard mask method. Here, the pre-groove hard mask method means that a hard mask pattern for forming a wiring groove pattern is formed on an interlayer insulating film in advance, and via patterning is performed directly on a step of the wiring groove pattern. In this method, via processing and wiring groove processing of an interlayer insulating film are sequentially performed to form a dual damascene structure.
[0005]
It is generally known that the etching of an organic low dielectric constant film is performed using a mixed gas of N ₂ gas and H ₂ gas, NH ₃ gas, or a mixed gas of these three gases. When a wiring groove and a via hole are formed in a single organic low dielectric constant film by employing the dual damascene method, half etching is performed on the organic low dielectric constant film in forming the wiring groove. Specifically, after a via hole is formed halfway through the organic low dielectric constant film by etching, the remainder of the via hole and the wiring groove are collectively formed.
[0006]
[Patent Document 1]
JP 2001-118825 A
[Problems to be solved by the invention]
In the dual damascene method as described above, when the Si contained in the adhesive film formed thin between the organic low dielectric constant film and the hard mask and the Si in the hard mask are subjected to sputtering of the hard mask, Si compounds are attached to the organic low-k film, and when the organic low-k film is etched, depots (Si compounds) attached to the inner wall of the chamber fly over the organic low-k film. Sometimes. However, in the above-mentioned gas for etching the organic low dielectric constant film (a mixed gas of N ₂ gas and H ₂ gas, NH ₃ gas or a mixed gas of these three gases), it is necessary to remove the Si compound. Can not. Therefore, at the time of etching for forming a groove and a via hole in the organic low dielectric constant film, the Si compound functions as a mask, and a residue is generated at the bottom of the finally formed groove.
[0008]
FIG. 12 is a cross-sectional view showing a state in the middle of a conventional method for manufacturing a semiconductor device. FIG. 12 shows a state in which a via hole and a wiring groove have been formed by a dual damascene method of a hard groove method using a leading groove. In this state, the SiC film 102, the organic low dielectric constant film 103, the SiC film 104, and the SiO ₂ film 105 are stacked on the Cu wiring 101, and a via hole is formed below the SiC film 102 and the organic low dielectric constant film 103. A wiring groove is formed in the upper part of the organic low dielectric constant film 103, the SiC film 104 and the SiO ₂ film 105. However, in the conventional manufacturing method, as shown in FIG. 12, when a via hole and a wiring groove are formed, a residue 115 is generated at the bottom of the wiring groove. When such a residue 115 is present, the yield is reduced, the resistivity of the wiring is increased, and the reliability is reduced.
[0009]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing residues generated when forming a wiring groove in a dual damascene method.
[0010]
[Means for Solving the Problems]
As a result of intensive studies, the inventor of the present application has come up with the following aspects of the invention.
[0011]
A method for manufacturing a semiconductor device according to the present invention is directed to a method for manufacturing a semiconductor device in which wiring is formed by a dual damascene method. In the present manufacturing method, first, a hole shallower than the thickness of the interlayer insulating film is formed in the interlayer insulating film by processing an interlayer insulating film made of an organic dielectric using a mask for a via hole. Next, a wiring groove is formed in the interlayer insulating film by processing the interlayer insulating film using a wiring groove mask, and a via hole is formed by penetrating the hole to a lower layer. Next, a wiring material is embedded in the wiring grooves and the via holes. In the present manufacturing method, when forming the wiring groove, first, the interlayer insulating film is processed using the mask for the wiring groove, thereby forming a groove in the interlayer insulating film. A plasma of a gas containing fluorine is irradiated toward the bottom of the groove by using a mask for use. Thereafter, the interlayer insulating film is processed using the wiring groove mask, so that the depth of the groove is increased to form the wiring groove.
[0012]
In the present invention, in forming the wiring groove, instead of forming the wiring groove in the interlayer insulating film by one processing, the processing is temporarily stopped, and the fluorine is directed toward the bottom of the groove formed at that time. Is irradiated with a plasma of a gas containing As a result, the residue of the Si compound or the like existing at the bottom of the groove at that time is removed. After removing the residue in this manner, further processing is performed to form a wiring groove. At this time, residues may be generated by further processing. However, in general, in the dual damascene method, an insulating film is formed between an interlayer insulating film and a wiring layer located thereunder. The residue is removed. Therefore, it is possible to avoid a decrease in yield, an increase in wiring resistivity, a decrease in reliability, and the like.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings.
[0014]
(1st Embodiment)
First, a first embodiment of the present invention will be described. 1 to 3 are sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. In the present embodiment, a semiconductor device is manufactured by a dual-damascene method using a hard-groove method.
[0015]
First, as shown in FIG. 1A, an SiC film 2 is formed on a Cu wiring 1 as an etching stopper film. The thickness of the SiC film 2 is, for example, 50 nm. Next, an organic low dielectric constant film (organic dielectric film) 3 is formed on the SiC film 2 as an interlayer insulating film. The thickness of the organic low dielectric constant film 3 is, for example, 450 nm. The raw materials of the organic low dielectric constant film 3 include, for example, SiLK (registered trademark), organic SOG, amorphous carbon fluoride and polytetrafluoroethylene (such as Teflon (registered trademark) of DuPont) and polyaryl manufactured by Dow Chemical Company. Ether (FLARE (registered trademark) of Honeywell Electronic Materials Japan, Inc.) can be used.
[0016]
Next, on the organic low dielectric constant film 3, an SiC film 4 is formed as a first hard mask, and further, an SiO ₂ film 5 is formed as a _second hard mask. The thicknesses of the SiC film 4 and the SiO ₂ film 5 are, for example, 50 nm and 100 nm, respectively. After that, a photosensitive resist is applied on the SiO ₂ film 5, and the resist is exposed and developed to form a resist mask 8a having a pattern of wiring grooves (trench).
[0017]
Subsequently, as shown in FIG. 1B, the SiO ₂ film 5 is etched using the resist mask 8a as a mask. This etching is, for _{example, C 4 F 6: 5~40sccm,} O 2: 20~70sccm, Ar: 50~1000sccm, Pressure: 1.33~13.3Pa (10~100mTorr), RF power:: 100 to 1000 W Under the conditions described above, using a reactive ion etching apparatus.
[0018]
Next, as shown in FIG. 1C, a photosensitive resist is applied to the entire surface, and is exposed and developed to form a resist mask 11a having a pattern of via holes.
[0019]
Next, as shown in FIG. 2A, the SiO ₂ film 5 and the SiC film 4 are etched using the resist mask 11a as a mask. This etching is performed, for example, under the following conditions: CF ₄ : 50 to 200 sccm, Ar: 0 to 500 sccm, pressure: 2.66 to 26.6 Pa (20 to 200 mTorr), RF power supply: 100 to 1000 W. This is performed using an etching apparatus. By this etching, the SiC film 4 is patterned into a planar shape of the via hole.
[0020]
Thereafter, as shown in FIG. 2B, using the two-layer hard mask as a mask, the organic low dielectric constant film 3 is etched by about 200 nm, and at the same time, the resist mask 11a is removed. This etching is, for _example, NH 3: 50 to 300, pressure: 2.66~20Pa (20~150mTorr), RF power:: Under 100~800W conditions, carried out using a reactive ion etching apparatus. The hole formed in the organic low dielectric constant film 3 by this etching becomes a part of the via hole.
[0021]
Subsequently, as shown in FIG. 2C, the SiC film 4 is etched using the SiO ₂ film 5 as a mask. This etching is performed, for example, under the following conditions: CHF ₃ : 5 to ₃₀ sccm, N ₂ : 0 to 50 sccm, O ₂ : 0 to 100 sccm, pressure: 1.33 to 13.3 Pa (10 to 100 mTorr), and RF power supply power: 50 to 200 W It is performed under a condition using a reactive ion etching apparatus. By this etching, the SiC film 4 is patterned into a planar shape of the wiring groove. Further, the thickness of the SiO ₂ film 5 decreases.
[0022]
Next, as shown in FIG. 3A, the organic low dielectric constant film 3 as an interlayer insulating film is etched using the SiO ₂ film 5 and the SiC film 4 as a mask. This etching is performed, for example, under the following conditions: NH ₃ : 50 to 200 sccm, Ar: 0 to 300 sccm, pressure: 26.6 to 106 Pa (200 to 800 mTorr), and RF power supply power: 50 to 400 W. This is performed using
[0023]
However, as shown in FIG. 3A, this etching is performed before the depth of the groove 12a formed by etching reaches the thickness (design value) of the wiring to be formed, for example, the depth of the groove 12a. Stops when it reaches about half the thickness of the wiring. For example, when a wiring having a thickness of 200 nm is to be formed, this etching may be stopped when the depth of the groove 12a becomes about 100 nm. In addition, this etching deepens the holes formed in the organic low dielectric constant film 3 in the previous step. This hole may reach the SiC film 2 to form the via hole 13 as shown in FIG. 3A, or may not reach the SiC film 2.
[0024]
After this etching is performed, as shown in FIG. 3A, a residue 15 containing a Si compound exists at the bottom of the groove 12a.
[0025]
Next, the residue 15 is removed by irradiating the bottom of the groove 12a with a plasma of a gas containing F (fluorine). This process is performed, for example, under the conditions of CH ₂ F ₂ : 5 to 50 sccm, O ₂ : 5 to 50 sccm, pressure: 0.665 to 13.3 Pa (5 to 100 mTorr), and RF power source power: 50 to 200 W. This is performed using a reactive ion etching apparatus.
[0026]
Thereafter, as shown in FIG. 3B, the organic low dielectric constant film 3 is etched again using the SiO ₂ film 5 and the SiC film 4 as a mask. This etching is performed, for example, under the following conditions: NH ₃ : 50 to 200 sccm, Ar: 0 to 300 sccm, pressure: 26.6 to 106 Pa (200 to 800 mTorr), and RF power supply power: 50 to 400 W. This is performed using By this etching, the wiring groove 12 is formed by increasing the depth of the groove 12a. If the holes formed in the organic low dielectric constant film 3 have not reached the SiC film 2 after the etching before removing the residue 15, the holes reach the SiC film 2 by this etching.
[0027]
After this etching is performed, although not shown, a residue containing a Si compound exists at the bottom of the wiring groove 12.
[0028]
Subsequently, the SiC film 2 is etched using the SiO ₂ film 5, the SiC film 4, and the organic low dielectric constant film 3 as a mask. As a result, the shape of the dual damascene is completed. This etching is, for _{example, CH 2 F 2: 5~50sccm,} O 2: 5~50sccm, N 2: 10~100sccm, Pressure: 0.665~13.3Pa (5~100mTorr), RF power:: 50 This is performed under a condition of 2000 W using a reactive ion etching apparatus. By this etching, the residue existing at the bottom of the wiring groove 12 is removed.
[0029]
Then, as shown in FIG. 3C, a Cu wiring 14 is buried in the via hole 13 and the wiring groove 12. Thereafter, if necessary, an interlayer insulating film, wiring, and the like are further formed to complete the semiconductor device.
[0030]
FIG. 4 is a cross-sectional view illustrating a structure of a semiconductor device manufactured by applying the present embodiment. In the example shown in FIG. 4, an element isolation region 22 is formed on the surface of the semiconductor substrate 21, and a transistor is formed in an element active region partitioned by the element isolation region 22. The transistor includes a source / drain region 23 formed on a surface of a semiconductor substrate 21, a gate insulating film 24 formed on the semiconductor substrate 21, a gate electrode 25 formed on the gate insulating film 24, and a gate electrode 25. Is provided on the side of the side wall. Then, an interlayer insulating film 27 is formed so as to cover this transistor. A contact plug 28 reaching the source / drain region 23 is embedded in the interlayer insulating film 27. This contact plug 28 corresponds to the Cu wiring 1 in FIGS.
[0031]
Further, an SiC film 29, an interlayer insulating film 30, a SiC film 33, an interlayer insulating film 34, and a SiC film 37 are sequentially stacked on the entire surface. The via plug 31, the wiring 32, the via plug 35, and the wiring 36 are embedded in these films. The via plugs 31 and 35 correspond to the portions existing in the via holes 13 of the Cu wiring 14 in FIG. 3C, and the wires 32 and 36 correspond to the portions existing in the wiring grooves 12. Thus, in the example shown in FIG. 4, at least two layers of multilayer wiring are formed by the manufacturing method according to the above-described embodiment.
[0032]
As described above, according to the manufacturing method according to the present embodiment, when the via hole and the wiring groove are formed in the single organic low-dielectric-constant film 3 by the dual damascene method, the formation of the wiring groove is performed during the etching. Since the Si compound is removed by the treatment using the plasma of the gas containing F, the residue 15 does not exist when the via hole and the wiring groove are formed. Therefore, the characteristics of the Cu wiring 14 formed thereafter are stabilized, so that the yield can be improved, the rise in resistivity can be suppressed, and high reliability can be obtained.
[0033]
In addition, even in the conventional manufacturing method, when etching the SiC film after forming the via hole and the wiring groove in the organic low dielectric constant film, some residues are removed. However, since a large amount of residue exists immediately before the etching of the SiC film, a large amount of residue remains, and it is not possible to avoid problems such as a decrease in reliability.
[0034]
(Second embodiment)
Next, a second embodiment of the present invention will be described. The second embodiment is a method suitable for forming a finer pattern. 5 to 9 are sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. Also in the present embodiment, a semiconductor device is manufactured by a dual damascene method using a hard-groove method with a trench.
[0035]
First, as shown in FIG. 5A, an SiC film 2 is formed on a Cu wiring 1 as an etching stopper film. Next, an organic low dielectric constant film 3 is formed on the SiC film 2 as an interlayer insulating film.
[0036]
Next, on the organic low dielectric constant film 3, an SiC film 4 is formed as a first hard mask, and further, an SiO ₂ film 5 is formed as a _second hard mask. Subsequently, an Si ₃ N ₄ film 6 is formed on the SiO ₂ film 5 as a third hard mask. The Si ₃ N ₄ film 6 becomes a film to be etched when forming a hard mask pattern of the wiring groove. Thereafter, an organic BARC (Bottom anti-reflection coating) 7 is formed on the Si ₃ N ₄ film 6 as an anti-reflection film required at the time of patterning. Then, an organic photosensitive resist is applied on the organic BARC 7, and is exposed and developed to form a resist mask 8b on which a wiring groove pattern is formed.
[0037]
Next, as shown in FIG. 5B, the organic BARC 7 is etched using the resist mask 8b as a mask.
[0038]
Next, as shown in FIG. 5C, the Si ₃ N ₄ film is etched using the resist mask 8b and the organic BARC 7 as a mask. As a result, the Si ₃ N ₄ film is patterned into a wiring groove pattern.
[0039]
Subsequently, as shown in FIG. 6A, the resist mask 8b and the organic BARC 7 are removed by ashing. Then, a pattern of a via hole is formed in the organic low dielectric constant film 3 or the like which is an interlayer insulating film. Here, a tri-level technique is used for the pattern of the wiring groove formed in the Si ₃ N ₄ film 6.
[0040]
Specifically, first, as shown in FIG. 6B, a lower resin film (organic film) 9 that fills the steps of the Si ₃ N ₄ film 6 and planarizes it is formed. Next, an SOG (Spin On Glass) film (inorganic film) 10 used as a mask when etching the lower resin film 9 is formed on the lower resin film 9. Subsequently, an organic photosensitive resist is applied on the SOG film 10, and is exposed and developed to form a resist mask (photosensitive resist film) 11b having a pattern of via holes.
[0041]
Next, as shown in FIG. 6C, the SOG film 10 is etched using the resist mask 11b as a mask.
[0042]
Next, as shown in FIG. 7A, using the SOG film 10 as a mask, the lower resin film 9 is etched, and at the same time, the resist mask 11b is removed. In this etching, since the lower resin film 9 is organic like the resist mask 11, their etching selectivity is about 1. Therefore, when the thickness of the resist mask 11 b is significantly larger than the thickness of the lower resin film 9, the resist mask 11 may remain on the SOG film 10 even after the etching of the lower resin film 9 is completed. Therefore, it is desirable that the thickness of the resist mask 11 be equal to or less than the thickness of the lower resin film 9.
[0043]
Subsequently, as shown in FIG. 7B, by using the lower resin film 9 as a mask, the Si ₃ N ₄ film 6, the SiO ₂ film 5, and the SiC film 4 (three-layer hard mask) are etched to form these. The SOG film 10 is removed at the same time as forming a via hole pattern in the film. In this etching, the SOG film 11 can be simultaneously removed by using the condition that the etching selectivity between the SOG film 10 and the three-layer hard mask is about 1. Therefore, when the thickness of the SOG film 10 is significantly larger than the total thickness of the three-layer hard mask, the SOG film 10 may remain even after the etching of the three-layer hard mask is completed. Therefore, the thickness of the SOG film 10 is desirably equal to or less than the total thickness of the Si ₃ N ₄ film 6, the SiO ₂ film 5, and the SiC film 4.
[0044]
Thereafter, as shown in FIG. 7C, the organic low dielectric constant film 3 is etched by about 200 to 400 nm using the three-layer hard mask as a mask, and at the same time, the lower resin film 9 is removed. The hole formed in the organic low dielectric constant film 3 by this etching becomes a part of the via hole.
[0045]
Next, the SiO ₂ film 5 is etched using the Si ₃ N ₄ film 6 exposed by removing the lower resin film 9 as a mask. As a result, as shown in FIG. 8A, a wiring groove pattern is also formed on the SiO ₂ film 5.
[0046]
Next, the SiC film 4 is etched using the Si ₃ N ₄ film 6 and the SiO ₂ film 5 as a mask. As a result, as shown in FIG. 8B, the Si ₃ N ₄ film 6 is removed simultaneously with the formation of the wiring groove pattern in the SiC film 4.
[0047]
Subsequently, the organic low dielectric constant film 3, which is an interlayer insulating film, is etched using the SiO ₂ film 5 and the SiC film 4 as a mask. However, as shown in FIG. 8C, similar to the process shown in FIG. 3A, in this etching, the depth of the groove 12a formed by the etching depends on the thickness (design of the wiring) to be formed. Before reaching the value, for example, when the depth of the groove 12a reaches half of the thickness of the wiring, it stops. For example, when a wiring having a thickness of 200 nm is to be formed, this etching may be stopped when the depth of the groove 12a becomes about 100 nm. In addition, this etching deepens the holes formed in the organic low dielectric constant film 3 in the previous step. This hole may reach the SiC film 2 to form the via hole 13 as shown in FIG. 8C, or may not reach the SiC film 2.
[0048]
After this etching is performed, as shown in FIG. 8C, the residue 15 containing the Si compound exists at the bottom of the groove 12a.
[0049]
Next, similarly to the first embodiment, the residue 15 is removed by irradiating the bottom of the groove 12a with a plasma of a gas containing F.
[0050]
Thereafter, as shown in FIG. 9A, the organic low dielectric constant film 3 is etched again using the SiO ₂ film 5 and the SiC film 4 as a mask. By this etching, the wiring groove 12 is formed by increasing the depth of the groove 12a. If the holes formed in the organic low dielectric constant film 3 have not reached the SiC film 2 after the etching before removing the residue 15, the holes reach the SiC film 2 by this etching.
[0051]
After this etching is performed, although not shown, a residue containing a Si compound exists at the bottom of the wiring groove 12.
[0052]
Subsequently, as shown in FIG. 9B, the SiC film 2 is etched using the SiO ₂ film 5, the SiC film 4, and the organic low dielectric constant film 3 as a mask. As a result, the shape of the dual damascene is completed. Further, the residue existing at the bottom of the wiring groove 12 is removed by this etching.
[0053]
Then, as shown in FIG. 9C, a Cu wiring 14 is buried in the via hole 13 and the wiring groove 12. Thereafter, if necessary, an interlayer insulating film, wiring, and the like are further formed to complete the semiconductor device.
[0054]
According to the second embodiment, the same effects as those of the first embodiment can be obtained. Further, according to the second embodiment, since the patterning is performed using the multilayer resist, it is possible to perform finer processing.
[0055]
FIGS. 10A and 10B are scanning electron microscope (SEM) photographs obtained when the device is actually manufactured based on the second embodiment, and FIGS. It is a SEM photograph obtained when it actually manufactured based on the conventional method. FIG. 10 corresponds to FIG. 2C, and FIG. 11 corresponds to FIG.
[0056]
As can be seen by comparing these photographs, in the SEM photographs shown in FIGS. 11A and 11B, needle-like residues are present evenly, but the SEM photographs shown in FIGS. 10A and 10B are shown. Then, no residue is present.
[0057]
Note that the plasma used for removing the residue may be a plasma of a gas containing fluorine, and is not limited to the above CH ₂ F ₂ . For example, plasma of a gas such as CF ₄ , C ₄ F ₆ , C ₄ F ₈ , C ₅ F ₈ , CHF _3, or CH ₃ F can be used.
[0058]
The plasma irradiation with the gas containing fluorine is not limited to one time, and may be performed plural times depending on the thickness of the interlayer insulating film and the amount of the residue generated.
[0059]
Furthermore, in the second embodiment, a three-layer hard mask is formed on the interlayer insulating film. However, the Si ₃ N ₄ film 6 is not formed, and the SiO ₂ film 5 is used as a mask for a wiring groove. The SiC film 4 may be used as a mask for a via hole.
[0060]
【The invention's effect】
As described in detail above, according to the present invention, it is possible to reduce residues generated when forming a wiring groove. For this reason, it is possible to prevent a decrease in the yield and an increase in the resistivity of the wiring, and it is possible to improve the initial characteristics and the reliability.
[Brief description of the drawings]
FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.
FIG. 2 is a cross-sectional view showing a manufacturing method of the semiconductor device according to the first embodiment of the present invention in the order of steps, following FIG. 1;
FIG. 3 is a cross-sectional view showing a manufacturing method of the semiconductor device according to the first embodiment of the present invention in the order of steps, following FIG. 2;
FIG. 4 is a cross-sectional view showing a structure of a semiconductor device manufactured by applying the first embodiment of the present invention.
FIG. 5 is a sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.
FIG. 6 is a cross-sectional view showing a method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps, following FIG. 5;
FIG. 7 is a cross-sectional view showing a method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps, following FIG. 6;
FIG. 8 is a cross-sectional view showing a method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps, following FIG. 7;
FIG. 9 is a cross-sectional view showing a method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps, following FIG. 8;
FIG. 10 is a scanning electron microscope photograph obtained when a semiconductor device is manufactured based on the second embodiment of the present invention.
FIG. 11 is a scanning microscope photograph obtained when a semiconductor device is manufactured based on a conventional method.
FIG. 12 is a cross-sectional view showing a state in the middle of a conventional method of manufacturing a semiconductor device.
[Explanation of symbols]
1; Cu wiring 2; SiC film 3; organic low dielectric constant film 4; SiC film 5; SiO ₂ film 6; Si ₃ N ₄ film 7;
8a, 8b; resist mask 9; lower resin film 10; SOG films 11a, 11b; resist mask 12; wiring groove 13; via hole 14;

Claims (10)

In a method of manufacturing a semiconductor device in which wiring is formed by a dual damascene method,
Forming a hole shallower than the thickness of the interlayer insulating film in the interlayer insulating film by processing the interlayer insulating film made of an organic dielectric using a mask for a via hole;
Forming a wiring hole in the interlayer insulating film by processing the interlayer insulating film using a wiring groove mask, and forming a via hole by penetrating the hole to a lower layer;
Embedding a wiring material in the wiring groove and the via hole;
Has,
The step of forming the wiring groove,
Forming a groove in the interlayer insulating film by processing the interlayer insulating film using the wiring groove mask;
Using a mask for the wiring groove, irradiating plasma of a gas containing fluorine toward the bottom of the groove,
Using the mask for the wiring groove, processing the interlayer insulating film to increase the depth of the groove to form the wiring groove;
A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein a gas represented by a chemical formula C _x1 F _y1 or CH _x2 F _y2 is used as the fluorine-containing gas. 3. The step of processing the interlayer insulating film includes a step of etching the interlayer insulating film using plasma of at least one gas selected from the group consisting of hydrogen, nitrogen, and ammonia. 3. The method for manufacturing a semiconductor device according to 1 or 2. 4. The method according to claim 1, further comprising a step of forming a mask for the wiring groove and a mask for the via hole on the interlayer insulating film before the step of forming the hole. The manufacturing method of the semiconductor device described in the above. Prior to the step of forming the wiring groove mask and the via hole mask, a step of sequentially forming first and second insulating films on the interlayer insulating film,
Forming a mask for the wiring groove and a mask for the via hole;
Processing the second insulating film into a planar shape of the wiring groove;
Processing the first insulating film into a planar shape of the via hole;
The method for manufacturing a semiconductor device according to claim 4, comprising: Forming a mask for the wiring groove and a mask for the via hole;
Forming a resist mask for a wiring groove on the second insulating film;
Etching the second insulating film using the resist mask for the wiring groove;
6. The method for manufacturing a semiconductor device according to claim 5, comprising: Forming a mask for the wiring groove and a mask for the via hole;
Forming a resist mask for via holes on the first insulating film and the second insulating film;
Etching the first insulating film using the resist mask;
The method for manufacturing a semiconductor device according to claim 5, comprising: 8. The method according to claim 7, wherein in the step of forming the wiring groove mask and the via hole mask, a mask made of a multilayer resist is formed as the via hole resist mask. . 9. The method according to claim 8, wherein a stacked film including two films made of different materials is formed as the first insulating film. 10. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the hole, at least a part of the via-hole resist is removed.

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