JP2004220715A - Ferroelectric storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric storage device in which a non-selection memory cell can be protected even in a transition period at which a potential supplied to a word line and a bit line is changed. <P>SOLUTION: This device has ferroelectric capacitors (memory cells) 30 at each intersection of a plurality of word lines 40 and a plurality of bit lines 50. A selection word voltage supply line 230 and a non-selection word voltage supply line 240 are connected to a word line driving part 10 driving the plurality of word lines 40. A selection bit voltage supply line 210 and a non-selection bit voltage supply line 220 are connected to a bit line driving part 20 driving the plurality of word lines 50. Further, the device is provided with a potential change slope compensating part 100 decreasing difference between potential change slope in the selection word voltage supply line 230 and potential change slope in the non-selection bit voltage supply line 220, and difference between potential change slope in the selection bit voltage supply line 210 and potential change slope in the non-selection word voltage supply line 240. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ferroelectric memory device.
[0002]
[Background Art]
As a ferroelectric memory device, an active ferroelectric memory having a transistor and a capacitor in each cell (1T / 1C cell in which one ferroelectric is arranged, or 2T / 2C cell in which a reference cell is further arranged for each cell) Dielectric memories are known.
[0003]
However, this active type ferroelectric memory device has a larger memory area and a larger capacity as compared with other non-volatile memory devices such as flash memories and EEPROMs in which a memory cell is composed of one element. Can not be converted.
[0004]
As a nonvolatile memory device suitable for increasing the capacity, there is a ferroelectric memory device in which each memory cell is a single ferroelectric capacitor. (See Patent Document 1)
[0005]
[Patent Document 1]
JP-A-9-116107
[0006]
[Problems to be solved by the invention]
In a ferroelectric memory device in which each memory cell is a single ferroelectric capacitor, since there is no switch in each cell, the data stored in the non-selected memory cells is particularly likely to be deteriorated. The problem to be solved remains, and the present invention aims to solve it.
[0007]
[Means for Solving the Problems]
The ferroelectric memory device according to the present invention,
A plurality of word lines arranged in parallel with each other;
Intersecting with the plurality of word lines, a plurality of bit lines arranged in parallel with each other, a plurality of ferroelectric memory cells arranged at each intersection of the plurality of word lines and the plurality of bit lines,
A word line drive unit that drives the plurality of word lines;
A bit line driving unit that drives the plurality of bit lines;
A selected word voltage supply line and an unselected word voltage supply line connected to the word line driving unit;
A selected bit voltage supply line and an unselected bit voltage supply line connected to the bit line driving unit,
The difference between the potential change gradient at the selected word voltage supply line and the potential change gradient at the unselected bit voltage supply line, and the potential change gradient at the selected bit voltage supply line and the potential change gradient at the unselected word voltage supply line. And a potential change gradient correction unit that reduces at least one of the difference from the potential change gradient.
[0008]
In the present invention, an excessive voltage is applied to the non-selected memory cells even in the transition period in which the selected word voltage, the non-selected word voltage, the selected bit voltage, or the non-selected bit voltage is switched by the operation of the potential change gradient correction unit. It can be prevented from being applied. This prevents an unexpected overvoltage from being applied to the unselected memory cells, and protects data stored in the unselected memory.
[0009]
In the ferroelectric memory device according to the present invention, the word line drive unit and the bit line drive unit apply a selection voltage to a selected memory cell among the plurality of ferroelectric memory cells, and apply a selection voltage to the remaining unselected memory cells. Can apply a non-selection voltage. In this case, the potential change gradient correction unit includes a potential difference between the selected word voltage supply line and the unselected bit voltage supply line, and a potential difference between the selected word voltage supply line and the unselected bit voltage supply line. The potential difference can be set to be equal to or less than the non-selection voltage. Therefore, even in the transition period in which the various voltages are switched, a voltage equal to or lower than the non-selection voltage at the time when the various voltages reach a predetermined value and stable can be applied to the non-selected memory cells, and the data stored therein can be degraded. Can be prevented.
[0010]
The ferroelectric memory device according to the present invention further includes a power supply circuit for generating a plurality of types of voltages and a voltage selection circuit for selectively outputting the plurality of types of voltages to the word line driving unit and the bit line driving unit. be able to. A control circuit for outputting to the voltage selection circuit a timing signal for switching and outputting the plurality of voltages to the selected word voltage supply line, the unselected word voltage supply line, the selected bit voltage supply line, and the unselected bit voltage supply line. Further, it can be provided.
[0011]
Here, the control circuit can output a signal for switching the potentials of the selected bit voltage supply line and the non-selected bit voltage supply line almost simultaneously with the timing of supplying the selected word voltage supply line to the selected word voltage supply line. . In this case, the voltage selection circuit can supply the non-selected bit voltage to the non-selected bit voltage supply line almost simultaneously with the timing of supplying the selected word voltage to the selected word voltage supply line. The effect of this is a reduction in access time.
[0012]
Similarly, the control circuit can output a signal for switching the potentials of the selected word voltage supply line and the non-selected word voltage supply line almost simultaneously with the timing of supplying the selected bit voltage to the selected bit voltage supply line. . In this case, the voltage selection circuit can supply the unselected word voltage to the unselected word voltage supply line almost simultaneously with the timing of supplying the selected bit voltage to the selected bit voltage supply line. This effect also reduces access time.
[0013]
In the ferroelectric memory device according to the present invention, the potential change gradient correction unit can make the potential change gradients of the selected word voltage supply line and the selected bit voltage supply line gentle, respectively. As an example, the potential change gradient correction unit can increase a wiring load of the selected word voltage supply line and the selected bit voltage supply line. In this case, the potential change gradient correction unit is constituted by, for example, a resistor (R) and a capacitor (C), and the above-described potential change gradient can be moderated by an increased wiring load.
[0014]
As another example, the potential change gradient correction unit may supply a current per unit time flowing through the selected word voltage supply line and the selected bit voltage supply line to the unselected word voltage supply line and the unselected bit voltage supply line. The current can be reduced so as to approach the amount of current per unit time flowing through the line. In this case, the potential change gradient correction unit can use, for example, a small current driving capability of the transistor. The potential change gradient correction unit can be configured by, for example, connecting the transistor with a diode.
[0015]
The potential change gradient correction unit may make the potential change gradient of the non-selected word voltage supply line and the non-selected bit voltage supply line steep. In this case, the amount of current per unit time flowing through the unselected word voltage supply line and the unselected bit voltage supply line is converted into the amount of current per unit time flowing through the selected word voltage supply line and the selected bit voltage supply line. What is necessary is just to increase so that it may approach. In this case, on the contrary, the small current driving capability of the transistor can be used. In this case, the access time can be further reduced.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0017]
(Basic configuration of ferroelectric memory device)
First, the basic configuration of the ferroelectric memory device will be described. FIG. 1 is an overall view of a ferroelectric memory device according to an embodiment of the present invention.
[0018]
The ferroelectric memory device shown in FIG. 1 has a structure in which a plurality of ferroelectric capacitors (memory cells) 30 are arranged at intersections of a plurality of word lines 40 and a plurality of bit lines 50 arranged in a matrix. ing. To select a specific memory cell 30 from the plurality of memory cells 30, the word line 40 and the bit line 50 may be selected.
[0019]
In a computer, one bit can be considered as an amount capable of expressing two states, and a ferroelectric memory device uses two types of polarization states appearing in the hysteresis phenomenon of the ferroelectric capacitor 30 as one bit. It is.
[0020]
FIG. 4 shows the correlation between the voltage applied to the ferroelectric and the polarization value of the ferroelectric for the hysteresis phenomenon. The vertical axis P (Q) in FIG. 4 indicates the polarization value (charge amount) of the ferroelectric, and the horizontal axis V indicates the voltage applied to the ferroelectric. The curve in FIG. 4 shows a characteristic in which the polarization state of the ferroelectric capacitor 30 circulates according to the change in the voltage applied to the ferroelectric capacitor 30. For example, it is assumed that the selection voltage Vs is applied to the ferroelectric capacitor 30 at the point B. Then, the state shifts to the point A, and when the applied voltage becomes 0, the state returns to the point B again. Further, it is assumed that the selection voltage -Vs is applied to the ferroelectric capacitor 30. Then, the state shifts to point C, and when the applied voltage becomes 0, the state shifts to point D.
[0021]
Here, it is assumed that a voltage (Vs / 3) is applied to the ferroelectric capacitor 30. After that, when the applied voltage becomes 0, the state returns to the point D. This indicates that the polarization of the ferroelectric capacitor 30 does not reverse. Thereafter, when the voltage Vs is further applied to the ferroelectric capacitor 30, the state shifts to point A.
[0022]
In other words, when a voltage is applied to the ferroelectric capacitor 30, the polarization direction of the ferroelectric capacitor 30 after the application is different depending on the value of the applied voltage.
[0023]
To reverse the polarization of the ferroelectric capacitor 30, a constant applied voltage is required, and the required applied voltage value differs depending on the ferroelectric material used. Here, in the voltage applied to the ferroelectric capacitor 30, a value smaller than the absolute value of the coercive voltage, that is, the absolute value of the voltage set within a range in which the polarization of the ferroelectric capacitor 30 does not reliably invert, Defined as non-selection voltage. The voltage (Vs / 3) in FIG. 4 is a non-selection voltage according to the present embodiment. Incidentally, points E and F in FIG. 4 are generally called coercive voltages, and the coercive voltage refers to a voltage applied to the ferroelectric when the polarization value becomes zero. That is, the coercive voltage is a value that is a measure of the polarization reversal.
[0024]
According to the above properties, the polarization directions (positive potential and negative potential) of the ferroelectric capacitor 30 can be regarded as “0” and “1”, respectively. When storing “0”, the voltage Vs is applied to the ferroelectric capacitor 30, and when storing “1”, the voltage (−Vs) is applied to the ferroelectric capacitor 30. Further, the characteristic that the polarization state is preserved without receiving an external force can be linked to the non-volatility of the storage device.
[0025]
Next, reading and writing of data in the ferroelectric storage device will be described. First, at the time of data writing, "0" data writing and "1" data writing are required. Due to the characteristics of the ferroelectric capacitor 30, it is necessary to invert the direction of voltage application when writing "0" data and when writing "1" data. Therefore, "0" data writing and "1" data writing 2 steps are required.
[0026]
Further, since this ferroelectric memory device is a destructive read method, a rewrite operation is required after reading. Therefore, data reading requires two steps of reading and rewriting. In the first reading step, a state held from the amount of mobile charges in the ferroelectric capacitor 30 is read by applying a voltage in the same application direction as the “0” data writing. In the subsequent rewriting, the "1" data is rewritten only in the cell that originally stored the "1" data.
[0027]
From the above, “0” data writing and “1” data writing are required in each of data reading and data writing.
[0028]
In this specification, “0” data writing is defined as “read”, and “1” data writing is defined as “write”.
[0029]
As described above, the ferroelectric memory device operates as a memory device by performing read and write operations on the memory cell 30 using the ferroelectric capacitor while appropriately controlling the applied voltage and the application direction.
[0030]
(Configuration of peripheral circuit of memory cell array)
The power supply circuit 400 of FIG. 1 can generate four types of voltages (Vs, 2Vs / 3, Vs / 3, 0). Further, the power supply circuit 400 includes a plurality of voltage output lines for outputting a plurality of voltages to the voltage selection circuit 300. The plurality of voltage output lines include a voltage output line 410 that outputs a voltage Vs, a voltage output line 420 that outputs a voltage (2Vs / 3), a voltage output line 430 that outputs a voltage (Vs / 3), and a voltage 0. Voltage output line 440.
[0031]
The voltage selection circuit 300 transmits the plurality of voltages output from the power supply circuit 400 to the selected bit voltage supply line 210, the unselected bit voltage supply line 220, the selected word voltage supply line 230, and the unselected word voltage supply line 240. Select output.
[0032]
The voltage selection circuit 300 switches a plurality of voltages to the voltage supply lines 210 to 240 almost simultaneously based on a signal from the control circuit 510 and outputs a plurality of, for example, four power switch circuits 310 to 340 (FIGS. 11 to 14). ), Which will be described later.
[0033]
Further, a potential change gradient correction unit 100 is provided on each of the selected word voltage supply line 230 and the selected bit voltage supply line 210. The potential change gradient correction unit 100 reduces the difference between the potential change gradient on the selected word voltage supply line 230 and the potential change gradient on the unselected bit voltage supply line 220, and Of the potential change gradient of the non-selected word voltage supply line 240 is reduced.
[0034]
In the present embodiment, the potential change gradient correction unit 100 outputs the potential change gradients of the selected word voltage supply line 230 and the selected bit voltage supply line 210, that is, the rising and falling gradients of the potential, gradually. For example, as shown in FIG. 2, the potential change gradient correction unit 100 intentionally increases the wiring load using the capacitance (C) and the resistance (R), thereby making the rising and falling gradients of the potential gentle. . Alternatively, as shown in FIG. 3, the potential change gradient correction unit 100 uses the small current supply capability of the transistor TR to reduce the amount of current per time based on the applied voltage, and selects the selected word voltage supply line 230 and the selected bit. It is also possible to make the gradient of the current change during charging of the voltage supply line 210 gentle.
[0035]
Each of the plurality of word lines 40 is selectively connected to a selected word voltage supply line 230 or a non-selected word voltage supply line 240 by gate switches 11 and 12 controlled by the word line driving unit 10. Further, each of the plurality of bit lines 50 is selectively connected to a selected bit voltage supply line 210 or a non-selected bit supply line 220 by gate switches 21 and 22 controlled by the bit line driving unit 20.
[0036]
A bit line switch 51 and a bit line switch 52 are connected to each of the plurality of bit lines 50. The voltage of the selected bit voltage supply line 210 or the non-selected bit supply line 220 is supplied to the other end of the bit line switch 51 via one of the gate switches 21 and 22 controlled by the bit line drive unit 20. You.
The other end of the second bit line switch 52 is connected to the sense amplifier 80. The bit line switch 51 is controlled by a write selection line 60, and the bit line switch 52 is controlled by a read selection line.
[0037]
(Read and write)
Next, the read (0 write) and write (1 write) operations will be described.
[0038]
FIG. 5 shows a voltage applied to the memory cell 30 at the time of reading. The selected memory cell 30a in FIG. 5 is the memory cell 30 to be read. 5 denotes a selected bit line, a reference character USBL denotes an unselected bit line, a reference character SWL denotes a selected word line, and a reference character USWL denotes a non-selected word line. A voltage is supplied to the selected memory cell 30a from the selected word voltage supply line 230 and the selected bit voltage supply line 210.
[0039]
The unselected memory cells 30b in FIG. 5 represent the remaining plurality of memory cells 30 that are not to be read. The non-selected memory cells 30b may receive a voltage from the non-selected word voltage supply line 240 and the non-selected bit voltage supply line 220, a voltage from the selected word voltage supply line 230 and the non-selected bit voltage supply line 220, or a non-selected word voltage. One of the voltages from the supply line 240 and the selected bit voltage supply line 210 is supplied.
[0040]
The voltage selection circuit 300 selectively outputs a plurality of voltages (VS, 2Vs / 3, Vs / 3, 0) generated by the power supply circuit 400 to a plurality of voltage supply lines. The voltage Vs and the voltage (Vs / 3) are output to 10, and the voltage 0 and the voltage (2 Vs / 3) are output to the bit line driving unit 20.
[0041]
Specifically, at this time, the voltage selection circuit 300 uses the selected word voltage supply line 230 for the output of the voltage Vs, uses the unselected bit voltage supply line 220 for the output of the voltage 2Vs / 3, and outputs the voltage Vs / 3. An unselected word voltage supply line 240 is used for output, and a selected bit voltage supply line 210 is used for output of voltage 0.
[0042]
To read data from the selected memory cell 30a, the voltage Vs is output from the selected word voltage supply line 230 to the selected word line SWL, and the voltage 0 is output from the selected bit voltage supply line 210 to the selected bit line SBL. . Therefore, the voltage Vs is applied to the selected memory cell 30a, and the selected memory cell 30a moves from the point B or D to the point A in FIG.
[0043]
FIG. 6 shows a voltage applied to the memory cell 30 at the time of writing. The selected memory cell 30a in FIG. 6 is the memory cell 30 to be written. A voltage is supplied to the selected memory cell 30a from the selected word voltage supply line 230 and the selected bit voltage supply line 210.
[0044]
The unselected memory cells 30b in FIG. 6 represent the remaining plurality of memory cells 30 not to be written. The non-selected memory cells 30b may receive a voltage from the non-selected word voltage supply line 240 and the non-selected bit voltage supply line 220, a voltage from the selected word voltage supply line 230 and the non-selected bit voltage supply line 220, or a non-selected word voltage. One of the voltages from the supply line 240 and the selected bit voltage supply line 210 is supplied.
[0045]
The difference between the write and the read is that the voltage selected and output by the voltage selection circuit 300 is switched between the word line driver 10 and the bit line driver 20.
[0046]
Specifically, at this time, the voltage selection circuit 300 uses the selected bit voltage supply line 210 for the output of the Vs voltage, uses the non-selected word voltage supply line 240 for the output of the voltage 2Vs / 3, and outputs the voltage Vs / 3. An unselected bit voltage supply line 220 is used for output, and a selected word voltage supply line 230 is used for output of zero voltage.
[0047]
To write to the selected memory cell 30a, a voltage of 0 is output from the selected word voltage supply line 230 to the selected word line SWL, and a voltage Vs is output from the selected bit voltage supply line 210 to the selected bit line SBL. You. Therefore, the voltage -Vs is applied to the selected memory cell 30a, and moves from the point B or D to the point C in FIG.
[0048]
(Operation of the potential change gradient correction unit)
The reason for providing the potential change gradient correction unit 100 in the present embodiment is as follows. The load connected to the selected bit voltage supply line 210 and the selected word voltage supply line 230 is much smaller than the load connected to the unselected bit voltage supply line 220 and the unselected word voltage supply line 230. Therefore, the potential change gradient on the selected bit voltage supply line 210 and the selected word voltage supply line 230 is steeper than the potential change gradient on the unselected bit voltage supply line 220 and the unselected word voltage supply line 230. In order to reduce such a difference in potential change gradient between the voltage supply lines 210 to 240, a potential change gradient correction unit 100 is provided.
[0049]
More specifically, the number of selected word lines SWL and selected bit lines SBL connected to the selected bit voltage supply lines 210 and selected word voltage supply lines, and the number of selected memory cells 30a connected to them are relatively small. is there. On the other hand, the number of unselected word lines USWL and unselected bit lines USBL connected to the unselected bit voltage supply lines 220 and unselected word voltage supply lines 230, and the number of unselected memory cells 30b connected to them. The number is overwhelmingly large. Therefore, the load connected to the unselected bit voltage supply line 210 and the unselected word voltage supply line 230 is large, and the rising and falling gradients of the potentials on the unselected word line USWL and the unselected bit line USBL become gentle. is there.
[0050]
A problem that occurs in the comparative example in which the potential change gradient correction unit 100 is not provided will be described with reference to FIGS. For example, FIG. 7 shows that voltages are applied to the selected word line SWL and the unselected bit line USBL at the same timing during the read period. According to FIG. 7, the voltage difference Vdef1 between the selected word line SWL and the unselected bit line USBL temporarily exceeds the non-selection voltage (Vs / 3). Similarly, FIG. 8 shows that a voltage is applied to the selected bit line SWL and the unselected word line USWL at the same timing during the write period. According to FIG. 8, the voltage difference Vdef2 between the selected bit line SBL and the unselected word line USWL temporarily exceeds the non-selection voltage (Vs / 3).
[0051]
7 and 8, a voltage exceeding a non-selection voltage in a potential change process is applied to a non-selected memory cell. The application of the overvoltage to the unselected memory cells promotes disturbance of the stored data, and is not preferable.
[0052]
In the present embodiment, since the potential change gradient correction unit 100 is provided, it is possible to avoid the problems that occur in the above comparative example. That is, in the present embodiment, even if, for example, a voltage is applied to the selected word line SWL and the unselected bit line USBL at the same timing, the voltage difference between the selected word line SWL and the unselected bit line USBL becomes the non-selection voltage (Vs / 3) will not be exceeded.
[0053]
Next, the operation of the potential change gradient correction unit 100 during reading and writing will be described. FIG. 9 is a waveform diagram showing a voltage change of the selected word line SWL and the unselected bit line USBL at the time of reading in the present embodiment. According to FIG. 9, the voltage difference Vdef3 between the selected word line SWL and the non-selected bit line USBL does not exceed the non-selection voltage (Vs / 3). This is because the potential change gradient correction unit 100 operates on the selected word line SWL which originally has a small wiring load, and the rise of the voltage of the selected word line SWL is moderated. FIG. 10 is a waveform diagram showing a voltage change of the selected bit line SBL and the unselected word line USWL at the time of writing in the present embodiment. At the time of writing, the potential change gradient correction unit 100 exhibits the same effect as at the time of reading. The potential change gradient correction unit 100 operates so as to make the rising of the voltage of the selected bit line SBL gentle. As a result, the voltage difference Vdef4 between the selected bit line SBL and the unselected word line USWL does not exceed the non-selection voltage (Vs / 3).
[0054]
(Voltage selection circuit and control circuit)
Next, the voltage selection circuit 300 will be described.
[0055]
The power switch circuits 310 to 340 provided in the power selection circuit 300 are shown in FIGS. The output of the power switch circuit 310 of FIG. 11 is connected to the selected word voltage supply line 230, and the output of the power switch circuit 320 of FIG. 12 is connected to the non-selected word voltage supply line 240. Further, the output of the power switch circuit 330 in FIG. 13 is connected to the selected bit voltage supply line 210, and the output of the power switch circuit 340 in FIG. 14 is connected to the non-selected bit voltage supply line 220. Inputs 1 to 6 in FIGS. 11 to 14 are connected to the control circuit 510.
[0056]
When the drive signal from the control circuit 510 is input to the input 1 in FIG. 11, the voltage Vs is output to the selected word voltage supply line 230. When a drive signal from the control circuit 510 is input to the input 2 in FIG. 11, a voltage 0 is output to the selected word voltage supply line 230. Further, when a drive signal is not input to the inputs 1 and 2 in FIG. 11, the voltage Vs / 3 is output to the selected word voltage supply line 230.
[0057]
When a drive signal from the control circuit 510 is input to the input 3 in FIG. 12, a voltage 2Vs / 3 is output to the non-selected word voltage supply line 240. When no drive signal is input to input 3 in FIG. 12, voltage Vs / 3 is output to non-selected word voltage supply line 240.
[0058]
When the drive signal from the control circuit 510 is input to the input 4 in FIG. 13, the voltage Vs is output to the selected bit voltage supply line 210. When a drive signal from the control circuit 510 is input to the input 5 in FIG. 13, a voltage 0 is temporarily output to the selected bit voltage supply line 210 by the pulse circuit 331 in FIG. Further, when a drive signal is not input to inputs 4 and 5 in FIG. 13, voltage Vs / 3 is output to selected bit voltage supply line 210. FIG. 15 shows an equivalent circuit of the pulse circuit 331.
[0059]
When a drive signal from the control circuit 510 is input to the input 6 of FIG. 14, a voltage of 2 Vs / 3 is output to the non-selected bit voltage supply line 220. When no drive signal is input to input 6 in FIG. 13, voltage Vs / 3 is output to non-selected bit voltage supply line 220.
[0060]
That is, each of the power switch circuits 310 to 340 selectively outputs a voltage to each of the voltage supply lines 210 to 240 according to the drive signal output from the control circuit 510. The control circuit 510 is a circuit that temporally controls the voltage of each of the voltage supply lines 210 to 240.
[0061]
Next, the control circuit 510 will be described with reference to FIG.
[0062]
The control circuit 510 of FIG. 16 includes delay circuits 511 to 513. FIG. 17 shows a plurality of inverters INV constituting each of the delay circuits 511 to 513.
Trig in FIG. 16 is a signal output when the selected memory cell is accessed. When this trig signal is input to the control circuit 510 in FIG. 16, the signals (SW0, SW2, UW2, SB0, SB3) controlling the output voltages of the voltage supply lines 210 to 240 are operated by the delay circuits 511 to 513. , UB2) are sequentially sent to the voltage selection circuit 300. The voltage selection circuit 300 determines a voltage to be output to each of the voltage supply lines 210 to 240 based on the received signal.
[0063]
FIG. 18 shows a timing chart of each signal output from control circuit 510 in FIG. At the same time, FIG. 18 shows a waveform diagram of the voltage applied to each of the selected word line SWL, unselected word line USWL, selected bit line SBL, and unselected bit line USBL in the same sequence as the above-described timing chart. Reference numerals t0 to t3 in FIG. 18 indicate time timing. Symbols T1 to T3 represent time intervals. The time interval T1 corresponds to a read period, and the time interval T3 corresponds to a write period. According to FIG. 18, when the trig signal is input to the control circuit 510 of FIG. 16 at the timing t0, first, the signal SW3 is supplied to the power switch circuit 310, the signal SB0 is supplied to the power switch circuit 330, and the signal UB2 is supplied to the power switch circuit. Output to 340. At this time, the voltage Vs is supplied to the selected word voltage supply line 230. At the same time, the voltage 0 is supplied to the selected bit voltage supply line 210 and the voltage 2Vs / 3 is supplied to the non-selected bit voltage supply line 220. That is, a voltage is simultaneously applied to the selected word line and the non-selected bit line at the timing t0. It is clear from the waveform diagrams of the selected word line SWL and the unselected bit line USBL in FIG. 18 that the time required for the selected word line SWL to rise to the voltage Vs and the unselected bit line USBL to rise to the voltage 2Vs / 3. And the time required for this is almost the same. This is due to the function of the potential change gradient correction unit 100. Next, at the timing t1, the signal SW3, the signal SB0, and the signal UB2 fall, and Vs / 3 is supplied to the selected word voltage supply line 230, the selected bit voltage supply line 210, and the unselected bit voltage supply line 220. A period from timing t0 when the trig signal is input to the control circuit 510 to timing t1 is a read operation period.
[0064]
This time, at the timing t2, the signal SW0 is output to the power switch circuit 310, the signal UW2 is output to the power switch circuit 320, and the signal SB0 is output to the power switch circuit 330. At this time, a voltage 0 is supplied to the selected word voltage supply line 230. At the same time, the voltage 2Vs / 3 is supplied to the unselected word voltage supply line 240, and the voltage Vs is supplied to the selected bit voltage supply line 210. That is, a voltage is simultaneously applied to the unselected word line and the selected bit line at the timing t2. Further, as in the case of reading, the time required for the selected bit line SBL to rise to the voltage Vs and the time required for the unselected word line USWL to rise to the voltage 2Vs / 3 are almost the same. This is also due to the action of the potential change gradient correction unit 100. Next, at the timing t3, the signal SW0, the signal UW2, and the signal SB0 fall, and Vs / 3 is supplied to the selected word voltage supply line 230, the unselected word voltage supply line 240, and the selected bit voltage supply line 210. A period from timing t2 to timing t3 after reading is a write operation period. In this manner, a voltage application waveform diagram as shown in FIG. 18 can be obtained by the operations of the control circuit 510 and the power switch circuits 310 to 340 in FIG.
[0065]
(Comparison between embodiment and comparative example)
In order to explain the effects of the present embodiment, a comparative example will be described.
[0066]
FIG. 19 shows a control circuit 500 of a comparative example for setting the voltage application timing as shown in FIG. The delay circuits 501 to 507 in FIG. 19 have an even number of inverters INV shown in FIG.
[0067]
The trigger signal trig, the sign SW3, the sign SB0, the sign UB2, the sign SB3, the sign SW0, and the sign UW2 in FIG. 19 have the same meanings as those in FIG.
[0068]
When the trigger signal trig in FIG. 19 is input to the control circuit 500, the signals (signals SW3, SB0, UB2, SB3, SW0, and SW3) that control the output voltages of the voltage supply lines 210 to 240 by the operation of the delay circuits 501 to 507. UW2) are sequentially sent to the voltage selection circuit 300. The voltage selection circuit 300 determines a voltage to be output to each of the voltage supply lines 210 to 240 based on the received signal. In the voltage selection circuit 300, switch circuits 310 to 340 for processing received signals are provided in the voltage supply lines 210 to 240.
[0069]
FIG. 20 shows a waveform diagram of voltage application to the selected word line SWL, unselected word line USWL, selected bit line SBL, and unselected bit line USBL in the comparative example. FIG. 20 shows a timing chart of each signal output from the control circuit 500 of FIG. 19 in a simultaneous sequence with the above-described voltage application waveform chart.
[0070]
Time intervals T1 to T7 in FIG. 20 are time intervals created by the delay circuits 501 to 507 in FIG. 19, respectively. The read period in FIG. 20 represents a period during which reading (“0” writing) is being performed on the selected memory cell, and similarly, the writing period in FIG. 20 is writing (“1” writing) on the selected memory cell. Represents the period during which
[0071]
Upon receiving the trig signal, the control circuit 500 operates the signals (SW3, SB0, UB2, SB3, SW0, UW2) at the timing shown in the timing chart of FIG. 20 by the operation of the delay circuits 501 to 507. Output to the voltage selection circuit 300. The voltage selection circuit 300 receiving these signals outputs a voltage to the selected word line SWL, unselected word line USWL, selected bit line SBL, and unselected bit line USBL as shown in the voltage waveform diagram of FIG.
[0072]
According to FIG. 20, during the read period, there is a time lag between the timing t0 at which the voltage is applied to the selected bit line SBL and the unselected bit line USBL and the timing t1 at which the voltage Vs starts to be supplied to the selected word line SWL. . Similarly, even during the write period, there is a time lag between a timing t4 at which a voltage is applied to the selected word line SWL and the unselected word line USWL and a timing t5 at which the voltage Vs starts to be supplied to the selected bit line. This is because the difference in the voltage rising gradient is considered as described below.
[0073]
For example, if the voltage is applied to the selected word line SWL and the non-selected bit line USBL at the same timing during the read period without providing the potential change gradient correction unit 100 as in the present embodiment, the problem shown in FIG. The consequences have already been explained.
[0074]
For this reason, in the comparative example shown in FIG. 20, in order to prevent a voltage exceeding the non-selection voltage (Vs / 3) from being applied to the non-selected memory cells, it is shown in FIG. A time lag is provided for each of the two voltage application timing pairs (t0-t1), (t2-t3), (t4-t5), and (t6-t7).
[0075]
However, this comparative example has a disadvantage that the memory access speed is reduced. Therefore, in the present embodiment, the time lag of the voltage application timing provided for the selected word line and the plurality of bit lines 50 or the selected bit line and the plurality of word lines 40 is eliminated. Then, the time can be reduced by the time lag. In the comparative example, a time lag was required because the absolute value of the voltage difference of the applied voltage could not be suppressed to Vs / 3 or less due to the difference in the voltage rising gradient. However, in the present embodiment, the difference in the voltage rising gradient is reduced by using the potential change gradient correcting unit 100. As a result, the absolute value of the voltage difference between the applied voltages can be reliably suppressed to Vs / 3 or less.
[0076]
(Modification of this embodiment)
As a modification of the present embodiment, the potential change gradient correction unit 100 can be provided only on one of the selected word voltage supply line 230 and the selected bit voltage supply line 210. In this case, the voltage supply line (the selected word voltage supply line 230 or the selected bit voltage supply line 210) provided with the potential change gradient correction unit 100 is provided with a time lag of the voltage application timing as shown in the comparative example. This eliminates the necessity, and the access time can be reduced by the time lag.
[0077]
As described above, the embodiment according to the ferroelectric storage device realizes a reduction in the memory access time.
[0078]
Note that the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a block diagram of a ferroelectric memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a potential change gradient correction unit.
FIG. 3 is a circuit diagram illustrating an example of a potential change gradient correction unit.
FIG. 4 is a diagram showing a hysteresis phenomenon of a ferroelectric substance.
FIG. 5 is a diagram showing a voltage application state during a read operation of the ferroelectric memory device according to one embodiment of the present invention.
FIG. 6 is a diagram showing a voltage application state during a write operation of the ferroelectric memory device according to one embodiment of the present invention.
FIG. 7 is a diagram comparing the voltage rising gradients of a selected word line and a non-selected bit line.
FIG. 8 is a diagram comparing the voltage rising gradients of an unselected word line and a selected bit line.
FIG. 9 is a diagram comparing the voltage rising gradients of a selected word line and a non-selected bit line.
FIG. 10 is a diagram comparing the voltage rising gradients of an unselected word line and a selected bit line.
11 is a diagram showing a power switch circuit provided in the voltage selection circuit shown in FIG.
12 is a diagram showing another power switch circuit provided in the voltage selection circuit shown in FIG.
FIG. 13 is a diagram showing still another power switch circuit provided in the voltage selection circuit shown in FIG. 1;
FIG. 14 is a diagram showing still another power switch circuit provided in the voltage selection circuit shown in FIG. 1;
15 is a diagram illustrating a pulse circuit 331 used in the power switch circuit illustrated in FIG.
FIG. 16 is a diagram showing a control circuit shown in FIG. 1;
FIG. 17 is a diagram illustrating a configuration of a delay circuit illustrated in FIG. 16;
FIG. 18 is a diagram showing a timing chart for explaining an operation in one embodiment of the present invention.
FIG. 19 is a diagram illustrating a control circuit of a comparative example.
FIG. 20 is a timing chart illustrating the operation of the comparative example.
[Explanation of symbols]
Reference Signs List 10 word line driver, 11 gate switch, 12 gate switch, 20 bit line driver, 21 gate switch, 22 gate switch, 30 ferroelectric capacitor, 40 word line, 50 bit line, 51 bit line switch, 52 bit line Switch, 60 write select line, 70 read select line, 80 sense amplifier, 90 memory cell array, 100 potential change gradient correction section, 210 selected bit voltage supply line, 220 unselected bit voltage supply line, 230 selected word voltage supply line, 240 Unselected word voltage supply line, 300 voltage selection circuit, 400 power supply circuit, 410 first voltage output line, 420 second voltage output line, 430 third voltage output line, 440
Fourth voltage output line, 510 control circuit

Claims (10)

A plurality of word lines arranged in parallel with each other;
Intersecting with the plurality of word lines, a plurality of bit lines arranged in parallel with each other, a plurality of ferroelectric memory cells arranged at each intersection of the plurality of word lines and the plurality of bit lines,
A word line drive unit that drives the plurality of word lines;
A bit line driving unit that drives the plurality of bit lines;
A selected word voltage supply line and an unselected word voltage supply line connected to the word line driving unit;
A selected bit voltage supply line and an unselected bit voltage supply line connected to the bit line driving unit,
The difference between the potential change gradient at the selected word voltage supply line and the potential change gradient at the unselected bit voltage supply line, and the potential change gradient at the selected bit voltage supply line and the potential change gradient at the unselected word voltage supply line. A potential change gradient correction unit that reduces at least one of the difference from the potential change gradient of the ferroelectric memory device. In claim 1,
The word line driving unit and the bit line driving unit apply a selection voltage to a selected memory cell of the plurality of ferroelectric memory cells, and apply a non-selection voltage to the remaining non-selected memory cells.
The potential change gradient correction unit is configured to calculate a potential difference between the selected word voltage supply line and the unselected bit voltage supply line, and a potential difference between the selected word voltage supply line and the unselected bit voltage supply line. The ferroelectric memory device is set at a voltage lower than the non-selection voltage. In claim 1 or 2,
A power supply circuit for generating a plurality of types of voltages,
A voltage selection circuit for selectively outputting the plurality of voltages to the word line drive unit and the bit line drive unit;
A control circuit for outputting to the voltage selection circuit a timing signal for switching and outputting the plurality of voltages to the selected word voltage supply line, the unselected word voltage supply line, the selected bit voltage supply line, and the unselected bit voltage supply line. And a ferroelectric memory device further comprising: In claim 3,
The control circuit outputs a signal for switching the potentials of the selected bit voltage supply line and the non-selected bit voltage supply line almost simultaneously with the timing of supplying the selected word voltage to the selected word voltage supply line. Dielectric storage device. In claim 3,
The control circuit outputs a signal for switching the potentials of the selected word voltage supply line and the unselected word voltage supply line almost simultaneously with the timing of supplying the selected bit voltage supply line to the selected bit voltage supply line. Dielectric storage device. In any one of claims 1 to 5,
The ferroelectric memory device, wherein the potential change gradient correction unit makes the potential change gradients of the selected word voltage supply line and the selected bit voltage supply line gentle, respectively. In claim 6,
The ferroelectric memory device, wherein the potential change gradient correction unit increases a wiring load on the selected word voltage supply line and the selected bit voltage supply line. In claim 6,
The potential change gradient correction unit is configured to calculate the amount of current per unit time flowing through the selected word voltage supply line and the selected bit voltage supply line by a unit time flowing through the unselected word voltage supply line and the unselected bit voltage supply line. A ferroelectric memory device characterized in that the current is reduced so as to approach the current amount per unit area. In any one of claims 1 to 5,
The ferroelectric memory device, wherein the potential change gradient correction unit makes the potential change gradients of the unselected word voltage supply line and the unselected bit voltage supply line steep, respectively. In claim 9,
The potential change gradient correction unit is configured to supply a current amount per unit time flowing through the unselected word voltage supply line and the unselected bit voltage supply line to the unselected word voltage supply line and the unselected bit voltage supply line. A ferroelectric memory device characterized by increasing the current amount so as to approach a current amount per unit time.

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