JP2004214557A - Semiconductor device having trench structure and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a vertical type trench structure capable of suppressing the local increase of the electric field strength of the bottom of a trench gate and suppressing the deterioration of withstand pressure between drain sources or collector emitters. <P>SOLUTION: This semiconductor device is provided with a first semiconductor layer 12 of a first conductivity type on one side of a semiconductor substrate 11 of the first conductivity type, and a second semiconductor layer 13 of a second conductivity type the first semiconductor layer 12. A third semiconductor layer 14 of the first conductivity type is provided on the surface of the second semiconductor layer 13. A trench 15 is formed so as to penetrate the third semiconductor layer 14 and the second semiconductor layer 13 and to reach the first semiconductor layer 12. The first and second semiconductor layers 12 and 13 are provided with a part 21a in which the jointing surface 21 of the both is parallel to the semiconductor substrate 11, and a part 21b formed so as to be depressed toward the side 15a of the trench 15 and come in contact with the side 15a. A distance L1 between the side 15a opposite to the adjacent trench 15 is formed three or more as large as the distance L2 of a boundary 21c of the parts 21a and 21b, and the side 15a. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a trench structure and a method for manufacturing the same.
[0002]
[Prior art]
As MOSFETs and insulated gate bipolar transistors (IGBTs), vertical MOSFETs and vertical IGBTs having a trench structure that can further reduce the cell size are known. As shown in FIG. 7A, the vertical MOSFET 50 has an n-type drift layer 52 formed on a semiconductor substrate 51. A p-type channel formation layer 53 is provided on the upper surface of the drift layer 52 (the surface opposite to the semiconductor substrate 51), and an n-type source region 54 is provided on the surface of the channel formation layer 53. A trench 55 is formed so as to extend from the surface of the central portion of source region 54 through part of channel forming layer 53 to drift layer 52.
[0003]
A gate oxide film 56 is formed on the inner wall surface of the trench 55, and a gate electrode 57 is provided from above the gate oxide film 56 so as to fill the trench 55. Gate oxide film 56 is formed to cover a portion of gate electrode 57 on the trench opening side, and insulating layer 58 is formed to cover a portion of gate oxide film 56 on the trench opening side. A source electrode 59 is formed to cover the exposed surfaces of the channel forming layer 53 and the source region 54 and the exposed portions of the gate oxide film 56 and the insulating layer 58, and the back surface of the semiconductor substrate 51 (the surface opposite to the drift layer 52). Is formed with a drain electrode 60. A gate terminal G, a source terminal S, and a drain terminal D are connected to the gate electrode 57, the source electrode 59, and the drain electrode 60, respectively.
[0004]
In the trench gate type MOSFET 50 having the above-described configuration, the bottom of the gate electrode 57 exists on the semiconductor substrate 51 side from the junction surface between the drift layer 52 and the channel forming layer 53. In the MOSFET 50 having such a configuration, when a voltage is applied between the drain terminal D and the source terminal S when the gate terminal G and the source terminal S are short-circuited (switch-off state), the drift layer 52 and the channel forming layer 53 A depletion layer extends on both sides of the junction surface. Then, as shown in FIG. 7B, the interval between the equipotential lines LV at the bottom of the trench gate is narrowed and the electric field strength is locally increased (the trench side surface at the junction surface between the drift layer 52 and the channel forming layer 53). Contact portion and the bottom of the trench gate). As a result, there is a problem that the breakdown voltage between the drain and the source is reduced.
[0005]
7A and 7B, in the drawings, the thickness and size of each element constituting the MOSFET 50 are shown in a relative relationship that does not always match the actual one for convenience of illustration. For example, actually, the thickness of the source region 54 is about 0.5 μm while the thickness of the gate oxide film 56 is about 0.1 μm.
[0006]
As a means for solving the above problem, as shown in FIG. 8, a configuration in which an electric field relaxation semiconductor region 61 is provided below a trench-type insulated gate, that is, below a trench 55 has been proposed (see Patent Document 1). . Also, Patent Document 1 proposes that the thickness of the gate oxide film 56 at the bottom of the trench is made 5 to 20 times or more the thickness of the gate oxide film 56 on the side surface of the trench 55 to improve voltage sharing. ing.
[0007]
[Patent Document 1]
JP-A-10-98188 (paragraphs [0004] and [0005] of the specification, FIGS. 1 and 9)
[0008]
[Problems to be solved by the invention]
However, the structure disclosed in Patent Document 1 in which the thickness of the gate oxide film 56 at the bottom of the trench is increased is difficult to manufacture. If the entire gate oxide film 56 is made thicker, the problem of electric field strength can be solved, but in this case, the on-resistance of the MOS transistor section increases. Further, in the configuration in which the electric field relaxation semiconductor region 61 is provided, the number of manufacturing steps of the trench gate portion is increased, and the current path is restricted, so that the on-resistance is easily increased.
[0009]
A first object of the present invention is to suppress a local increase in electric field strength at a contact portion between a channel forming layer and a drift layer at a junction side surface of a trench and at a bottom portion of a trench gate, thereby preventing a drain-source or collector -To provide a semiconductor device having a vertical trench structure capable of suppressing a decrease in breakdown voltage between emitters. A second object is to provide a method for manufacturing the semiconductor device.
[0010]
[Means for Solving the Problems]
In order to achieve the first object, the invention according to claim 1 is a semiconductor device having a vertical trench structure. The semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type provided on one side of the semiconductor substrate, and a channel region formed on an anti-semiconductor substrate side surface of the first semiconductor layer. The semiconductor device includes a second semiconductor layer of the second conductivity type, and a third semiconductor layer of the first conductivity type provided in a part of a surface layer of the second semiconductor layer. The semiconductor device further includes a trench provided so as to reach the first semiconductor layer through the third semiconductor layer and the second semiconductor layer. The semiconductor device includes a portion where the bonding surface between the first semiconductor layer and the second semiconductor layer is parallel to the semiconductor substrate, and a portion formed so as to be recessed toward the side surface of the trench and in contact with the side surface of the trench. .
[0011]
According to the present invention, in a configuration in which a first semiconductor layer of the first conductivity type is directly stacked on a semiconductor substrate of the first conductivity type, the semiconductor device is a MOSFET. Then, the first semiconductor layer becomes a drift layer, the second semiconductor layer becomes a channel formation layer, and the third semiconductor layer becomes a source region. Further, in a configuration in which a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor layer is stacked over a second conductive type semiconductor substrate via a first conductive type semiconductor layer, Becomes an IGBT. Then, the first semiconductor layer serves as a drift layer, the second semiconductor layer serves as a channel formation layer, and the third semiconductor layer serves as an emitter region.
[0012]
The semiconductor device includes a portion where the bonding surface between the first semiconductor layer and the second semiconductor layer is parallel to the semiconductor substrate, and a portion formed so as to be concave toward the side surface of the trench and in contact with the side surface of the trench. Therefore, unlike the conventional semiconductor device in which the entire bonding surface between the first semiconductor layer and the second semiconductor layer is formed in parallel with the semiconductor substrate, the contact between the channel forming layer and the drift layer at the side surface of the trench is different. The local increase in the electric field strength at the portion and the bottom of the trench gate is suppressed. As a result, a decrease in breakdown voltage between the drain and the source of the MOSFET or between the collector and the emitter of the IGBT can be suppressed.
[0013]
According to a second aspect of the present invention, in the first aspect of the present invention, a distance between opposing side surfaces of the adjacent trench is L1, a portion of the bonding surface parallel to the semiconductor substrate, and a side surface of the trench. Assuming that the distance between the boundary between the recessed portion and the side surface of the trench is L2, the distance L1 is formed to be three times or more the distance L2. In the present invention, the contact portion between the channel forming layer and the drift layer at the junction side surface with the trench side surface is smaller than the distance L1 between the side surfaces of the trench being less than three times the distance L2. The local increase in the electric field strength at the gate bottom is further suppressed.
[0014]
According to a third aspect of the present invention, in the second aspect of the present invention, the incident angle θ of the junction surface to the side surface of the trench satisfies 0 ° <θ <90 °. The “incident angle θ of the bonding surface to the side surface of the trench” means an angle formed between a concave portion of the bonding surface and a portion of the bonding surface parallel to the semiconductor substrate. When the formed portion is a curved surface, it means an angle formed between a tangent at an intersection of the portion and the side surface and the parallel portion.
[0015]
In the present invention, the electric field strength at the contact portion between the channel forming layer and the drift layer at the junction side surface and the trench gate bottom portion is smaller than when the incident angle θ is formed at 0 ° or 90 ° or more. Is locally suppressed from increasing.
[0016]
According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, a portion formed so as to be concave toward a side surface of the trench is the first semiconductor layer. It is formed on a curved surface that is convex toward the side. According to the present invention, the local increase in the electric field strength at the trench gate bottom portion is further suppressed as compared with the case where the portion is formed in a plane.
[0017]
To achieve the second object, the invention according to claim 5 includes a first semiconductor layer forming step of forming a first semiconductor layer of the first conductivity type on one side of a semiconductor substrate. Further, after forming an oxide film on the surface of the first semiconductor layer by LOCOS oxidation so as to increase the film thickness at a position corresponding to the position where the trench is formed, the oxide film is removed to remove the oxide film. A concave portion forming step of forming, on the surface of the one semiconductor layer, a concave portion having a bottom surface parallel to the surface of the semiconductor substrate at the center and having an inclined portion inclined toward the bottom surface; A second semiconductor layer forming step of forming a second conductivity type second semiconductor layer on the surface of the first semiconductor layer after the formation of the concave portion, and a first semiconductor layer penetrating the second semiconductor layer. Forming a trench having a depth reaching the semiconductor layer at a position corresponding to the bottom surface of the concave portion. A third semiconductor layer forming step of forming a third semiconductor layer of the first conductivity type performed after or before the trench forming step, and after the trench forming step and the third semiconductor layer forming step. Steps after the gate oxide film forming step are performed.
[0018]
According to the manufacturing method of the present invention, the first semiconductor layer of the first conductivity type is formed on one side of the semiconductor substrate. There are a case where a semiconductor substrate of the first conductivity type is used as a semiconductor substrate and a case where a semiconductor substrate of the second conductivity type is used. When a semiconductor substrate of the first conductivity type is used, the first semiconductor layer is directly formed on the semiconductor substrate. When a semiconductor substrate of the second conductivity type is used, a first semiconductor layer of the first conductivity type having a lower impurity concentration than the semiconductor layer is formed on the semiconductor substrate via a semiconductor layer of the first conductivity type. Is done. Then, an oxide film is formed on the surface of the first semiconductor layer by LOCOS oxidation so that the film thickness at a position corresponding to the position where the trench is formed is increased. After that, by removing the oxide film, a concave portion having a bottom surface parallel to the surface of the semiconductor substrate and having an inclined portion inclined toward the bottom surface is formed in the surface of the first semiconductor layer. Next, after the second semiconductor layer of the second conductivity type is formed on the surface of the first semiconductor layer in the second semiconductor layer forming step, the trench is formed through a trench forming step and a third semiconductor layer forming step. A trench is formed at a position corresponding to the recess, the trench having a depth reaching the first semiconductor layer through the third semiconductor layer and the second semiconductor layer. Thereafter, steps after the gate oxide film forming step are performed to form a semiconductor device. Therefore, the semiconductor device according to the first aspect of the present invention can be easily manufactured.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
(First Embodiment)
A first embodiment in which the present invention is embodied in a MOSFET as an n-channel semiconductor device will be described with reference to FIGS. FIG. 1 is a partial schematic cross-sectional view of a MOSFET, and FIG. 2 is a partial schematic cross-sectional view illustrating an operation. Note that a part of hatching in the cross section is omitted.
[0020]
As shown in FIG. 1, a MOSFET 10 as a semiconductor device has a first conductivity type (n in this embodiment). ⁺ A semiconductor substrate 11 made of silicon of the first conductivity type (an n-type in this embodiment) forming a drain region (drift layer) on one side surface of the semiconductor substrate 11. Have been. On the anti-semiconductor substrate side surface (the upper surface in FIG. 1) of the first semiconductor layer 12, a second semiconductor layer 13 of a second conductivity type (p-type in this embodiment) for forming a channel region is provided. . A third semiconductor layer 14 of the first conductivity type (n-type in this embodiment) is provided on a part of the surface layer of the second semiconductor layer 13. The third semiconductor layer 14 forms a source region. Then, a trench 15 is provided so as to reach the first semiconductor layer 12 through the third semiconductor layer 14 and the second semiconductor layer 13. The trench 15 is provided so that the planar shape of the second semiconductor layer 13 is divided into a predetermined shape such as a substantially square shape or an elongated rectangular shape to form a cell pattern.
[0021]
A gate oxide film 16 is formed on the inner wall surface of the trench 15, and a gate electrode 17 is provided from above the gate oxide film 16 so as to fill the trench 15. The gate oxide film 16 is also formed at a position covering the trench opening side portion of the gate electrode 17. An insulating layer 18 is formed to cover a portion of the gate oxide film 16 on the trench opening side.
[0022]
A source electrode 19 is formed to cover the exposed surfaces of the second semiconductor layer 13 and the third semiconductor layer 14 and the exposed portions of the gate oxide film 16 and the insulating layer 18, and the back surface of the semiconductor substrate 11. On the surface opposite to the layer 12), a drain electrode 20 is formed. A gate terminal G, a source terminal S, and a drain terminal D are connected to the gate electrode 17, the source electrode 19, and the drain electrode 20, respectively. The source electrode 19 and the drain electrode 20 are provided integrally with each cell, the gate electrode 17 of each cell is connected in common, and each cell is connected in parallel.
[0023]
The first semiconductor layer 12 and the second semiconductor layer 13 are formed so that the joint surface 21 of the two is recessed toward the portion 21 a parallel to the semiconductor substrate 11 and the side surface 15 a of the trench 15. And a portion 21b in contact with. When the distance between the opposing side surfaces 15a of the adjacent trench 15 is L1, and the distance between the boundary 21c between the portion 21a and the portion 21b of the bonding surface 21 and the side surface 15a of the trench 15 is L2, the distance L1 is the distance L2. Is formed three times or more. Further, the angle of incidence θ of the bonding surface 21 on the side surface 15a of the trench 15 is formed so as to satisfy 0 ° <θ <90 °. The “incident angle θ of the bonding surface 21 to the side surface 15 a of the trench 15” is an angle formed between a concave portion 21 b of the bonding surface 21 and a portion 21 a of the bonding surface 21 parallel to the semiconductor substrate 11. means.
[0024]
In FIGS. 1 and 2, the thickness and the size of each element constituting the MOSFET 10 are shown in a relative relationship that does not always match the actual one for convenience of illustration. For example, in practice, the thickness of the third semiconductor layer 14 is about 0.5 μm while the thickness of the gate oxide film 16 is about 0.1 μm.
[0025]
Next, an example of a method of manufacturing the MOSFET 10 having the above configuration will be described with reference to FIGS. For convenience of illustration, only one trench 15 is shown.
First, in the first semiconductor layer forming step, as shown in FIG. ⁺ A first semiconductor layer 12 of a first conductivity type (n-type in this embodiment) is formed on one side of a semiconductor substrate 11 of a first conductivity type made of silicon of the type. The first semiconductor layer 12 is directly laminated on the semiconductor substrate 11. The first semiconductor layer 12 is formed by, for example, epitaxial growth.
[0026]
Next, in a recess forming step, a recess 22 having a bottom surface 22a parallel to the surface of the semiconductor substrate 11 and a slope 22b inclined toward the bottom surface 22a is formed in the center of the surface of the first semiconductor layer 12. . More specifically, as shown in FIG. 3B, the oxide film 23 is formed on the surface of the first semiconductor layer 12 by LOCOS oxidation so that the film thickness at the position corresponding to the position where the trench 15 is formed is increased. It is formed. Next, the oxide film 23 is removed, and a concave portion 22 is formed on the surface of the first semiconductor layer 12 as shown in FIG. In the LOCOS oxidation, as shown in FIG. 1, the shape of the concave portion 22 is such that the distance L1 between the opposing side surfaces 15a of the adjacent trench 15 and the portion 21a The distance L2 between the boundary 21c with the side surface 21b and the side surface 15a is set such that L1 ≧ 3 × L2.
[0027]
Next, in a second semiconductor layer forming step, a second semiconductor layer 13 of the second conductivity type is formed on the surface of the first semiconductor layer 12. More specifically, as shown in FIG. 3C, after the surface of the first semiconductor layer 12 is doped with a second conductivity type (p-type in this embodiment) impurity (for example, boron B), Boron B is diffused to a predetermined thickness by thermal diffusion, and a second semiconductor layer 13 is formed as shown in FIG. Then, the recess 22 is formed on the surface of the second semiconductor layer 13.
[0028]
Next, in a trench forming step, as shown in FIG. 3E, a trench 15 having a depth reaching the first semiconductor layer 12 through the second semiconductor layer 13 is formed at a position corresponding to the bottom surface of the concave portion 22. It is formed. The trench 15 is formed by, for example, a dry etching method. As a result, as shown in FIG. 3E, the bonding surface 21 of the first semiconductor layer 12 and the second semiconductor layer 13 is directed toward a portion 21 a parallel to the semiconductor substrate 11 and a side surface 15 a of the trench 15. And a portion 21b formed so as to be concave and in contact with the side surface 15a of the trench 15.
[0029]
Next, in a third semiconductor layer forming step, a third semiconductor layer 14 is formed at a position along the opening of the trench 15 in the second semiconductor layer 13. Next, steps subsequent to the gate oxide film forming step are performed in the same manner as in the related art. That is, an oxide film forming step of forming a silicon oxide film on the inner surface of the trench 15 and the surface of the third semiconductor layer 14 is performed, and a silicon oxide film serving as the gate oxide film 16 is formed. After that, the gate material is buried in the trench 15 by a known method to form the gate electrode 17.
[0030]
Next, an insulating layer 18 is provided so as to cover the gate electrode 17 and a part of the gate oxide film 16. Thereafter, the source electrode 19 is formed so as to cover the entire front surface side (the upper side in FIG. 1) of the semiconductor substrate 11, and the state shown in FIG. Further, the drain electrode 20 is formed on the back surface of the semiconductor substrate 11, and the MOSFET 10 as shown in FIG. 1 is manufactured. The surface of each electrode is covered with a passivation film (not shown).
[0031]
Next, the operation of the MOSFET 10 configured as described above will be described.
When a gate voltage is applied so that the potential of the drain electrode 20 is higher than the potential of the source electrode 19 and the potential of the gate electrode 17 is higher than the potential of the source electrode 19, and the gate voltage exceeds the threshold voltage, the side surface 15a of the trench 15 A channel is formed on the surface of the second semiconductor layer 13. Then, electrons flow from the third semiconductor layer 14 through the channel into the first semiconductor layer 12 and the semiconductor substrate 11, and the MOSFET 10 is turned on.
[0032]
When a voltage is applied between the drain terminal D and the source terminal S in a state where the gate terminal G and the source terminal S are short-circuited (switch-off state), a junction surface between the first semiconductor layer 12 and the second semiconductor layer 13 is formed. The depletion layer spreads on both sides of 21. The electric field is formed such that equipotential lines are formed along the bonding surface 21, but is bent by the potential of the gate electrode 17 at the trench 15. In the case where the bonding surface 21 is formed only of a portion parallel to the semiconductor substrate 11 as in the related art, equipotential lines LV are mixed in the contact portion of the bonding surface 21 with the side surface 15a of the trench 15 and near the trench bottom. In this state, the electric field is locally concentrated (increased). As a result, breakdown easily occurs in Si, and the breakdown voltage between the drain and the source is reduced.
[0033]
However, in the present invention, there is provided a portion 21 a in which the bonding surface 21 is parallel to the semiconductor substrate 11 and a portion 21 b formed so as to be concave toward the side surface 15 a of the trench 15 and in contact with the side surface 15 a of the trench 15. That is, the bonding surface 21 is in a state where the trench 15 side extends at a gentle angle toward the bottom of the trench 15. As a result, as shown in FIG. 2, the equipotential lines are not sharply bent, the local concentration (increase) of the electric field is suppressed, and the decrease in the withstand voltage between the drain and the source is suppressed.
[0034]
When the distance L1 between the opposing side surfaces 15a of the adjacent trenches 15 is less than three times the distance L2, the width (distance) of the portion 21a between the two portions 21b of the bonding surface 21 between the adjacent trenches 15 in FIG. ) Is less than the distance L2, and the entire bonding surface 21 approaches a state where it becomes deep. As a result, the interval between the equipotential lines LV at the bottom of the trench gate is narrowed, and the effect of forming the trench 15 toward the side surface 15a is weakened.
[0035]
This embodiment has the following effects.
(1) In a semiconductor device having a vertical trench structure, a bonding surface 21 between a first semiconductor layer 12 and a second semiconductor layer 13 is directed toward a portion 21 a parallel to the semiconductor substrate 11 and a side surface 15 a of the trench 15. And a portion 21b formed so as to be depressed and in contact with the side surface 15a of the trench 15. Therefore, unlike a semiconductor device in which the entire bonding surface 21 between the first semiconductor layer 12 and the second semiconductor layer 13 is formed parallel to the semiconductor substrate 11, the electric field strength at the bottom of the trench gate is locally increased. Therefore, a decrease in the breakdown voltage between the drain and the source of the MOSFET can be suppressed.
[0036]
(2) When the distance between the opposed side surfaces 15a of the adjacent trenches 15 is L1, and the distance between the boundary 21c between the portion 21a and the portion 21b of the bonding surface 21 and the side surface 15a of the trench 15 is L2, the distance L1 Is formed at least three times the distance L2. Therefore, as compared with the case where the distance L1 between the side surfaces 15a of the trench 15 is formed to be less than three times the distance L2, the channel forming layer (the second semiconductor layer 13) and the drift layer (the first semiconductor layer). The local increase in the electric field strength at the contact portion of the bonding surface 21 of the layer 12) with the side surface of the trench and at the bottom of the trench gate is further suppressed.
[0037]
(3) The angle of incidence θ of the bonding surface 21 on the side surface 15a of the trench 15 is formed so as to satisfy 0 ° <θ <90 °. Therefore, as compared with the case where the incident angle θ is formed at 0 ° or 90 ° or more, the contact portion between the side surface 15 a of the trench 15 at the joint surface 21 of the second semiconductor layer 13 and the first semiconductor layer 12 is formed. In addition, the local increase in the electric field strength at the bottom of the trench gate is further suppressed.
[0038]
(4) An insulating layer 18 is formed on the surface of the gate oxide film 16, and a source electrode 19 is formed thereon. Therefore, even if a concave portion is formed in the trench 15, the surface becomes nearly flat in the state where the gate electrode 17 is formed, as compared with the case where the insulating layer 18 is not provided.
[0039]
(5) Since the semiconductor device is applied to the MOSFET 10, the effects (1) to (4) can be obtained in the MOSFET 10.
(6) When the MOSFET 10 is manufactured, only a step of forming the concave portion 22 on the surface of the first semiconductor layer 12 by LOCOS oxidation often used in the manufacture of a semiconductor device is added. By doing so, the MOSFET 10 is obtained. Therefore, the fabrication is simpler than the prior art in which the thickness of the gate oxide film is increased only at the bottom of the trench or an electric field relaxation semiconductor region is provided below the trench.
[0040]
(Second embodiment)
Next, a second embodiment will be described with reference to FIGS. In this embodiment, the shape of a portion 21b formed so as to be depressed toward the side surface 15a of the trench 15 and the shape of the peripheral edge on the opening side of the trench 15 are different from those of the first embodiment. Is the same. The same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0041]
As shown in FIG. 4, a portion 21 b of the bonding surface 21 between the first semiconductor layer 12 and the second semiconductor layer 13, which is formed so as to extend toward the side surface 15 a of the trench 15, It is formed on a curved surface that is convex toward the semiconductor layer 12 side. Further, the third semiconductor layer 14 is formed in parallel with the semiconductor substrate 11. When the concave portion 21b of the bonding surface 21 is a curved surface, the incident angle θ of the bonding surface 21 to the side surface 15a of the trench 15 is determined by the tangent of the portion 21b at the intersection of the portion 21b and the side surface 15a, The angle formed by the parallel portion 21a is the incident angle θ of the bonding surface 21 to the side surface 15a of the trench 15.
[0042]
Next, a method of manufacturing the MOSFET 10 will be described with reference to FIGS.
First, n ⁺ A first semiconductor layer 12 is formed on one surface of a first conductivity type semiconductor substrate 11 made of silicon of the type, and p-type implantation is performed by ion implantation at a position corresponding to a position where a trench 15 is to be formed next. The region 24 is formed, as shown in FIG. Next, as shown in FIG. 5B, the p-type impurity is entirely doped and diffused, and as shown in FIG. 5B, the portion where the trench 15 is formed is convex toward the first semiconductor layer 12 side. Is formed.
[0043]
Next, as shown in FIG. 5C, a trench 15 having a depth reaching the first semiconductor layer 12 through the second semiconductor layer 13 is formed. As a result, as shown in FIG. 5C, the bonding surface 21 of the first semiconductor layer 12 and the second semiconductor layer 13 is directed toward the portion 21a parallel to the semiconductor substrate 11 and the side surface 15a of the trench 15. And a portion 21b formed so as to be concave and in contact with the side surface 15a of the trench 15. Then, the portion 21b has a curved surface protruding toward the first semiconductor layer 12 side.
[0044]
Next, after the third semiconductor layer 14 is formed at a position along the opening of the trench 15 in the second semiconductor layer 13, a gate oxide film, a gate electrode 17, and a drain electrode 20 are formed. The MOSFET 10 as shown in FIG.
[0045]
This embodiment has the following effects in addition to the effects similar to (1) to (4) of the first embodiment.
(7) Since the portion 21b is formed on the curved surface convex toward the first semiconductor layer 12, the intervals between the equipotential lines LV are more averaged than when the portion 21b is formed in a plane. The local increase in the electric field strength at the bottom of the trench gate is further suppressed.
[0046]
The embodiment is not limited to the above, and may be configured as follows, for example.
The semiconductor device having the trench structure is not limited to the MOSFET 10 but may be applied to an IGBT. When applied to an n-channel IGBT, for example, as shown in FIG. 6, the second conductivity type (p ⁺ (Type) semiconductor substrate 11 is used. Then, the first conductivity type (n ⁺ The structure is the same as that of the MOSFET 10 except that a first conductive type (n-type) first semiconductor layer 12 having a lower impurity concentration than the semiconductor layer 25 is stacked via a semiconductor layer 25 of the same type. . However, in the case of the IGBT 26, the electrode called the source electrode 19 in the MOSFET 10 is called the emitter electrode 27, and its terminal is the emitter terminal E. An electrode called the drain electrode 20 is called a collector electrode 28, and its terminal is a collector terminal C. The source region is called an emitter region. Also in this case, the same effects as those of the above (1) to (4) can be obtained in the IGBT.
[0047]
In manufacturing the IGBT 26, for example, a first conductivity type semiconductor layer is formed on a second conductivity type semiconductor substrate, and the first conductivity type first semiconductor layer 12 having a lower impurity concentration than the semiconductor layer is formed thereon. Can be obtained by performing the steps subsequent to the concave part forming step of the manufacturing method described in the first embodiment on the laminated structure. Further, a semiconductor layer of a first conductivity type is formed on a semiconductor substrate of a second conductivity type, and a first semiconductor layer 12 of a first conductivity type having a lower impurity concentration than the semiconductor layer is formed thereon. For this, the method described in the second embodiment may be applied.
[0048]
In the above embodiments, an n-channel semiconductor device has been described, but a p-channel semiconductor device may be used. In this case, the impurities of the first conductivity type and the impurities of the second conductivity type may be used in reverse. For example, in the case of MOSFET 10, semiconductor substrate 11 is p ⁺ Type, the first semiconductor layer 12 is p-type, the second semiconductor layer 13 is n-type, and the third semiconductor layer 14 is p-type. In the case of the IGBT 26, the semiconductor substrate 11 is set to n ⁺ Mold, the semiconductor layer 25 is p ⁺ Type, the first semiconductor layer 12 is p-type, the second semiconductor layer 13 is n-type, and the third semiconductor layer 14 is p-type.
[0049]
In the case of the IGBT 26, the semiconductor layer 25 formed between the semiconductor substrate 11 and the first semiconductor layer 12 is not always necessary, and the semiconductor layer 25 may be omitted.
The planar shape of the trench 15 is not limited to a continuous lattice shape as a whole, and a plurality of trenches which are structurally separated and independent from each other may be formed.
[0050]
In the second embodiment, the p-type impurity is doped and diffused twice without using the ion implantation method, so that the portion where the trench 15 is formed protrudes toward the first semiconductor layer 12 side. The second semiconductor layer 13 may be formed.
[0051]
The invention (technical idea) grasped from the embodiment will be described below.
(1) In the invention according to any one of claims 1 to 4, in the semiconductor device, a first conductivity type semiconductor substrate is used as the semiconductor substrate, and the first semiconductor layer is formed of the semiconductor. This is a MOSFET having a configuration directly stacked on a substrate.
[0052]
(2) In the invention according to any one of claims 1 to 4, in the semiconductor device, a semiconductor substrate of a second conductivity type is used as the semiconductor substrate, and the first semiconductor layer is formed of the semiconductor. The IGBT is stacked on a substrate with a first conductivity type semiconductor layer interposed therebetween, and the first semiconductor layer has a lower impurity concentration than the semiconductor layer.
[0053]
【The invention's effect】
As described in detail above, according to the first to fourth aspects of the present invention, the electric field strength at the contact portion between the channel forming layer and the drift layer at the junction side surface and the trench gate bottom is locally reduced. It is possible to suppress an increase in the breakdown voltage and to suppress a decrease in the breakdown voltage between the drain and the source or between the collector and the emitter. According to the fifth aspect of the present invention, a semiconductor device having a vertical trench structure capable of suppressing a decrease in the breakdown voltage between the drain and the source or between the collector and the emitter as described above can be easily manufactured. can do.
[Brief description of the drawings]
FIG. 1 is a partial schematic cross-sectional view of a MOSFET according to a first embodiment.
FIG. 2 is a schematic cross-sectional view illustrating the operation.
FIGS. 3A to 3F are schematic diagrams illustrating a method for manufacturing a MOSFET.
FIG. 4 is a partial schematic cross-sectional view of a MOSFET according to a second embodiment.
FIGS. 5A to 5D are schematic diagrams illustrating a method for manufacturing a MOSFET.
FIG. 6 is a partial schematic cross-sectional view of an embodiment embodied in an IGBT.
FIG. 7A is a partial schematic cross-sectional view of a conventional MOSFET, and FIG. 7B is a schematic diagram for explaining an operation.
FIG. 8 is a schematic cross-sectional view of another conventional MOSFET.
[Explanation of symbols]
L1, L2 distance, 10 MOSFET as a semiconductor device, 11 semiconductor substrate, 12 first semiconductor layer, 13 second semiconductor layer, 14 third semiconductor layer, 15 trench, 15a side surface Reference numeral 17: gate electrode, 21: bonding surface, 21a, 21b part, 21c boundary, 22 concave part, 22a bottom surface, 22b inclined part, 23 oxide film, 26 IGBT as a semiconductor device.

Claims (5)

A semiconductor substrate, a first semiconductor layer of a first conductivity type provided on one side of the semiconductor substrate, and a second conductivity type for forming a channel region provided on a side of the first semiconductor layer opposite to the semiconductor substrate. A second semiconductor layer, and a third semiconductor layer of a first conductivity type provided in a part of a surface layer portion of the second semiconductor layer, wherein the third semiconductor layer and the second semiconductor layer are provided. A semiconductor device having a vertical trench structure including a trench provided so as to reach the first semiconductor layer through the first semiconductor layer, wherein a junction surface between the first semiconductor layer and the second semiconductor layer is A semiconductor device having a trench structure including a portion parallel to the semiconductor substrate and a portion formed so as to be depressed toward a side surface of the trench and in contact with the side surface of the trench. The distance between the opposing side surfaces of the adjacent trenches is L1, and a boundary between a portion of the junction surface parallel to the semiconductor substrate and a portion formed to be recessed toward the side surface of the trench and a side surface of the trench. 2. The semiconductor device having a trench structure according to claim 1, wherein when the distance is L2, the distance L1 is formed to be three times or more the distance L2. 3. The semiconductor device having a trench structure according to claim 2, wherein an incident angle θ of the junction surface to a side surface of the trench satisfies 0 ° <θ <90 °. 4. The part formed so that it may be depressed toward the side of the trench is formed in the curved surface which becomes convex toward the 1st semiconductor layer side. Semiconductor device having a trench structure. A first semiconductor layer forming step of forming a first semiconductor layer of the first conductivity type on one side of the semiconductor substrate;
After forming an oxide film on the surface of the first semiconductor layer by LOCOS oxidation so as to increase the film thickness at a position corresponding to the position where the trench is formed, the first film is removed by removing the oxide film. A concave portion forming step of forming a concave portion having a bottom surface parallel to the surface of the semiconductor substrate at the center and having a slope inclined toward the bottom surface on the surface of the semiconductor layer;
Forming a second semiconductor layer of a second conductivity type on a surface of the first semiconductor layer after the formation of the concave portion;
Forming a trench having a depth reaching the first semiconductor layer through the second semiconductor layer at a position corresponding to the bottom surface of the concave portion;
A third semiconductor layer forming step of forming a first conductive type third semiconductor layer on a surface layer of the second semiconductor layer, which is performed after or before the trench forming step; A method for manufacturing a semiconductor device having a trench structure in which a step after a gate oxide film forming step is performed after a third semiconductor layer forming step.

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