JP2004213895A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption of a power supply circuit of a semiconductor memory and to reduce an active standby current in particular. <P>SOLUTION: A plurality of memory banks that can be respectively and independently activated by an activation command and a plurality of power supply circuits provided respectively corresponding to the memory banks to respectively receive external power source voltage and output a prescribed internal power source voltage are provided. Outputs of the power supply circuits are respectively connected to corresponding memory banks, a power supply circuit provided in accordance with a corresponding bank among the power supply circuits are turned on in a response to a command for activating one of the memory banks, and the other power supply circuits are turned off. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a power supply circuit of a semiconductor memory, and more particularly to a control method suitable for low power consumption.

  A so-called on-chip voltage limiter system (step-down system) that generates an internal voltage obtained by stepping down an external power supply voltage on a semiconductor chip and uses the generated internal voltage as a power supply is widely used in semiconductor memories and the like. This is to reduce the current consumption of the circuit or to ensure the reliability of the fine element. A circuit that generates an internal power supply voltage for this purpose is a voltage limiter circuit (step-down circuit).

  The voltage limiter circuit consumes a steady current to maintain the output voltage level even when the semiconductor memory is in a standby state. As one of the methods for reducing current consumption during standby, [Document 1] is provided in common with eight voltage limiter circuits, two in each of four memory cell arrays, and a total of eight voltage limiter circuits. One common voltage limiter circuit is described (FIG. 3 of [Document 1]). The common voltage limiter circuit is always operated, and the eight voltage limiter circuits are controlled so that when memory access is performed, eight start simultaneously and four operate after a predetermined period has elapsed.

[Document 2] describes first and second voltage limiters provided corresponding to the first and second banks and their operation timings. When the activation of the first bank is instructed, the first voltage limiter generates an internal voltage, and when the activation of the second bank is continuously instructed while the first bank is activated, the second voltage limiter also becomes the first voltage. It is described that an internal voltage is generated in combination with a voltage limiter (FIG. 12 of [Document 2]).
JP-A-7-105682 JP-A-9-161481.

  Prior to the present application, the inventors of the present application examined current consumption in an active standby state of an SDRAM (synchronous dynamic random access memory). The active standby state in the SDRAM is a state in which a memory bank is activated, data of a specific word is held in a sense amplifier, and a read / write command is not applied in preparation for a memory access. Reading data from a dynamic memory cell takes a relatively long time, whereas once held in a sense amplifier, the data held in the sense amplifier is as if it were a single column of SRAM (static random access memory). ), It is possible to read at high speed.

  After the bank activation command is applied in order to enter the active standby state, a large current flows because the word line is selected and the sense amplifier operates. It is. However, if there is a voltage limiter circuit, current consumption will flow. At this time, if both the circuit for standby and the circuit for operation are operating, the current consumption of the voltage limiter is considerably large (usually several mA to several tens mA). In particular, in the case of synchronous DRAM, in order to take advantage of high-speed data transfer, it is often used to activate a bank in advance and leave it unattended. Therefore, the active standby current greatly affects the current consumption of the entire system.

  In the configuration of [Document 1] described above, since operation dependent on banks specific to SDRAM is not taken into account, as many as eight voltage limiter circuits operate at the same time, and the peak operating current becomes too large. Not considered. Even in the active standby state, as many as four (five if the common voltage limiter circuits are included) voltage limiter circuits operate, and the active standby current becomes unnecessarily large.

  Further, in [Literature 2], the active standby state is not considered, and when a plurality of memory banks are activated one after another, the corresponding voltage limiter circuits operate additively, and the plurality of memory banks are activated in the active standby state. It does not take into account that the operating current of the limiter circuit is unnecessarily added when the state is set. This becomes a serious problem, especially when the number of banks is large.

  A typical configuration for solving the above problem is as follows. That is, the first and second memory banks activated by the first and second commands, respectively, are wired across the first and second memory banks, and supply a predetermined voltage to the first and second memory banks. And a first and second power supply circuit provided corresponding to each of the first and second memory banks, and each output node is coupled to the power supply wiring to generate the predetermined voltage. The first power supply circuit starts generating the predetermined voltage in response to the first command, and when the second command is input while maintaining the active state of the first memory bank, The first power supply circuit stops generating the predetermined voltage in response to the second command, and the second power supply circuit starts generating the predetermined voltage in response to the second command.

  According to the present invention, the current consumption of the on-chip voltage limiter circuit in the active standby state can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The circuit elements constituting each block of the embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (complementary MOS transistor). A circuit symbol of a MOSFET without an arrow indicates an N-type MOSFET (NMOS) and is distinguished from a P-type MOSFET (PMOS) with an arrow.

[Example 1]
FIG. 1 shows a synchronous DRAM of a 4-bank configuration to which the present invention is applied. In the figure, CHIP is a semiconductor memory chip, BANK0 to BANK3 are memory banks, CKT is a peripheral circuit common to all banks, VDL0 to VDL3 and VDLS are an internal power supply voltage VDL (first internal voltage) for a memory array from an external power supply VDD. A voltage limiter circuit (or a step-down circuit, more generally a power supply circuit) for generating, and VCL4 to VCL6 and VCLS are voltage limiter circuits for generating an internal power supply voltage VCL (second internal voltage) for peripheral circuits from VDD. It is. As an example of the voltage value, VDD = 3.3 V, VCL = 2.2 V, and VDL = 1.8 V. That is, two types of internal voltages VCL and VDL generated from the external power supply voltage VDD and having a lower voltage than VDD are supplied to the internal circuit block. VDL is set to a voltage lower than VCL.

  CTL0 is a control circuit for controlling VDL0 to VDL3, and CTL1 is a control circuit for controlling VCL4 to VCL6. CTL0 and CTL1 are located in CKT. In addition, a bonding pad, an input buffer, an output buffer, a main control circuit (described later), a main amplifier, a refresh counter, and the like are arranged in the CKT. Although not particularly limited, the input buffer and the output buffer operate on the power supply voltage VDD supplied from the outside.

  FIG. 2 shows an example of the configuration of each bank. In the figure, MA is a memory array in which memory cells are arranged in a matrix, SC is a sense circuit, SWD is a sub-word line driver, IS is a region at the intersection of a sense amplifier and a sub-word line driver. A drive circuit is provided.

  The first internal voltage VDL is used as a power supply of a sense amplifier driving circuit. The VDL wiring is arranged in a mesh on the memory array using second and third layer metals to reduce parasitic resistance. The VDL is wired over BANK0 to BANK3 as shown in FIG. VDL is also supplied to a VDL / 2 generation circuit (not shown) that generates a voltage half of VDL. The voltage VDL / 2 is used as a power supply for precharging the plate electrode of the memory cell and the bit line as described later.

  On the other hand, the second internal voltage VCL is supplied to the row decoders XD0 and XD1, the column decoders YD0 and YD1, the bank-dedicated peripheral circuit BCKT, and the common peripheral circuit CKT. The peripheral circuit BCKT dedicated to the bank includes an address latch, a predecoder, and the like. Since the row decoder, the column decoder, and the peripheral circuits BCKT and CKT operate using the VCL as a power supply, the wiring of the VCL passes through these circuits. The wiring of the VCL is also wired across BANK0 to BANK3 as shown in FIG. Of the circuits included in the common peripheral circuit CKT, the input buffer and the output buffer operate at VDD as described above, but most of the other circuits use VCL lower than VDD as a power supply to reduce power consumption. Operate. For example, the main control circuit, main amplifier, refresh counter, and control circuits CTL0 and CTL1 also operate using VCL as a power supply.

FIG. 3 shows details of the memory array MA, the sense circuit SC, and the sense amplifier drive circuit IS. At the intersection of the sub-word line SWL and the bit line pair BL, / BL, a dynamic memory cell MC including a capacitor connected to one end of the source / drain path of the switch MOSFET is arranged in a well-known folded data line pair system. . VDL / 2 is commonly supplied to the plate electrode, which is the other end of the capacitor. The sense circuit section includes a sense amplifier SA (two cross-coupled COMS inverters) for amplifying the signal voltage on the bit line pair, and a bit for precharging the bit line pair to the level of 1/2 of VDL. A line precharge circuit PC and the like are arranged. A pair of signal lines NCS and PCS for driving the sense amplifier SA are wired to the sense amplifier drive circuit. A precharge circuit CSPC similar to the bit line precharge circuit is provided between the signal lines NCS and PCS, and VDL / 2 is supplied. The sense amplifier drive circuit IS includes three MOS transistors MN1 to MN3.

  When neither the NCS nor the PCS performs an amplification operation, the CSPC is precharged to half the level of VDL by the CSPC. When performing the amplification operation, first, MN1 and MN2 are turned on. As a result, the NCS and the ground are connected, and the PCS and the external power supply VDD are connected, respectively, so that the potential of the NCS decreases and the potential of the PCS increases. When the potential of the PCS rises to near the VDL level, MN2 is turned off and MN3 is turned on. As a result, the PCS and the internal power supply VDL are connected. Eventually, NCS = 0 V and PCS = VDL, one of the bit line pairs becomes 0 V and the other becomes the VDL level, and the amplification operation is completed. The reason why the PCS is once connected to VDD without being connected to VDL from the beginning is to speed up the amplification operation and to reduce the load on the VDL voltage limiter circuit. This is a technique called overdrive.

  FIG. 4 shows a connection relationship between the respective circuits. Voltage limiter circuits VDL0 to VDL3 and VDLS that generate first internal voltage VDL generate internal power supply voltage VDL with reference to reference voltage VRD generated by reference voltage generation circuit RVG (not shown in FIG. 1). . Among them, the VDLS is a circuit that is constantly operating and has a small current supply capability but a small current consumption. VDL0 to VDL3 are circuits that consume relatively large current and have a large current supply capability, and are turned on / off by activation signals LD0 to LD3 generated by the control circuit CTL0. The size of the box representing the limiter circuit in FIG. 4 indicates the magnitude of the current supply capability of each limiter circuit. As shown in FIGS. 1 and 2, the outputs of VDL0 to VDL3 and VDLS form a second layer (solid line in FIGS. 1 and 2) and a third layer metal wiring (dotted line in FIGS. 1 and 2) on the memory array. They are arranged vertically and horizontally and connected.

  Voltage limiter circuits VCL4 to VCL6 and VCLS for generating second internal voltage VCL generate internal power supply voltage VCL with reference to reference voltage VRC generated by reference voltage generation circuit RVG. Among them, the VCLS is a circuit that is constantly operating and has a small current supply capability but a small current consumption. VCL4 to VCL6 are circuits that consume a relatively large amount of current and have a large current supply capability. VCL4 is turned on / off by an activation signal LC4 generated by the control circuit CTL1, and VCL5 and VCL6 are turned on / off by an activation signal LC5. The outputs of VCL4 to VCL6 and VCLS are also connected.

  The main control circuit CTLM (omitted in FIG. 1) includes a clock signal CLK, a chip select signal / CS (a shaded "/" in front of a signal name indicates a complementary signal), a row address strobe / RAS, and a column. A circuit that receives signals such as an address strobe / CAS, a write enable signal / WE, and a clock enable signal CKE, interprets a command, and sets an operation mode. In the synchronous DRAM, a method of designating a command by a combination of signals such as / CS, / RAS, / CAS, / WE, and CKE at the rising edge of the clock signal CLK is standardized, and this embodiment is also standardized. Follow the method.

  The features of this embodiment are that the outputs of a plurality of voltage limiters are connected to each other, and that each circuit is finely turned on / off depending on the operation mode of the memory as described below.

  Next, the control circuit CTL0 will be described with reference to the circuit diagram of FIG. 5 and the operation waveform diagrams of FIGS. The input signals BA0 to BA3 are bank active signals, which are "1" when the memory banks 0 to 3 are activated and "0" when they are inactive. SDRAM standardized bank active command ACTV consists of / CS = L, / RAS = L, / CAS = H, / WE = H, row address (address to specify word line), bank address (to specify bank number) Address). More general activation of a bank is an operation of designating the location of a bank and one word in the bank, reading the data of one word into a plurality of corresponding sense amplifiers, and latching the data. RF is a refresh signal, and becomes "1" when the memory is being refreshed. As described above, the output signals LD0 to LD3 are signals for turning on / off the VDL limiter circuits VDL0 to VDL3, respectively (ON when "1", OFF when "0").

  FIG. 6 is an operation waveform diagram in the case of normal operation. At times t0, t1, t2, and t3, activation commands (ACTV 0, ACTV 1, ACTV 2, and ACTV 3) for bank 0, bank 1, bank 2, and bank 3 are input, and at time t4, all banks are precharged. This is a waveform when a command (PRE ALL) is input. When PRE ALL is input, all banks are deactivated, and the data line pairs and sense amplifier drive line pairs in each bank are precharged to the precharge potential VDL / 2. In an actual use state, a read or write command is usually input between activation of the bank and precharge, but is omitted here for simplicity. First, when BA0 becomes "1", the signal OS0 becomes "0" for a predetermined time by the operation of the inverter 100-0 and the one-shot pulse generation circuit 101-0. As a result, the output LT0 of the latch constituted by the NAND gates 103-0 and 104-0 becomes "1", and the output signal LD0 becomes "1". Next, when BA1 becomes "1", the signal OS1 becomes "0" for a predetermined time. As a result, the output LT1 of the latch constituted by the NAND gates 103-1 and 104-1 becomes "1", and LT0 becomes "0". The output signal LD1 becomes "1", and LD0 becomes "0" with a delay of a predetermined time by the operation of the delay circuit 105-0. Next, when BA2 becomes "1", similarly, the output signal LD2 becomes "1", and LD1 becomes "0" with a delay of a predetermined time. Next, when BA3 becomes "1", similarly, the output signal LD3 becomes "1", and LD2 becomes "0" with a delay of a predetermined time. Finally, when BA0 to BA3 all become "0" at time t4, the output IDB of the OR gate 106 becomes "0", so that the signal LT3 which has been "1" until this time becomes "0". The output signal LD3 becomes "0" with a delay of a predetermined time.

  As is apparent from the above description, each of the voltage limiter circuits VDL0 to VDL3 is turned on when an activation command of a memory bank near the input is input, and turned off when an activation command of another bank is input. become. Immediately after the bank activation command is input, a large current flows because the sense amplifier operates. The current flowing during this period is supplied from a voltage limiter circuit near the bank. Since only the current for maintaining the voltage level flows after the operation of the sense amplifier, a sufficient current can be supplied from a circuit far from the bank or a voltage limiter circuit VDLS for standby. This is because the outputs of the voltage limiter circuits are connected as described above. By adopting such a control method, even if a plurality of memory banks are activated, most of the time zones are turned on (although two or more voltage limiter circuits may be turned on temporarily). There is only one voltage limiter circuit except for VDLS. Of course, even in the active standby state, only one voltage limiter circuit is turned on except for VDLS. Therefore, current consumption during active standby can be significantly reduced as compared with the conventional method in which all voltage limiter circuits are turned on during operation. Synchronous DRAMs are often used to activate and leave the banks in advance in order to take advantage of high-speed data transfer, so reducing the active standby current greatly contributes to reducing the current consumption of the entire system.

  The reason why each voltage limiter circuit is turned off after a predetermined time without being turned off immediately when an activation command of another bank is input is as follows. As described above, immediately after the bank activation command is input, a large current flows. The time during which the large current flows varies depending on the process technology and design used, but is about 10 to 30 ns. On the other hand, the interval at which the bank activation command is continuously input is determined by the specifications of the synchronous DRAM, and is usually two clock cycles. For example, if the clock frequency is 100 MHz, it is 20 ns. Therefore, when the activation command of bank 1 is input two clock cycles after the activation command of bank 0 is input, a large current may still flow through bank 0. If the voltage limiter circuit VDL0 is immediately turned off here, the large current will be supplied from the circuit VDL1 far from the bank 0, which may cause malfunction or operation delay due to a voltage drop due to wiring resistance, which is not preferable.

  FIG. 7 shows operation waveforms at the time of refresh (auto-refresh represented by a standardized SDRAM command REF). When the auto-refresh command is input, all banks are activated at the same time, and a word line indicated by a refresh counter is activated for each bank to refresh one word of memory cells. When the refresh command (REF) is input at time t5, all the bank active signals BA0 to BA3 and the refresh signal RF become "1". Thereby, the outputs LT0 to LT3 of the latch become "1", and the output signals LD0 to LD3 become "1". When the refresh operation is completed inside the chip (in this case, there is no need to input a command), the signals RF and BA0 to BA3 become "0", the output IDB of the OR gate 106 becomes "0", and the latch output LT0 to LT3 become "0", and the output signals LD0 to LD3 become "0" with a delay of a predetermined time. That is, at the time of refresh, the voltage limiter circuits VDL0 to VDL3 are simultaneously turned on. This is because all banks operate simultaneously at the time of refresh, so that four times the current during normal operation can be supplied. The standby-time voltage limiter circuit VDLS is always on.

  Next, the control circuit 51 will be described with reference to the circuit diagram of FIG. 8 and the operation waveform diagrams of FIGS. The input signal CKE is a clock enable signal input from the outside. PDMB is a signal that becomes “0” in a power-down mode or a self-refresh mode described later, and becomes “1” in other cases. RF is a refresh signal, and becomes "1" when the memory is being refreshed. BA is a signal that becomes "1" when a bank active command is input. RD and WR are signals which become "1" in the read mode and the write mode, respectively. The output signal LC4 is a signal for turning on / off the VCL limiter circuit VCL4 as described above (on when "1", off when "0"). The output signal LC2 is a signal for turning on / off the VCL limiter circuits 40 and 42 as described above (on when "1", off when "0").

  FIG. 9 is an operation waveform diagram in the case where bank 0 is activated and data is read. When the activation command of bank 0 (ACTV 0) is input at time t6, the signal BA becomes "1" only while the command is input, and the output DLY1 of the delay circuit 106 becomes "1" for a predetermined time. become. Next, when a read command (READ 0) of the bank 0 is input at time t7, the read mode is entered, the signal RD becomes "1", and the output DLY2 of the delay circuit 108 also becomes "1". When a precharge command (PRE 0) for bank 0 is input at time t8, RD becomes "0", and DLY2 also becomes "0" with a slight delay. Since the output signal LC5 is the OR of DLY1 and DLY2, it becomes "1" immediately after the input of the bank activation command and in the read mode. The output signal LC4 is always "1" because the clock enable signal CKE is "1".

  Therefore, immediately after the bank activation command is input and in the read mode, all of the voltage limiter circuits VCL4 to VCL6 and VCLS are turned on. In other cases, only VCL4 and VCLS are turned on and VCL5 and VCL6 are turned off. Immediately after the input of the bank activation command, a large current flows because the address buffer and the row decoder operate. Also, in the read mode, a large current flows because the column decoder, the main amplifier, the output buffer, and the like operate. Therefore, during these periods, all the voltage limiter circuits are turned on so that a large current can be supplied. Since the current flowing in other periods is small, some circuits are turned off. That is, the operation periods of VCL5 and VCL6 are set to be almost the same as the operation periods of the row decoder, column decoder, and the like that operate in association with bank activation and reading, or to be slightly longer with some allowance. By employing such a control method, only one voltage limiter circuit is turned on in the active standby state (between the activation of the bank and the read command) except for the VCLS. Therefore, current consumption during active standby can be significantly reduced as compared with the conventional method in which all voltage limiter circuits are turned on during operation.

  The above is the case of reading, but in the case of writing, the operation is the same except that WR is set to "1" instead of the signal RD, and the active standby current is similarly reduced. Can be.

  FIG. 10 shows operation waveforms at the time of refresh (auto refresh). As in the case of FIG. 7, when the refresh command (REF) is input at time t5, the refresh signal RF becomes "1" only while the refresh operation is being performed. The output signal LC5 becomes "1" for a predetermined time from the rise of RF, and thereafter becomes "0" by the operation of the one-shot pulse generation circuit 114 and the delay circuit 116. Since the clock enable signal CKE is "1", the output signal LC4 is always "1". Therefore, immediately after the start of the refresh operation, the voltage limiter circuits VCL4 to VCL6 and VCLS are all turned on, and thereafter, VCL5 and VCL6 are turned off. Immediately after the start of the refresh operation, a large current flows because the row decoder and the like operate. Therefore, during this period, all the voltage limiter circuits are turned on so that a large current can be supplied. Since little current flows thereafter, some circuits are turned off to reduce current consumption.

  FIG. 11 shows operation waveforms in the power down mode. The power down mode is a low power consumption mode corresponding to a normal DRAM standby state (a state in which all data lines are precharged to VDL / 2). A method of designating the start / end of the power-down mode by the clock enable signal CKE or the like is standardized, and the present embodiment also follows the standardized method. When the power down mode start command (PDM Entry) is input at time t9, the signal PDMB becomes "0", and the output signal LC4 becomes "0". At time t10, a power-down mode end command (PDM Exit) is input. Since signal CKE has been set to "1" prior to that, LC4 is set to "1" at this time. Since both LC4 and LC5 are "0" during the power down mode, all the voltage limiter circuits VCL4 to VCL6 are turned off, and only the standby voltage limiter circuit VCLS is turned on. Therefore, current consumption during the power down mode is extremely small.

  Although the falling of the signal LC4 is determined by the PDMB, the rising is determined by the CKE for the following reason. According to the synchronous DRAM standard, the end of the power down mode is designated by setting CKE to "1" at the rising edge of the clock signal CLK. CKE must be set to "1" before the rise of CLK by the setup time (usually 2-3 ns). Therefore, the end of the power down mode is determined by CKE, and the rise of LC4 can be made faster than by PDMB. Since a command such as bank active may be input in the clock cycle following the power down mode end command, it is desirable to turn on the voltage limiter VCL4 early in preparation for this.

  FIG. 12 shows operation waveforms in the self-refresh mode. When a self-refresh command is input, the SDRAM periodically performs refreshing by an internal timer until a self-refresh end command is input. When the self-refresh mode start command (SELF Entry) is input at time t11, the signal PDMB becomes "0", and the output signal LC4 becomes "0". When the refresh operation is started at time t12 by the timer provided on the chip, the signal RF becomes "1". The output signal LC4 is "1" while RF is "1". The output signal LC5 becomes "1" for a predetermined time from the rise of RF. At time t13, a self-refresh mode end command (SELF Exit) is input. Since signal CKE has been set to "1" prior to that, LC4 is set to "1" at this time. Therefore, in the self-refresh mode, the voltage limiter circuits VCL4 to VCL6 are turned on when the refresh operation is actually performed, but are turned off in other time zones. The interval at which the refresh operation is performed is usually several tens to several hundreds of μs, and one refresh operation is completed in several tens of ns. Therefore, the time during which the refresh operation is performed is 0.1% or less of the entire time. In most other time zones, the voltage limiter circuits VCL4 to VCL6 are all off and only the standby voltage limiter circuit VCLS is on, so that the current consumption in the self-refresh mode is extremely small.

  FIG. 13 shows an example of the VCL voltage limiter circuit. This circuit comprises a differential amplifier DA and an output stage FS. The differential amplifier DA is activated when the activation signal LCi is "1" (high level), and outputs a voltage VFB obtained by dividing the output voltage VCL by two P-channel MOS transistors M19 and M20 and a reference voltage VRC. Compare. The output PG is input to the gate of the P-channel MOS transistor M16 in the output stage. When the potential of VCL decreases, the potential of PG decreases, M16 turns on, and charge is supplied from VDD to VCL. When the potential of VCL rises excessively, charges are discharged through a leak circuit including N-channel MOS transistors M17 and M18. When the activation signal LCi is "0" (low level), the N-channel MOS transistor M1 is turned off, the P-channel MOS transistors M8, M9, M15 are turned on, and the N-channel MOS transistor M14 is turned on. As a result, the P-channel MOS transistors M4 to M7 and the N-channel MOS transistors M12 and M13 are turned off, so that all the current flowing through the differential amplifier DA is cut off. Further, the output stages M16 and M18 are also turned off. Therefore, the consumed current is only the current flowing through the voltage dividing circuits M19 and M20, which is extremely small as compared with the operating state. The reason why the current always flows through M19 and M20 is to stably maintain the level of voltage VFB in preparation for the next operation of differential amplifier DA.

  FIG. 14 is an example of the VDL voltage limiter. The difference from the circuit of FIG. 13 is that the function of discharging electric charge when the potential of the output voltage VDL rises excessively is enhanced. The differential amplifier DA has two outputs PG and NG. PG is input to a P-channel MOS transistor M16, as in the circuit of FIG. 13, while NG is input to the gate of an N-channel MOS transistor M25. If the potential of VDL rises too much, the potential of NG rises and the charge of VDL is discharged through M25. When the overdrive method (see FIG. 3) is used, there is a possibility that the potential of VDL is excessively increased. Although the present embodiment has been described using four banks as an example, the number of banks may be an integer, but more preferably a power of two such as 2, 4, 8, 16, 32. The remaining embodiments also take a four-bank configuration as an example, but the number of banks is not limited to four.

  By making the number of voltage limiter circuits (except for the standby state) generating the first internal voltage VDL equal to the number of banks (four in this embodiment), the above-described control can be performed. On the other hand, the number of voltage limiter circuits for generating the second internal voltage VCL (except for the standby state) is three in this embodiment, but may be two or more. That is, it is only necessary that at least one circuit is controlled by each of the control signals LC4 and LC5. The stand-by voltage limiter circuit may be at least one for each of the VDL and VCL, but is desirably one for reducing standby current consumption.

[Example 2]
Next, a second embodiment of the present invention will be described. The arrangement of the circuits is the same as that of FIG. 1 and is omitted here, and FIG. 15 shows the connection relationship between the circuits. The difference from FIG. 4 is that the voltage limiter circuits VDL0 and VDL1 are collectively controlled by an activation signal LD0. Similarly, VDL2 and VDL3 are controlled by the activation signal LD2.

  FIG. 16 shows a circuit diagram of the control circuit CTL0, and FIG. 17 shows operation waveforms. As in the case of FIG. 6, at times t0, t1, t2, and t3, the activation commands of bank 0, bank 1, bank 2, and bank 3 are input, and at time t4, the all-bank precharge command is input. It is a waveform in the case. First, when BA0 becomes "1", as in the case of FIG. 6, the signal OS0 becomes "0" for a predetermined time, and the output LT0 of the latch constituted by the NAND gates 103-0 and 104-0 becomes "0". The output signal LD0 becomes "1". Next, when BA1 becomes "1", the signal OS1 becomes "0" for a predetermined time, but at this time, the outputs LT0 and LT2 of the latch do not change. Next, when BA2 becomes "1", the signal OS2 becomes "0" for a predetermined time. As a result, the output LT2 of the latch constituted by the NAND gates 103-2 and 104-2 becomes "1", and LT0 becomes "0". The output signal LD2 becomes "1", and the output signal LD0 becomes "0" after a predetermined time delay due to the operation of the delay circuit 105-0. Next, when BA3 becomes "1", the signal OS3 becomes "0" for a predetermined time, but at this time, the outputs LT0 and LT2 of the latch do not change. Finally, when BA0 to BA3 all become "0" at time t4, the output IDB of the OR gate 106 becomes "0", so that the signal LT2 which has been "1" until this time becomes "0". The output signal LD2 becomes "0" with a delay of a predetermined time.

  It should be noted that the voltage limiter circuits VDL0 and VDL1 are always turned on / off at the same time, and thus may be combined into one circuit. The same applies to VDL2 and VDL3.

  In the present embodiment, since two voltage limiters are collectively controlled by one activation signal, two voltage limiters other than the VDLS are turned on in almost all time zones. Therefore, although the current consumption reduction effect is inferior to that of the first embodiment, there are advantages that the control circuit is simplified and the number of activation signals is reduced. This is particularly effective when the number of banks is large. For example, in the case of a memory having 16 banks, if one voltage limiter circuit is individually controlled in each bank, 16 activation signals are required. The activation signal is sufficient.

  Since the control circuit CTL1 is the same as that of the first embodiment (FIG. 8), the description is omitted.

  In the present embodiment, the number of VDL voltage limiter circuits (except for the standby state) is set to four, which is the same as the number of banks. However, VDL0 and VDL1 are controlled by the same control signal LD0 and are turned on / off at the same time. It is good also as one circuit collectively. The same applies to VDL2 and VDL3. When the circuits controlled by the same control signal are combined into one, the number of VDL voltage limiter circuits is a divisor of the number of banks.

[Example 3]
FIG. 18 shows a third embodiment of the present invention. The difference from FIG. 1 is that a voltage limiter circuit VDL4 for VDL is added. This circuit is controlled by the activation signal LC4 as shown in FIG.

  FIG. 20 is a circuit diagram of the control circuit CTL0, and FIG. 21 is an operation waveform thereof. 6 and 17, at time t0, t1, t2, and t3, the activation commands of bank 0, bank 1, bank 2, and bank 3 are input, respectively. At time t4, the all-bank precharge command is issued. This is a waveform when input. First, when BA0 becomes "1", the output OS10 of the one-shot pulse generation circuit 108-0 becomes "1" for a predetermined time. As a result, the output signal LD0 becomes "1", and becomes "0" after a predetermined time delay due to the operation of the delay circuit 105-0. Similarly, when BA1, BA2 and BA3 become "1", LD1, LD2 and LD3 respectively become "1" for a predetermined time. On the other hand, LC4 is always "1" here.

  Therefore, each of the voltage limiter circuits VDL0 to VDL3 is turned on only immediately after the activation command of a memory bank near the voltage limiter circuit is input, and VDL4 is always on. Immediately after the bank activation command is input, a large current flows because the sense amplifier operates. The current flowing during this period is mainly supplied from a voltage limiter circuit near the bank. Since the current flowing after the operation of the sense amplifier is small, it can be sufficiently supplied from VDL4 or VDLS. By adopting such a control method, even if a plurality of memory banks are activated, most of the time zones are turned on (although two or more voltage limiter circuits may be turned on temporarily). The only voltage limiter circuits are VDLS and VDL4. Of course, even in the active standby state, the only voltage limiter circuits that are turned on are VDLS and VDL4. Therefore, current consumption during active standby can be significantly reduced as compared with the conventional method in which all voltage limiter circuits are turned on during operation.

  As is clear from the above description, the current supply capability of the voltage limiter circuit VDL4 may be smaller than VDL0 to VDL3. However, it is desirable to be larger than VDLS. This is because, in the write mode, a current for inverting the potential of the bit line pair flows, and this current is supplied from VDL4 (because VDL0 to VDL3 are off). Since VDL4 is controlled by the activation signal LC4, it is turned off in the power-down mode or the self-refresh (see FIGS. 11 and 12).

  An advantage of this embodiment is that the control circuit CTL0 is simplified. This is clear when FIG. 20 is compared with FIG. 5 and FIG.

  Since the control circuit CTL1 is the same as that of the first embodiment (FIG. 8), the description is omitted.

  In the case of this embodiment, when the number of banks is changed, the number of VDL voltage limiter circuits (except for the standby state) may be at least the number of banks + 1. That is, there is one circuit corresponding to each bank and one or more circuits controlled by LC4.

[Example 4]
FIG. 22 shows a fourth embodiment of the present invention. The feature of this embodiment is that the same control method as that for VDL (third embodiment) is applied to the voltage limiter circuit for VCL. The voltage limiter circuit for VCL is arranged one by one (VCL0 to VCL3) near each bank, and the VCL4 and the standby VCLS are arranged in the center. FIG. 4 shows a connection relationship between the respective circuits. The VDL voltage limiter circuits VDL0 to VDL4 are controlled by activation signals LD0, LD1, LD2, LD3, and LC4, respectively, as in the third embodiment (FIG. 19). The VCL voltage limiter circuits VCL0 to VCL4 are controlled by activation signals LC0, LC1, LC2, LC3, and LC4, respectively.

  Since the control circuit CTL0 is the same as that of the third embodiment (FIG. 20), description thereof will be omitted, and the control circuit CTL1 will be described with reference to the circuit diagram of FIG. As in the case of FIG. 9, this is a case where bank 0 is activated and data is read. First, at time t6, when the bank 0 activation command is input and the signal BA0 becomes "1", the output OS20 of the one-shot pulse generation circuit 120-0 becomes "1" for a predetermined time. As a result, the output signal LC0 becomes "1", and becomes "0" after a predetermined time delay due to the operation of the delay circuit 122-0. Next, when a read command for the bank 0 is input at time t7, the read mode is entered, so that the signal RD becomes "1", and the output signals LC0 to LC3 all become "1". When a precharge command (PRE 0) for bank 0 is input at time t8, RD becomes "0", and LC0 to LC3 also become "0" with a slight delay. The output signal LC4 is always "1" because the clock enable signal CKE is "1".

  Therefore, immediately after the bank activation command is input, the voltage limiter circuits VCL0, VCL4, and VCLS are turned on.In the read mode, a large current flows immediately after VCL0 to VCL4 and VCLS are all turned on and in the read mode. In the period, the number of voltage limiter circuits to be turned on is increased to supply a large current. Since the current flowing in other periods is small, the number of voltage limiter circuits to be turned on is reduced. With such a control method, only the voltage limiter circuits VCL4 and VCLS are on in the active standby state (between the activation of the bank and the read command). Therefore, current consumption during active standby can be significantly reduced as compared with the conventional method in which all voltage limiter circuits are turned on during operation.

  As is clear from the above description, the current supply capability of the voltage limiter circuit VCL4 may be smaller than VCL0 to VCL3. However, it is desirable to be larger than VCLS. This is because only a part of the circuits (such as the input buffer for the clock signal CLK) is operating in the active standby state. Since VCL4 is controlled by the activation signal LC4, it is turned off in the power down mode or the self refresh (see FIGS. 11 and 12).

  The above is the case of reading, but in the case of writing, the operation is the same except that WR is set to "1" instead of the signal RD, and the active standby current is similarly reduced. Can be.

  In the case of the present embodiment, the number of voltage limiter circuits (except for the standby state) for VDL and VCL may be equal to or more than the number of banks +1. That is, there is one circuit corresponding to each bank and one or more circuits controlled by LC4.

[Example 5]
FIG. 26 shows a fifth embodiment of the present invention. The difference from the first embodiment is that a dedicated internal power supply voltage VII is generated for the input buffer, and the levels of the memory array internal power supply voltage VDL and the peripheral circuit internal power supply voltage VCL are equal. As an example of the voltage value, VDD = 3.3 V, VCL = VDL = 1.8 V, and VII = 2.5 V. The input buffer satisfies standards such as high level VIH and low level VIL of the input signal, so that it is desirable that the power supply voltage is stable. Therefore, a dedicated power supply is generated by the voltage limiter circuits VII0 to VII2 and VIS. As described above, since the input buffer is arranged in the peripheral circuit CKT, the wiring of VII passes through the CKT.

  FIG. 27 shows the connection relationship between the circuits. Since the outline is the same as that of the first embodiment (FIG. 4), only different points will be described. To generate the internal power supply voltage VII, voltage limiter circuits VII0 to VII2 and VIS are added. These circuits generate an internal power supply voltage VII with reference to a reference voltage VRI generated by a reference voltage generation circuit RVG (not shown in FIG. 26). Among them, the VIS is a circuit which is always operating and has a small current supply capability but a small current consumption. VII0 to VII2 are circuits that consume a relatively large amount of current and have a large current supply capability, and are turned on / off by an activation signal LC4. Therefore, VII0 to VII2 are always on except during the power down mode or the self refresh.

  Since the levels of the internal power supply voltages VDL and VCL are equal, the VDL voltage limiter circuit and the VCL voltage limiter circuit use a common reference voltage VRC. Also, the standby VDL voltage limiter circuit VDLS is omitted. Instead, VDL and VCL are connected by an appropriate resistor (in FIG. 27, a MOS transistor MC is used instead). When all the banks are inactive, the voltage limiter circuits VDL0 to VDL3 are off, and the level of VDL at this time is held by the VCL voltage limiter circuit through the MC. As described above, when the levels of VDL and VCL are equal, omitting VDLS makes it possible to reduce the current consumption in the power-down mode or the self-refresh mode.

  In the present embodiment, the number of voltage limiter circuits for VDL and VCL (except for the standby state) can be selected as in the first embodiment. In this embodiment, three voltage limiter circuits for VII (except for the standby state) are provided, but one or more voltage limiter circuits may be used. The present embodiment is characterized in that the standby VDL voltage limiter circuit can be omitted as described above.

  The embodiment in which the present invention is applied to the synchronous DRAM has been described. However, according to the present invention, if a semiconductor memory (for example, DDR (double data rate) -SDRAM, Synclink-DRAM, Rambus-DRAM) having a plurality of banks and a command is specified in a command, Different formats are applicable. The present invention can also be applied to a semiconductor device in which similar DRAM, logic circuit, CPU and the like are mounted on one chip. It is particularly effective to apply the present invention to a semiconductor device having a memory that reads and latches data in a sense amplifier and holds the data in a manner similar to the active standby state of the SDRAM.

FIG. 1 is a diagram illustrating a synchronous DRAM according to a first embodiment of the present invention. FIG. 2 is a configuration diagram of one bank of the synchronous DRAM of FIG. 1. FIG. 3 is a detailed circuit diagram of a part of the bank in FIG. 2. FIG. 2 is a configuration diagram of a power supply circuit of the synchronous DRAM of FIG. 1. FIG. 2 is a circuit diagram of a voltage limiter control circuit CTL0 of the synchronous DRAM of FIG. FIG. 6 is an operation waveform diagram of the control circuit of FIG. 5. FIG. 6 is an operation waveform diagram of the control circuit of FIG. 5. FIG. 2 is a circuit diagram of a voltage limiter control circuit CTL1 of the synchronous DRAM of FIG. FIG. 9 is an operation waveform diagram of the control circuit of FIG. 8. FIG. 9 is an operation waveform diagram of the control circuit of FIG. 8. FIG. 9 is an operation waveform diagram of the control circuit of FIG. 8. FIG. 9 is an operation waveform diagram of the control circuit of FIG. 8. FIG. 2 is a circuit diagram of voltage limiter circuits VDL0 to VDL3 of the synchronous DRAM of FIG. FIG. 2 is a circuit diagram of voltage limiter circuits VCL4 to VCL6 of the synchronous DRAM of FIG. FIG. 6 is a configuration diagram of a power supply circuit of a synchronous DRAM according to a second embodiment of the present invention. FIG. 16 is a circuit diagram of a voltage limiter control circuit CTL0 of the synchronous DRAM of FIG. FIG. 17 is an operation waveform diagram of the control circuit of FIG. 16. FIG. 11 is a diagram illustrating a synchronous DRAM according to a third embodiment of the present invention. FIG. 19 is a configuration diagram of a power supply circuit of the synchronous DRAM of FIG. 18. 19 is a circuit diagram of a voltage limiter control circuit CTL0 of the synchronous DRAM of FIG. FIG. 21 is an operation waveform diagram of the control circuit of FIG. 20. FIG. 11 is a diagram illustrating a synchronous DRAM according to a fourth embodiment of the present invention. 23 is a configuration diagram of a power supply circuit of the synchronous DRAM of FIG. 22. FIG. FIG. 23 is a circuit diagram of a voltage limiter control circuit CTL1 of the synchronous DRAM of FIG. 22. FIG. 25 is an operation waveform diagram of the control circuit of FIG. 24. FIG. 14 is a diagram illustrating a synchronous DRAM according to a fifth embodiment of the present invention. FIG. 27 is a configuration diagram of a power supply circuit of the synchronous DRAM of FIG. 26.

Explanation of reference numerals

CHIP: Chip, BANK0, BANK1, BANK2, BANK3: Memory bank, CKT: Peripheral circuit, VDL0 to VDL4: VDL voltage limiter circuit for operation, VDLS: VDL voltage limiter circuit for standby, VCL0 to VCL6 …… VDD voltage limiter circuit for operation, VCLS …… VDD voltage limiter circuit for standby, CTL0 …… VDL voltage limiter control circuit, CTL1 …… VDD voltage limiter control circuit, CTLM …… Main control circuit, RVG …… Voltage generation circuit.

Claims (9)

A first memory array including a plurality of first memory cells provided at predetermined intersections between the plurality of first word lines and the plurality of first data lines;
A plurality of first sense amplifiers provided corresponding to the plurality of first data lines;
A first voltage generation circuit that receives a first voltage and outputs a second voltage;
A plurality of first wirings formed on a first wiring layer and extending in the plurality of first data line directions;
A plurality of second wirings formed in a second wiring layer and extending in the plurality of first word line directions;
The plurality of first and second wires are connected at a point where the plurality of first and second wires cross each other,
A semiconductor device, wherein the second voltage is supplied to the plurality of first sense amplifiers via the plurality of first and second wirings. The semiconductor device according to claim 1 is
A second memory array including a plurality of second memory cells provided at predetermined intersections between the plurality of second word lines and the plurality of second data lines;
A plurality of second sense amplifiers provided corresponding to the plurality of second data lines;
A second voltage generation circuit that receives the first voltage and outputs the second voltage;
An output line from the second voltage generation circuit is connected to the first and second wirings,
The semiconductor device according to claim 1, wherein the first voltage is higher than the second voltage. 3. The semiconductor device according to claim 1, wherein:
The second wiring layer is formed between a wiring layer on which the plurality of first data lines are formed and the first wiring layer;
The semiconductor device according to claim 1, wherein the first and second wirings are metal wirings, and the crossing points are also formed on the first and second memory arrays. A semiconductor device according to any one of claims 2 to 3, which is a semiconductor chip having a plurality of memory banks,
A peripheral circuit common to the plurality of memory banks;
A third voltage generation circuit that receives the first voltage and outputs a voltage lower than the first voltage to the common peripheral circuit;
The plurality of first and second memory cells are dynamic memory cells;
The semiconductor device according to claim 1, wherein the first and second memory arrays are formed in different banks among the plurality of memory banks. The semiconductor device according to claim 4,
A semiconductor device, wherein a voltage output from the third voltage generating circuit is higher than the second voltage. The semiconductor device according to claim 4, wherein
The first and second voltage generating circuits are provided near two of the plurality of memory banks, respectively, and are turned on in response to corresponding bank activation signals. Semiconductor device. The semiconductor device according to any one of claims 4 to 6, further comprising an external clock signal, a clock enable signal, a chip select signal, a row address strobe signal, a column address strobe signal, and a write enable signal. And a control circuit for outputting a receiving command.
While the first voltage generation circuit is in an on state in response to a first bank activation signal output from the control circuit, the first voltage generation circuit is turned on in response to a second bank activation signal output from the second voltage generation circuit. The semiconductor device according to claim 1, wherein the first voltage generation circuit is turned off before the second voltage generation circuit is turned off when the first voltage generation circuit is turned off. The plurality of memory banks of the semiconductor device according to claims 4 to 7 are first, second, third, and fourth memory banks,
The common peripheral circuit is formed in an area between the first and second memory banks and between the third and fourth memory banks;
A voltage output from the third voltage generating circuit is formed in the first wiring layer, and extends in the first and second data line directions and in the first and second word line directions. A semiconductor device provided to a semiconductor device.   A semiconductor device, wherein a mesh wiring is provided on a memory array including a plurality of first memory cells provided at predetermined intersections between a plurality of first word lines and a plurality of first data lines.

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