JP2004208193A - Spread spectrum clock generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a spread spectrum clock generating circuit capable of securing sufficient resolution even with a wide amplitude adjustment range and minimum amplitude in a small circuit scale. <P>SOLUTION: This spread spectrum clock generating circuit is provided with a frequency phase comparator 12, a charge pump 13 for generating a charge/discharge signal in accordance with a phase difference detected by the frequency phase comparator, a loop filter 14 for generating a differential voltage signal corresponding to the charge signal, a voltage current conversion circuit 16 for converting the differential voltage signal into a differential current signal, and a clock generator 18 for generating a generation clock of a frequency corresponding to the differential current signal. The spread spectrum clock generating circuit is provided with a spread spectrum modulation circuit 21 for modulates the differential current signal and generating a spread spectrum modulation signal and an amplifier circuit 22 for amplifying the spread spectrum modulation signal, adds the amplified spread spectrum modulation signal to the differential current signal to apply the resultant signal to the clock generator 18. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a spread spectrum clock generation circuit that generates a clock signal whose period fluctuates by a small amount in order to reduce electromagnetic wave radiation.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as semiconductor devices have become faster and more highly integrated, electromagnetic wave radiation from the devices has become a problem. As the operating frequency increases, the wavelength of the signal becomes shorter, and the wiring length inside the connection circuit or the substrate becomes almost the same as the wavelength of the high-frequency signal. Radiation increases rapidly. Also, electromagnetic wave radiation is emitted from the clock generation circuit itself. Electromagnetic radiation of an electronic device using a semiconductor element that operates with a high-speed clock causes adverse effects such as a malfunction due to mutual interference between electronic devices and interference with a communication device.
[0003]
In order to solve such problems, in electronic equipment where electromagnetic radiation is a problem at present, measures such as reducing the electromagnetic radiation by improving the circuit layout etc. and reducing the leakage of electromagnetic waves to the surroundings by shielding the electromagnetic waves, etc. Has been done. However, there is a problem that it is difficult to sufficiently perform shielding for reducing electromagnetic wave radiation since portable devices and the like are required to be reduced in size and weight.
[0004]
Therefore, it has been practiced to spread the clock by slightly changing the operation clock of the semiconductor device to reduce electromagnetic wave radiation, and a spread spectrum clock generation (SSCG) circuit for generating such a clock has been developed. Proposed. (JP-A-2000-101424, etc.)
The present applicant discloses in Japanese Patent Application No. 2002-266631 a voltage-controlled oscillator (VCO) widely used in a clock generation circuit using a PLL by using a voltage-current conversion circuit, a current variable circuit, and a current-controlled oscillator (ICO). The SSCG circuit to constitute is proposed. This SSCG circuit uses a current digital-to-analog converter (IDAC) that can control the amount of current with a digital code signal as a current variable circuit, so that fluctuations in the oscillation frequency can be digitally controlled and control is easy. It has the feature of.
[0005]
FIG. 1 is a diagram showing a configuration example of an SSCG circuit described in Japanese Patent Application No. 2002-266631. This example is a circuit that generates a clock CK having a frequency M / N times that of a reference clock CLK using a PLL (Phase Locked Loop) circuit. This circuit includes a 1 / N frequency divider 11, a frequency phase comparator 12, a charge pump (CP) 13, a loop filter 14, a voltage controlled oscillator (VCO) 15, and a 1 / M frequency divider 19. And a voltage-current (VI) conversion circuit 16, a current variable circuit 17, and a current-controlled oscillator (ICO) 18.
[0006]
In the circuit shown in FIG. 1, the frequency / phase comparator 12 detects the phase difference between CLK divided by 1 / N and CK divided by 1 / M, and outputs a signal for controlling the CP 13 according to the phase difference. The CP 13 outputs a signal for charging and discharging the loop filter 14 according to the phase difference, and a difference voltage corresponding to the phase difference is generated at one end of the loop filter 14. This difference voltage is applied to the VCO 15, and a clock having a constant cycle is generated accordingly. In this SSCG circuit, the difference voltage is converted into a difference current signal by a VI conversion circuit 16, and a current variable circuit 17 adds a signal which fluctuates in a predetermined cycle having a small amplitude as shown in FIG. 2 to the difference current signal. Then, a spectrum modulation signal is generated, and the generated signal is applied to the ICO 18. As a result, the cycle of the generated clock CK fluctuates in a predetermined cycle around a cycle M / N times the cycle of the reference clock CLK. The fluctuation rate and the period of the fluctuation are determined by the spectrum modulation signal generated by the current variable circuit 17. Note that the response time of the PLL circuit is set sufficiently longer than the cycle of the spectrum modulation signal.
[0007]
FIG. 3 is a diagram showing a configuration of a current digital-to-analog converter (IDAC) used as the current variable circuit 17 described in Japanese Patent Application No. 2002-266631. As shown in FIG. 3, the IDAC has a current mirror circuit composed of transistors Tr11 to Tr15, Tr20, and Tr30 to Tr3n. By appropriately setting the size of the transistor as shown in FIG. A current of 80% of the current Iref output from the I conversion circuit 42 flows, a current of 10% of Iref flows in Tr3n, and a current of (20 × 1/2 ⁿ⁻² )% of Iref flows in Tr32, A current of (20 × 1/2 ^{n -1} )% of Iref flows through Tr31, and a current of (20 × 1 / ²ⁿ )% of Iref flows through Tr30. When the Tr4n to Tr40 are turned on by the bit data / D0 to / Dn of the output code, a current flows through the corresponding Tr3n to Tr30. Therefore, when all of Tr4n to Tr40 are turned off, a current amount of 80% of Iref flowing through Tr20 is output. A current flows, and a current amount of about 100% of Iref is output. That is, by setting the bit data / D0 to / Dn of the output code to an appropriate value, an appropriate amount of current between 80% and about 100% of Iref is output. Note that the current variable circuit is provided with a control circuit for generating the output code.
[0008]
In the above IDAC, it is possible to control the amount of current that is output by decomposing about 20% of the fluctuation range into n bits. That is, the minimum resolution is 20/2 ⁿ %. For example, if n = 9, then 2 ⁹ = 512, 0.04% of 20% divided into 500 steps is the resolution, and the output current is controlled at a pitch of 0.04% from 80% to 100%. it can.
[0009]
The SSCG circuit of FIG. 1 is generally used as a single chip or as a single chip together with other circuits. In an SSCG circuit that performs spread spectrum modulation, it is necessary to change the amplitude of spread spectrum modulation in accordance with the application to be used. For example, when the electromagnetic wave radiation is more important than the fluctuation of the period, the amplitude of the spread spectrum modulation needs to be increased, and when the fluctuation of the period is required to be small, the amplitude of the spread spectrum modulation needs to be reduced. . Therefore, in order to increase the versatility of the SSCG circuit chip, the output code output from the control circuit can be set arbitrarily so as to be applicable to various uses.
[0010]
[Patent Document 1]
JP-A-2000-101424 (whole)
[0011]
[Problems to be solved by the invention]
Even if the output code applied to the IDAC can be set arbitrarily, the configuration of the IDAC itself is fixed by the chip, and the range in which the input current Iref can be varied and the minimum step (resolution) that can be varied are fixed. FIG. 4 shows a change in the output code when the amplitude is changed. The current changes in response to the change in the output code, and a difference current that changes as in FIG. 4 is obtained. As shown in FIG. 4A, when the amplitude is large, the amplitude is large compared to the minimum step, and changes relatively smoothly. On the other hand, when the amplitude is reduced to half, as shown in FIG. 4B, it becomes less smooth than in the case of FIG. When the amplitude is further reduced to half, that is, the first quarter, the change of the difference current signal becomes less smooth. If the change of the difference current signal is not smooth, the high frequency component in the current applied to the ICO increases, which adversely affects the operation of the PLL.
[0012]
Therefore, in order to obtain a difference current signal that changes sufficiently smoothly even when the amplitude is reduced, it is necessary to increase the number of transistors to increase the number of bits of the output code. For example, the amplitude can be adjusted with 5 bits, that is, the amplitude can be adjusted in the range of 100% to 3%, and the minimum amplitude can be changed to 4 bits resolution, that is, 15 steps. is necessary. In the circuit configuration of FIG. 3, if n = 9, the maximum size transistor needs to be 2 ⁸ = 256 times the minimum size transistor, and the chip area of this portion is 2 ⁹ = 512 times. Need to be Therefore, the size of Tr3n and Tr4n is 256 times the size of Tr30 and Tr40. Since the size of the transistor of the minimum size is determined by the manufacturing process, the size of the transistor of the maximum size becomes very large, and there is a problem that the area required for it becomes large.
[0013]
Also, a plurality of transistors of the minimum size are formed in parallel, one transistor of the minimum size, two transistors of the next size, two transistors of the minimum size, and four transistors of the next size are connected in parallel. Is changed by a power of two to realize a transistor array having a size ratio of the circuit of FIG. In this case, assuming that n = 9, 256 transistors of the maximum size are connected in parallel with transistors of the minimum size. Therefore, to realize a set of Tr30 and Tr40 from a set of Tr3n and Tr4n, 512 sets of Tr30 and Tr40 are required.
[0014]
In any case, when the number of bits of the output code is increased, the size of the transistor is increased by a power of two, which causes a problem that the circuit scale is increased and the cost is increased.
[0015]
SUMMARY OF THE INVENTION It is an object of the present invention to realize a spread spectrum clock generation circuit capable of securing a sufficient resolution even with a wide amplitude adjustment range and a minimum amplitude without increasing the circuit scale so much.
[0016]
[Means for Solving the Problems]
FIGS. 5A and 5B are diagrams showing the principle configuration of the spread spectrum clock generation circuit of the present invention.
[0017]
As shown in FIG. 5, the spread-spectrum clock generating circuit of the present invention includes a spread-spectrum modulation circuit and an amplifying circuit. After performing spread-spectrum modulation and amplitude adjustment of the difference current signal separately, the original difference current signal To be added. Specifically, the spread spectrum modulation circuit and the amplifier circuit are cascaded, and the difference current signal output from the voltage-current conversion circuit is modulated by the spread spectrum modulation circuit, and then the spread spectrum modulation signal is amplified by the amplification circuit. The amplitude is adjusted, and the amplitude-adjusted signal is added to the original difference current signal and applied to the ICO.
[0018]
As shown in FIGS. 5A and 5B, the order of the spread spectrum modulation circuit and the amplification circuit may be reversed.
[0019]
6A and 6B are diagrams for explaining the principle of the present invention. FIG. 6A shows a modulated current signal after performing n-bit pattern modulation on a difference current signal having an amplitude A by a spread spectrum modulation circuit. FIG. 6B shows a signal obtained by amplifying (attenuating) the amplitude of the signal of FIG. Even if the amplitude is multiplied by k / m, the resolution (the number of steps) does not change.
[0020]
In the spread spectrum clock generation circuit according to the present invention, since the pattern modulation and the amplitude adjustment are performed independently, a modulation current with a constant resolution independent of the amplitude adjustment is output. As described above, when the amplitude can be adjusted with 5 bits and the resolution is 4 bits even with the minimum amplitude, in the conventional configuration of FIG. 3, n = 9 and Tr30 to Tr3n and Tr40 to Tr4n are set as n = 9. In order to realize this, it was necessary to have a size of 2 ⁹ = 512 times the minimum size of the transistor set Tr30 and Tr40. On the other hand, in the spread spectrum clock generation circuit of the present invention, it is sufficient that the size is 2 ⁵ +2 ⁴ = 48 times, and the circuit scale can be reduced.
[0021]
The spread spectrum modulation circuit and the amplifier circuit can be realized by the current digital-to-analog converter (IDAC) shown in FIG.
[0022]
The spread spectrum modulation circuit can be realized by a digital control circuit that generates an output code that continuously changes between a maximum value and a minimum value in each cycle, and an IDAC.
[0023]
The amplifier circuit can be realized by a digital control circuit for generating a fixed output code and an IDAC.
[0024]
The digital control circuit includes a plurality of frequency dividers having different division ratios for dividing a clock, a switching controller for sequentially selecting outputs of the plurality of frequency dividers, and an up / down counter for counting the selected divided clock. And a counter that counts the frequency-divided clock and switches between an up operation and a down operation of the up / down counter at every predetermined count.
[0025]
Further, the digital control circuit can be realized by a computer system under program control.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 7 is a diagram showing a configuration of a spread spectrum clock generation (SSCG) circuit according to the first embodiment of the present invention. As shown in the figure, the circuit generates a clock CK M / N times the reference clock CLK using a PLL circuit, similarly to the circuit shown in FIG. 1, and the portion of the current variable circuit 17 is different from the conventional example.
[0027]
As shown in FIG. 7, in the SSCG circuit of the first embodiment, the difference current signal output from the VI conversion circuit 16 in the VCO 15 is applied to the ICO 18 and also input to the pattern IDAC 31. The pattern IDAC 31 performs spread spectrum modulation on the difference current signal according to the output code output from the pattern control circuit 33 to generate a spread spectrum modulated signal. The level IDAC 32 amplifies (attenuates) the spread spectrum modulated signal according to the output code output from the level control circuit 34 and adjusts the amplitude.
[0028]
FIG. 8 is a diagram showing the configuration of the pattern IDAC31, and FIG. 9 is a diagram showing the configuration of the level IDAC32. As shown in FIGS. 8 and 9, the pattern IDAC 31 has a configuration similar to the IDAC of FIG. 3, but Tr12, Tr14, and Tr20 are omitted. The level IDAC 32 is different from the pattern IDAC 31 in that the number of bits is m bits and a pair of transistors having a transistor size ratio of 1/2 m is added. The pattern IDAC31 in FIG. 8 can change the input current Iref from zero to Iref (1-1 / ²ⁿ ) / X. The level IDAC32 in FIG. 9, it is possible to vary between Iref input current Iref from Iref / (2 ^m X).
[0029]
The output code output by the level control circuit 34 is set externally according to the use object and has a constant value.
[0030]
The pattern control circuit 33 outputs the same spread spectrum modulation code as that disclosed in the aforementioned Japanese Patent Application No. 2002-266631.
[0031]
FIG. 10 is a diagram showing the configuration and operation of the pattern control circuit 33 realized by a digital logic circuit. As shown in FIG. 10A, the pattern control circuit 33 has an up / down counter 41 for counting clocks and a frequency dividing counter 42 for controlling the up / down counter 41. The up / down counter 41 outputs the count value in an n-bit binary code. As shown in FIG. 8B, the frequency dividing counter 42 counts the clock, and switches the up-counting operation and the down-counting operation of the up-down counter 41 when the count value reaches a predetermined value. As a result, an output code that changes as shown in FIG. 10B is obtained. Here, the count value desirably changes between a maximum value and a minimum value defined by the number of bits.
[0032]
FIG. 11 is a diagram showing the configuration of the SSCG circuit according to the second embodiment of the present invention. In the first embodiment, the pattern control circuit is realized by a logic circuit. In the second embodiment, the pattern control circuit is realized by a computer system such as a microcomputer or a DSP. Other parts are the same as in the first embodiment.
[0033]
【The invention's effect】
As described above, according to the present invention, a spread spectrum clock generation circuit that can secure a sufficient resolution even with a wide amplitude adjustment range and a minimum amplitude can be realized with a small circuit scale, and is a low-cost and highly versatile spread spectrum clock generation circuit. A circuit is obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration example of a conventional spread spectrum clock generation (SSCG) circuit.
FIG. 2 is a diagram showing a spread spectrum modulated signal.
FIG. 3 is a diagram showing a configuration of a current digital-to-analog converter (IDAC) used as a current variable circuit in a conventional example.
FIG. 4 is a diagram for explaining a problem when the amplitude is changed in the conventional example.
FIG. 5 is a diagram showing a principle configuration of the present invention.
FIG. 6 is a diagram illustrating the principle of the present invention.
FIG. 7 is a diagram showing a configuration of an SSCG according to the first embodiment of the present invention.
FIG. 8 is a diagram showing a configuration of a pattern IDAC in the first embodiment.
FIG. 9 is a diagram illustrating a configuration of a level IDAC in the first embodiment.
FIG. 10 is a diagram showing a configuration and an operation of realizing the pattern control circuit of the first embodiment by a logic circuit.
FIG. 11 is a diagram illustrating a configuration of an SSCG according to a second embodiment of the present invention.
[Explanation of symbols]
11 1 / N frequency divider 12 frequency phase comparator 13 charge pump circuit 14 loop filter 15 VCO
16 VI conversion 17 Current variable circuit 18 Current controlled oscillator (ICO)
19 1 / M frequency divider 21 spread spectrum modulation circuit 22 amplifier circuit

Claims (7)

A frequency-phase comparator for detecting a phase difference between the reference clock and the generated clock;
A charge pump that generates a charge / discharge signal according to the phase difference detected by the frequency phase comparator,
A loop filter for generating a difference voltage signal according to the charging signal,
A voltage-current conversion circuit that converts the difference voltage signal into a difference current signal,
A clock generator that generates a generated clock having a frequency corresponding to the difference current signal.
A spread spectrum modulation circuit that modulates the difference current signal to generate a spread spectrum modulation signal,
An amplification circuit for amplifying the spread spectrum modulation signal,
A spread-spectrum clock generation circuit, wherein the amplified spread-spectrum modulated signal is added to the difference current signal and applied to the clock generator. A frequency-phase comparator for detecting a phase difference between the reference clock and the generated clock;
A charge pump that generates a charge / discharge signal according to the phase difference detected by the frequency phase comparator,
A loop filter for generating a difference voltage signal according to the charging signal,
A voltage-current conversion circuit that converts the difference voltage signal into a difference current signal,
A clock generator that generates a generated clock having a frequency corresponding to the difference current signal.
An amplifier circuit for amplifying the difference current signal;
A spread spectrum modulation circuit that modulates the amplified difference current signal to generate a spread spectrum modulation signal,
A spread spectrum clock generation circuit, wherein the spread spectrum modulation signal is added to the difference current signal and applied to the clock generator. The spread spectrum modulation circuit includes a digital control circuit that generates an output code that continuously changes between a maximum value and a minimum value in each cycle, and a current digital-to-analog conversion circuit that changes an input current signal according to the output code. 3. The spread spectrum clock generation circuit according to claim 1, comprising: 3. The spread spectrum clock according to claim 1, wherein the amplification circuit includes a digital control circuit that generates a fixed output code, and a current digital-to-analog conversion circuit that changes an input current signal into a current corresponding to the output code. 4. Generator circuit. The current digital-to-analog conversion circuit includes a transistor array that generates a current corresponding to the input current at a weighting ratio corresponding to the output code, and outputs a combined output current of the transistor array. 5. The spread-spectrum clock generation circuit according to claim 3, wherein a current output of each transistor in the transistor row is controlled according to the output code to change the current to a current corresponding to the output code. The digital control circuit includes a plurality of frequency dividers having different division ratios for dividing a clock, a switching controller for sequentially selecting outputs of the plurality of frequency dividers, and an up / down controller for counting the selected divided clock. 5. The spread spectrum clock generation circuit according to claim 3, further comprising: a counter; and a counter that counts the frequency-divided clock and switches between an up operation and a down operation of the up / down counter at every predetermined count. 5. The spread spectrum clock generation circuit according to claim 3, wherein the digital control circuit is a computer system controlled by a program.

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