JP2004206246A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a data fetching timing responding to a delay of signal by an external load capacity of a semiconductor without using extra terminal of a semiconductor chip. <P>SOLUTION: By use of the semiconductor device comprising a clock device 210, an input/output I/O 220, a central processing unit 250, a delay device 260, a flip-flop 290, an output buffer 230, an input buffer 235, an input I/O 280 having an I/O pad 225, a delay clock 240 delayed by the external load capacity 238 is generated in the semiconductor device. According to this, a means for changing the fetching timing at an optional time according to the signal delay by an external condition change of the semiconductor can be obtained to realize a precise adjustment of data fetching timing. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an interface circuit interposed between signal lines for transferring signals, and more particularly, to a semiconductor device that can smoothly transmit and receive information on a data bus formed between semiconductor chips.
[0002]
[Prior art]
When transmitting and receiving data between a plurality of semiconductor chips, when the information of an input signal needs to be taken into an internal circuit at a specific timing and the value must be determined, the optimal taking timing of this information is as follows. It changes due to changes in the temperature conditions and voltage conditions inside and outside the semiconductor chip, and also due to the delay depending on the condition of the additional capacitance between the semiconductor chips.
[0003]
In order to determine the capture timing, as shown in FIG. 1A, a clock device 110, a delay device 125, a receiving circuit 140, an output buffer 115 and an output pad 117 composed of an output buffer 117 are provided in the semiconductor device 100. O120, and the input I / O 135 composed of the input buffer 130 and the input pad 133, output the clock information 113 to the semiconductor chip of the information exchange partner via the output I / O 120, and as a result When the information input 137 is input from the input I / O 135 as the input signal 137, the time corresponding to the signal delay inside and outside the chip is adjusted by the delay device 125, and the receiving circuit 140 determines the timing at which the receiving circuit 140 takes in the input information 137. generate. Conventionally, a means for selecting a delay value (for example, Patent Document 1) or the like is used as the delay adjusting means. However, since a large number of delay value selecting means are required to guarantee an external load in a wide range, The number of circuit elements has increased, which has caused a problem in area.
[0004]
As another example, as shown in FIG. 1B, a clock device 160, a receiving circuit 195, an output I / O 170 including an output buffer 165 and an output pad 167, an input buffer 175, and an input With the configuration including the clock input I / O 180 and the data input I / O 190 constituted by the pad 177, the clock information 163 to the semiconductor chip of the information exchange partner is output via the output I / O 120, and as a result, When the information input 193 is input from the input I / O 190, the timing for optimally capturing the information input 193 is input as a capture signal 183 from the partner semiconductor chip, and the value is determined by the receiving circuit 195.
[0005]
[Patent Document 1]
JP-A-5-190673
[Problems to be solved by the invention]
The operation of the semiconductor chip must be ensured in a specific temperature range and operating voltage range. Therefore, the design is made by adjusting the signal delay, but the load capacitance outside the chip depends on the layout of the semiconductor chip on the board. However, it is difficult to specify the value when designing a semiconductor chip, and the value differs depending on the contents to be arranged. Therefore, in the semiconductor device 100 shown in FIG. 1A, it is easy to adjust the delay in the semiconductor device 100 by the delay device 125, but it is difficult to correctly adjust the delay due to the load capacitance outside the chip.
[0007]
Further, in the semiconductor device 150 shown in FIG. 2B, since both the information input 193 and the capture signal 183 are delayed by the load capacitance outside the chip, it is easy to adjust the optimal capture timing. However, since the terminals of the semiconductor device are additionally used to obtain the capture signal 183, the area of the semiconductor device is greatly increased, and the price is disadvantageously increased.
[0008]
The present invention has been made in view of the above-described drawbacks, and has as its object to realize an inexpensive timing generator by acquiring timing means for taking in consideration of signal delay due to a load capacitance outside a chip without additionally specifying terminals of a semiconductor chip. I do.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention comprises:
A clock device for generating a clock for notifying the timing of an input / output signal to an external device, an input / output pad capable of outputting the clock, and delaying a signal fed back from the I / O pad to the inside of the device And a receiving means for receiving an input data signal input from an external device using a delay clock generated by the delay device. As a result, a means for adjusting delay information and a delay amount depending on the external load capacitance can be obtained with one I / O pad.
[0010]
The semiconductor device according to the present invention is the semiconductor device according to claim 1, wherein the delay device includes register means that can be arbitrarily set, and selection means that can select a delay amount of the input / output signal timing according to the register value. Is what it is. As a result, a delay adjusting means for the capture timing according to the delay outside the semiconductor chip is obtained.
[0011]
In the semiconductor device according to the present invention, in the semiconductor device according to claim 1, the setting means for setting the register device is a central processing unit. This provides a means for adjusting the capture timing at an arbitrary time.
[0012]
The semiconductor device according to the present invention is the semiconductor device according to claim 1, wherein the receiving means is a flip-flop that latches the external input data using the delayed clock. As a result, a means for securing external input data at an arbitrary fetch timing is obtained.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing the first embodiment of the present invention.
[0014]
As shown in FIG. 2, the semiconductor device 200 according to the first embodiment includes a clock device 210, input / output I / O pads 220, a central processing unit 250, a delay device 260, input I / O pads 280, and flip-flops. 290.
[0015]
A clock output 215 from the clock device 210 is output as a control output 237 for controlling a control circuit outside the semiconductor device via the output buffer 230 and the pad 225. An external signal 277 synchronized with the control output 237 is input to the semiconductor device 200 as input information 285 via a pad 270 and an input buffer 275. A clock output 215 is input to the input buffer 235 in the input / output I / O 220. By passing through, the delay clock 240 delayed by the external additional capacitance 238 is generated. The delay clock 240 is adjusted in delay amount by a delay device 260 controlled by a delay adjustment signal 255 from the central processing unit 250, and is input to the flip-flop 290 as a delay adjustment clock 265.
[0016]
The flip-flop 290 stores the input information 285 using the delay adjustment clock 265.
[0017]
FIG. 3 shows an example of the delay device. The delay device 260 includes delay buffers 310, 313, and 316, a selection circuit 330, and a register 340.
[0018]
The delay clock 240 generates delay additional signals 320, 323, and 326 by passing through delay buffers 310, 313, and 316 having arbitrary delay values, and inputs the respective signals to the selection circuit 330. The input by the delay adjustment signal 255 is held by the register 340, and the selection signal 345 is input to the selection circuit based on the held information. The selection circuit 330 can select an arbitrary delay addition signal 320, 323, or 326 delay adjustment signal based on the selection signal 345 and output it as the delay adjustment clock 265.
[0019]
【The invention's effect】
As described above, the semiconductor device according to the present invention includes a clock device for generating a clock for notifying the input / output signal timing to an external device, an input / output I / O pad for outputting the clock, and A delay device for delaying a signal fed back from the / O pad to the inside of the device; and a receiving means for receiving an input data signal input from an external device using a delay clock by the delay device. . This makes it possible to obtain delay information and delay amount adjustment means depending on the external load capacitance with one I / O pad, and use external input data corresponding to the delay due to the external load capacitance without using a terminal, which was conventionally difficult. It is possible to realize the automatic adjustment of the capture.
[0020]
Further, in the semiconductor device according to the present invention, the delay device includes register means that can be arbitrarily set, and selection means that can select a delay amount of the input / output signal timing according to the register value. As a result, it is possible to obtain a delay adjusting means of the capture timing according to the delay outside the semiconductor chip, and it is possible to realize the adjustment of the capture timing with higher accuracy than before.
[0021]
Further, in the semiconductor device according to the present invention, the setting device for setting the register device is a central processing unit. As a result, a means for adjusting the capture timing at any time can be obtained, and highly accurate adjustment of the capture timing can be realized at any time.
[0022]
Further, in the semiconductor device according to the present invention, the receiving means is a flip-flop that latches the external input data using the delayed clock. As a result, it is possible to obtain a means for securing external input data at an arbitrary fetch timing, and to receive an external input in consideration of a load capacity outside the semiconductor chip.
[Brief description of the drawings]
FIG. 1 is a block diagram of a conventional circuit for transferring signals between semiconductor devices. FIG. 2 is a block diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 3 shows an example of a delay device. Block diagram [Explanation of symbols]
Reference Signs List 100 semiconductor device 110 clock device 125 delay device 140 receiving circuit 120 output I / O
135 input I / O
180 Clock input I / O
220 input / output I / O
250 Central processing unit 310 Delay buffer 330 Selection circuit 340 Register

Claims (4)

A clock device for generating a clock for notifying the timing of an input / output signal to an external device, an I / O pad capable of inputting / outputting the clock, and delaying a signal fed back from the I / O pad into the device A semiconductor device, comprising: a delay device for causing the delay device to receive an input data signal input from an external device using a delay clock generated by the delay device. 2. The semiconductor device according to claim 1, wherein said delay device includes register means that can be arbitrarily set, and selection means that can select a delay amount of said input / output signal timing according to said register value. . 2. The semiconductor device according to claim 1, wherein the setting means for setting the register device is a central processing unit. 2. The semiconductor device according to claim 1, wherein said receiving means is a flip-flop that latches said external input data using said delayed clock.

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