JP2004205346A - Phase difference detecting circuit and inclined-angle measuring instrument - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when a CPU having a small capacity is used, the burden becomes heavier at the time of continuously measuring the phase difference between two input signals at a plurality of spots and averaging the measured phase differences, because the phase difference can be measured at only one spot. <P>SOLUTION: The mean value of the phase differences between the two input signals S1 and S2 can be found by dividing the count value outputted from a counter 4 by the number of occurring times of the phase differences between the input signals S1 and S2 while an inputting timing signal S4 is outputted. In addition, the dividing means used for the division is realized by means of hardware or software and the averaged phase difference of the sporadically inputted input signals S1 and S2 is made detectable by using the CPU 5 having the small capacity. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a phase difference detection circuit for detecting an averaged phase difference between intermittently input signals, and a tilt angle measuring device using the phase difference detection circuit.
[0002]
[Prior art]
In a conventional phase difference detection circuit, two digital signals are input as input signals, voltage means for applying a voltage to the capacitor via a resistor connected in series with the capacitor, and a voltage to the capacitor in response to the input signal. When two kinds of voltages are applied, and when a pulse of the input signal is lost, a control unit that controls the voltage application unit to stop applying the voltage to the capacitor is provided, and a part of the input signal is provided. The configuration is such that a stable phase error voltage is obtained even when the phase error voltage is lost (for example, see Patent Document 1).
[0003]
[Patent Document 1]
JP-A-58-175319 (FIG. 2)
[0004]
[Problems to be solved by the invention]
In the conventional example, since a phase difference is output by an analog voltage, an analog error due to temperature and aging occurs. In addition, a D / A converter is required to input the output to the CPU, which causes an error to increase. In addition, by taking two signals from the first stage into the CPU and viewing the phase difference between the two input signals as a time difference, it is easy for the CPU to replace the conventional phase difference detection circuit described above with the CPU. By holding the phase difference digitally, it is easy to continue to output the value immediately before the input signal is interrupted, and it is possible to cope with even sporadic input signals. However, when a CPU having a small capacity is used, the phase difference between the two input signals can be measured at only one location, and there is no function of continuously measuring and averaging the phase difference between the two input signals at a plurality of locations. However, there has been a problem that it is impossible to measure and average the phase difference between the two input signals at a plurality of continuous points.
[0005]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and is intended to detect a phase difference averaged of an input signal sporadically input using a CPU having a small capacity. The aim is to obtain a circuit.
[0006]
Further, according to the present invention, for an input signal sporadically input from an ultrasonic receiver when an ultrasonic sensor is used, an averaged phase difference within an arbitrary period detected using a CPU having a small capacity is calculated. It is an object of the present invention to obtain a tilt angle measuring device that can detect a relative angle amount with respect to a reflecting object by using the same.
[0007]
[Means for Solving the Problems]
A phase difference detection circuit according to the present invention is a phase difference detection circuit for digitally detecting a phase difference between input signals, wherein at least one of the phase difference detection circuits extracts phase difference information between input signals intermittently input. A phase difference information extraction circuit, the phase difference information extracted by the phase difference information extraction circuit, and a period defining signal that defines a period for averaging the phase difference between the input signals; Averaging phase difference detecting means for detecting a phase difference between the converted input signals.
[0008]
The tilt angle measuring device according to the present invention includes a plurality of pairs of an ultrasonic oscillator and an ultrasonic receiver having the same ultrasonic path length from transmission to reception of ultrasonic waves, and reflects the transmitted ultrasonic waves. The relative angle with respect to the reflecting object, the tilt angle which is detected based on the phase difference between the input signals obtained by receiving the ultrasonic waves reflected by the reflecting object by the ultrasonic receivers of each set. In the measurement device, at least one of the ultrasonic receivers of each set obtained by receiving the ultrasonic waves reflected from the reflecting object, at least one of which is intermittently input, is used to digitally calculate the phase difference between the input signals. And a phase difference detection circuit for detecting the phase difference.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, one embodiment of the present invention will be described.
Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a configuration of a phase difference detection circuit according to the first embodiment, which compares an input signal S1 and an input signal S2 and outputs a pulse signal having a width corresponding to the phase difference between the input signals. An exclusive OR circuit (phase difference information extracting circuit) 1, a logic of an output of the exclusive OR circuit 1, a reference clock signal output by the oscillation circuit 3, and an input timing signal S4 given from a microcomputer (not shown). AND circuit (phase difference information extraction circuit) 2 for calculating the product and outputting the calculation result as signal S5, and a counter (averaging phase difference detection means, counting circuit) for counting signal S5 output from AND circuit 2 4 is provided. Reference numeral 5 denotes a CPU (averaging phase difference detecting means, calculating means) having a small capacity, for example, which divides the count value output from the counter 4 by the number of times the phase difference has occurred.
[0010]
Next, the operation will be described.
FIG. 2 is a timing chart showing the operation of the phase difference detection circuit shown in FIG. 1. Hereinafter, the operation will be described with reference to this timing chart.
FIG. 2A shows the signal waveform of the input signal S1, and FIG. 2B shows the signal waveform of the input signal S2. The exclusive OR circuit 1 outputs an exclusive OR result (ExOR) of the input signal S1 and the input signal S2, and outputs the exclusive OR result and a reference clock signal output from the oscillation circuit 3 to the same. The logical product with the input timing signal S4 shown in FIG. 3C is calculated by the AND circuit 2 and output to the counter 4 as a signal S5 shown in FIG. 2B, and the counting result of the signal S5 is output from the counter 4. Is output. FIG. 7E shows the result of counting the signal S5 output by the counter 4.
The input timing signal S4 is a signal that defines an interval for detecting a phase difference between the input signal S1 and the input signal S2, and the signal S5 is a signal that defines the input signal S1 and the input signal when the input timing signal S4 is being output. The number of the reference clock signals corresponds to the phase difference time from S2. Accordingly, the exclusive OR circuit 1 outputs the exclusive OR result of the input signal S1 and the input signal S2, and the input timing signal S4 is output even if the oscillation circuit 3 outputs the reference clock signal. In the absence state, the output of the AND circuit 2 maintains the "Low level", and the count value of the counter 4 does not change.
In the state where the input timing signal S4 is being output, the number of times a phase difference has occurred between the input signal S1 and the input signal S2 is four in the example of the timing chart shown in FIG. By dividing the counted value by the number of occurrences of the phase difference of 4, the average value of the phase difference between the input signal S1 and the input signal S2 can be easily obtained. Further, this dividing means can be realized by hardware or software, and can easily detect the averaged phase difference of the input signal sporadically input even by using the CPU 5 having a small capacity.
[0011]
As described above, according to the first embodiment, even when a CPU having a small capacity is used, the phase difference between the two input signals S1 and S2 is continuously measured at a plurality of points, and the phase difference is measured. There is an effect that a phase difference detection circuit that can obtain the average value of the phase difference is obtained.
[0012]
Embodiment 2 FIG.
Next, a phase difference detection circuit according to the second embodiment will be described.
FIG. 3 is a circuit diagram showing a configuration of a phase difference detection circuit according to the second embodiment. The same or corresponding parts as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.
In this phase difference detection circuit, the counter that counts the signal S5 output from the AND circuit 2 is the up / down counter 11, and the signal S6 supplied to the input terminal for setting up counting and down counting is “Low level”. When the signal S6 supplied to the input terminal is at "High level", it functions as a down counter.
Further, the phase difference detection circuit selects an inverter circuit 21 for inverting the input signal S2, a capacitor 14 and a resistor 15 for detecting a rising edge and a falling edge of the input signal S2, and selects and outputs the rising edge. A diode 16 is provided. Further, a capacitor 22 and a resistor 23 for detecting a rising edge and a falling edge of the input signal S2 inverted by the inverter circuit 21 and a diode 24 for selecting and outputting the rising edge are provided. The cathodes of the diodes 16 and 24 are connected to a resistor 39 and a clock input terminal of a D flip-flop (averaging phase difference detecting means) 25.
Further, a delay circuit including a resistor 12 and a capacitor 13 is arranged between the exclusive OR circuit 1 and the ground. A connection point between the resistor 12 and the capacitor 13 is a data connection of the D flip-flop 25. Connected to input terminal.
[0013]
Next, the operation will be described.
FIG. 4 is a timing chart showing the operation of the phase difference detection circuit shown in FIG. 3, and the operation will be described below with reference to this timing chart.
The input signal S1, the input signal S2, and the signal S5 output from the AND circuit 2 are the same as the input signal S1, the input signal S2, and the signal S5 described in the first embodiment. In the phase difference detection circuit according to the second embodiment, the up-count operation and the down-count operation of the up / down counter 11 are switched according to the delay and advance of the phase difference between the input signal S1 and the input signal S2. When the phase of the input signal S2 is advanced with respect to the signal S1, the up-down counter 11 performs an up-count operation, and when the phase of the input signal S2 is delayed with respect to the input signal S1, the up-down counter 11 performs a down-count operation.
As shown in the timing chart of FIG. 4, when the phase of the input signal S2 is advanced with respect to the input signal S1, the data input terminal of the D flip-flop 25 is connected to the input signal S1 as shown in FIG. A rectangular wave S3, in which a pulse signal having a pulse width corresponding to the phase difference between the input signal S2 and the pulse signal S2 is slightly delayed by the integrating circuit, is supplied to the clock input terminal of the D flip-flop 25. The clock signal is output at the rising and falling timings of the input signal S2. As is apparent from the rising and falling timings of the input signal S2 and the delay waveform S3 shown in FIG. 4D, the "low level" of the delay waveform S3 is read into the D flip-flop 25. , D flip-flop 25 outputs "Low level" signal S6, and up-down counter 11 performs an up-count operation.
When the phase of the input signal S2 is advanced from the state where the phase of the input signal S1 is advanced with respect to the input signal S1 at the time Tt, the rising timing of the input signal S2 at the time Tt and the delay waveform S3 shown in FIG. As is apparent, the "high level" of the delay waveform S3 is read into the D flip-flop 25, the "high level" signal S6 is output from the D flip-flop 25, and the up / down counter 11 A down count operation is performed.
Therefore, in the example shown in the timing chart of FIG. 4, the up / down counter 11 increases the count value until time Tt, decreases the count value after time Tt, and changes the input timing signal S4 from “High level”. The count value of the up / down counter 11 when it changes to “Low level” is output. At this time, if the sign of the count value output from the up / down counter 11 is positive, the state where the phase of the input signal S2 is advanced with respect to the input signal S1 occurs more frequently than the state where the phase of the input signal S2 is delayed. If the sign of the count value is negative, it can be determined that the state where the phase of the input signal S2 is delayed with respect to the input signal S1 occurs more frequently than the state where the phase of the input signal S2 is advanced.
As described above, since the count value of the up / down counter 11 increases or decreases according to the phase difference between the input signal S1 and the input signal S2, the pulse width of the input timing signal S4 is increased and the input signal S1 and the input signal S4 are increased. The averaged phase difference with S2 can be detected in a wide range.
[0014]
Embodiment 3 FIG.
Next, a phase difference detection circuit according to the third embodiment will be described.
FIG. 5 is a circuit diagram showing a configuration of the phase difference detection circuit according to the third embodiment. The same or corresponding parts as those in FIG. 3 are denoted by the same reference numerals and description thereof is omitted.
The phase difference detection circuit according to the third embodiment can determine whether the trigger for changing the phase difference detection signal from the exclusive OR circuit 1 from L to H is due to a change in the input signal S1 or the input signal S2, Which of the input signal S1 and the input signal S2 comes first, that is, the determination of the delay or the advance can be obtained from both the signals S1 and S2, so that a wide range of phase difference can be detected with high accuracy.
Also in this phase difference detection circuit, the counter for counting the signal S5 output from the AND circuit 2 is the up / down counter 11, and the signal S6 supplied to the input terminal for setting up counting and down counting is “Low level”. When the signal S6 supplied to the input terminal is at "High level", it functions as a down counter.
Further, the phase difference detection circuit selects an inverter circuit 31 for inverting the input signal S1, a capacitor 27 and a resistor 28 for detecting a rising edge and a falling edge of the input signal S1, and selects and outputs the rising edge. A diode 29 is provided. Further, a capacitor 32 and a resistor 33 for detecting a rising edge and a falling edge of the input signal S1 inverted by the inverter circuit 31 are provided, and a diode 34 for selecting and outputting the rising edge is provided. The cathodes of the diode 29 and the diode 34 are connected to a resistor 38 and a set input terminal of a set / reset flip-flop (averaging phase difference detecting means) 35. The cathodes of the diode 16 and the diode 24 described in the second embodiment are connected to the reset input terminal of the set / reset flip-flop 35. The output of the set / reset flip-flop 35 is connected to the data input terminal of the D flip-flop 25.
A delay circuit including a resistor 36 and a capacitor 37 is disposed between the output side of the exclusive OR circuit 1 and the ground, and the connection point between the resistor 36 and the capacitor 37 is the D flip-flop 25. Clock input terminal.
[0015]
Next, the operation will be described.
FIG. 6 is a timing chart showing the operation of the phase difference detection circuit shown in FIG. 5, and the operation will be described below with reference to this timing chart.
The waveform shown in FIG. 6C is the waveform at the connection point between the resistor 36 and the capacitor 37 when the output of the exclusive OR circuit 1 is supplied to the delay circuit, and the signal S9 represented by this waveform is It is supplied to the clock input terminal of the D flip-flop 25. On the other hand, the set-reset flip-flop 35 is set by a pulse signal generated from the rising edge and the falling edge of the input signal S1, and is reset by a pulse signal generated from the rising edge and the falling edge of the input signal S2. You. FIG. 4D shows the waveform of the signal S8 output from the set / reset flip-flop 35. This signal S8 is supplied to the data input terminal of the D flip-flop 25. Therefore, when the relationship between the delay and the advance between the input signal S1 and the input signal S2 is reversed and the phase of the input signal S2 shifts from the state where the phase of the input signal S2 is advanced with respect to the input signal S1 at the time Tt, the signal becomes At the edge of S9, the "High level" of the signal S8 supplied to the data input terminal is read into the D flip-flop 25, and the "High level" is output from the D flip-flop 25 which has output the "Low level" until then. Then, the up / down counter 11 shifts from an up-count operation to a down-count operation.
When the phase of the input signal S2 is advanced from the state where the phase of the input signal S2 is delayed with respect to the input signal S1, the "Low level" of the signal S8 supplied to the data input terminal at the edge of the signal S9 changes to the D flip-flop. The D flip-flop 25 which has been read into the memory 25 and has been outputting a "High level" until then outputs a "Low level", and the up / down counter 11 shifts from a down counting operation to an up counting operation.
[0016]
In the example shown in the timing chart of FIG. 6, the up / down counter 11 increases the count value until time Tt, decreases the count value after time Tt, and changes the input timing signal S4 from “High level” to “Low”. The count value of the up / down counter 11 at the time of the change to “level” is output. At this time, if the sign of the count value output from the up / down counter 11 is positive, the state in which the phase of the input signal S2 is advanced with respect to the input signal S1 occurs more frequently than the state in which the phase is delayed. If the sign is negative, it can be determined that the state in which the phase of the input signal S2 is delayed with respect to the input signal S1 occurs more frequently than the state in which the phase is advanced.
[0017]
Thus, the set / reset flip-flop 35 is set by the pulse signal generated from each edge of the input signal S1, and the set / reset flip-flop 35 is reset by the pulse signal generated from each edge of the input signal S2. The set / reset flip-flop 35 determines which of S1 and the input signal S2 is input first, and outputs the output of the set / reset flip-flop 35 and the signal S9 output by the exclusive OR circuit 1 to the D flip-flop 25. By outputting the signal, the delay and advance of the input signal S1 and the input signal S2 are determined from the timing of the input signal S1 and the input signal S2 immediately before the occurrence of the phase difference signal as the signal S9. Averaging between input signal S1 and input signal S2 with high accuracy and over a wide range Phase difference can detect.
[0018]
Embodiment 4 FIG.
Next, an inclination angle measuring apparatus using any one of the phase difference detection circuits according to the above embodiments will be described. The tilt angle measuring device according to the fourth embodiment uses the phase difference detection circuit described in the second embodiment.
FIG. 7 is a circuit diagram showing the configuration of the tilt angle measuring device according to the fourth embodiment. In FIG. 7, the same or corresponding parts as those in FIG. The tilt angle measuring device includes an ultrasonic oscillator 41, an ultrasonic receiver 42, and an ultrasonic receiver 43. Also, a frequency dividing circuit 44 that divides the reference clock signal output from the oscillation circuit 3 by 1/500 and converts it into a 20 kHz pulse signal, and performs an AND operation on the output of the frequency dividing circuit 44 and the output timing signal. And an AND circuit 45 that outputs the output of the frequency dividing circuit 44 to the ultrasonic oscillator 41 only during a period in which the output timing signal is supplied. The output terminal of the ultrasonic receiver 42 is connected to one input terminal of the exclusive OR circuit 1, and the output terminal of the ultrasonic receiver 43 is connected to the other input terminal of the exclusive OR circuit 1. I have.
[0019]
Next, the operation will be described.
This inclination angle measuring device divides a 10 MHz reference clock signal oscillated in an oscillation circuit 3 by a frequency dividing circuit 44, converts the frequency into a 20 KHz pulse signal, supplies the pulse signal to an ultrasonic oscillator 41, and oscillates the ultrasonic oscillation. The vibrator 41 is vibrated, and the generated ultrasonic waves are emitted toward the reflecting object. Then, the ultrasonic waves reflected from the reflecting object and returned are received by the ultrasonic receiver 42 and the ultrasonic receiver 43. The ultrasonic receiver 42 outputs the received ultrasonic waves as an electric input signal S1, and the ultrasonic receiver 43 outputs the received ultrasonic waves as an input signal S2.
The phase difference detection circuit used in the tilt angle measuring device has been described in detail in the second embodiment and will not be described here. By detecting the average phase difference between the signal S1 and the input signal S2, the relative angle between the reflecting object and the tilt angle measuring device can be detected.
[0020]
As described above, according to the fourth embodiment, since the phase difference between the input signal S1 and the input signal S2 can be averaged and detected for a plurality of sections, errors due to temperature fluctuations and air fluctuations due to convection can be reduced. The relative angle between the reflecting object and the tilt angle measuring device can be detected.
[0021]
Embodiment 5 FIG.
Next, an inclination angle measuring device according to the eighth embodiment will be described.
When air flows between the reflective object and the ultrasonic oscillator, and between the reflective object and the ultrasonic receiver, two paths emitted from one ultrasonic oscillator 41 as in the inclination angle measuring device of the fourth embodiment. In the configuration in which the ultrasonic waves are received by the respective ultrasonic receivers, one path is shortened according to the direction in which the wind blows, the other path is extended, and each path changes to change the input signal S1 and the input signal S2. Since the phase difference also changes and an error easily occurs, in the tilt angle measuring apparatus according to the fifth embodiment, in order to avoid an error due to wind, an ultrasonic oscillator and an ultrasonic receiver having the same path length from transmission to reception are used. Are prepared in two sets.
[0022]
FIG. 8 is a circuit diagram showing the configuration of the inclination angle measuring apparatus according to the fifth embodiment. In FIG. 8, the same or corresponding parts as those in FIG. In the inclination angle measuring apparatus according to the fifth embodiment, the frequency dividing circuit 44 according to the fourth embodiment includes a 1/250 frequency dividing circuit 51 and a 1/2 frequency dividing circuit 52. Then, the frequency-divided output of 40 kHz of the 1/250 frequency dividing circuit 51 is supplied to the clock input terminal of the D flip-flop 25. Further, the output side of the AND circuit 45 is connected to the other input terminal of the exclusive OR circuit 1 and the terminal on one movable side of the changeover switch (operation switching circuit) 53. One terminal on the fixed contact side of the changeover switch 53 is connected to the input terminal of the ultrasonic oscillator 54. The other terminal on the fixed contact side of the changeover switch 53 is connected to the input terminal of the ultrasonic oscillator 55. An output terminal of the ultrasonic receiver 57 that receives the ultrasonic wave emitted from the ultrasonic oscillator 54 and reflected by the reflecting object is connected to one terminal on a fixed contact side of a changeover switch (operation switching circuit) 58. The output terminal of the ultrasonic receiver 56 that receives the ultrasonic wave emitted from the ultrasonic oscillator 55 and reflected by the reflecting object is connected to the other terminal on the fixed contact side of the changeover switch 58. The terminal on one movable side of the changeover switch 58 is connected to one input terminal of the exclusive OR circuit 1.
[0023]
Next, the operation will be described.
In this tilt angle measuring device, an ultrasonic sensor including an ultrasonic oscillator 54 and an ultrasonic receiver 57, an ultrasonic sensor including an ultrasonic oscillator 55 and an ultrasonic receiver 56, and two sets of ultrasonic sensors are used. The operation is performed alternately so that the ultrasonic signals of the other set do not interfere with each other. Then, using the pulse signal of 20 KHz output from the AND circuit 45 as a reference clock, the changeover switch 53 and the changeover switch 58 are simultaneously switched, and the reference clock is alternately supplied to the ultrasonic oscillator 54 and the ultrasonic oscillator 55, At the same time, the reference clock is supplied to the other input terminal of the exclusive OR circuit 1. Then, the ultrasonic receiver 56 receives an ultrasonic wave and detects a phase difference of the input signal S1 output to the exclusive OR circuit 1 with respect to the reference clock using 20 KHz as a reference clock. Further, the ultrasonic receiver 57 receives the ultrasonic wave and detects a phase difference of the input signal S2 output to the exclusive OR circuit 1 with respect to the reference clock. These phase differences are obtained as outputs of the up / down counter 11. Further, a difference between the respective phase differences with respect to a reference clock is calculated, and a phase difference equivalent to a case where the input signal S1 and the input signal S2 are simultaneously processed in the exclusive OR circuit 1 is detected.
In this way, the two sets of ultrasonic sensors are alternately operated so that the other set of ultrasonic signals does not interfere with each other, and it is possible to easily detect the phase difference between a plurality of input signals that are not input at the same time. A relative angle with the inclination angle measuring device can be detected.
[0024]
In the above-described fourth and fifth embodiments, the case where the phase difference detection circuit is used for the inclination angle measuring device has been described. However, for example, it is necessary to purchase the generated power to a power company. It is necessary to match the phase between the power generated by the generator and the power supplied from the power company side, but in such a case, it may be used to detect and check the phases of the two. It is valid.
[0025]
【The invention's effect】
As described above, according to the present invention, a phase difference information extraction circuit for extracting phase difference information between input signals, at least one of which is intermittently input, and the position extracted by the phase difference information extraction circuit. A phase difference information for detecting an averaged phase difference between the input signals in the period based on a period defining signal defining a period for averaging the phase difference between the input signals. With the configuration including the detection means, there is an effect that an averaged phase difference within an arbitrary period can be detected for an input signal sporadically input using a CPU having a small capacity.
[0026]
According to the present invention, at least one of the sets of ultrasonic receivers obtained by receiving ultrasonic waves reflected from a reflecting object receives phase difference information between input signals intermittently input. The phase difference detecting circuit according to any one of claims 1 to 4, which detects the phase difference to be extracted digitally, is sporadically input from the ultrasonic receiver. With respect to an input signal, there is an effect that a relative angle amount with respect to a reflecting object can be detected by using an averaged phase difference within an arbitrary period detected using a CPU having a small capacity.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a phase difference detection circuit according to Embodiment 1 of the present invention.
FIG. 2 is a timing chart showing an operation of the phase difference detection circuit according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a phase difference detection circuit according to a second embodiment of the present invention.
FIG. 4 is a timing chart illustrating an operation of the phase difference detection circuit according to the second embodiment of the present invention;
FIG. 5 is a circuit diagram showing a configuration of a phase difference detection circuit according to Embodiment 3 of the present invention.
FIG. 6 is a timing chart showing an operation of the phase difference detection circuit according to the third embodiment of the present invention.
FIG. 7 is a circuit diagram showing a configuration of a tilt angle measuring device according to a fourth embodiment of the present invention.
FIG. 8 is a circuit diagram showing a configuration of a tilt angle measuring device according to a fifth embodiment of the present invention.
[Explanation of symbols]
1 Exclusive OR circuit (phase difference information extraction circuit), 2,45 AND circuit (phase difference information extraction circuit), 4 counter (averaging phase difference detection means, counting circuit), 5 CPU (averaging phase difference detection means) , Arithmetic means), 11 up / down counter, 12, 15, 23, 33, 36, 38, 39 resistor, 16, 24, 29, 34 diode, 13, 22, 32, 37 capacitor, 21, 31 inverter circuit, 25 D flip-flop (averaging phase difference detecting means), 35 set reset flip-flop (averaging phase difference detecting means), 41, 54, 55 ultrasonic oscillator, 42, 43, 56, 57 ultrasonic receiver, 44, 51, 52 frequency divider circuit, 53, 58 selector switch (operation switching circuit).

Claims (5)

In a phase difference detection circuit that digitally detects a phase difference between input signals,
A phase difference information extraction circuit that extracts phase difference information between input signals at least one of which is intermittently input,
Based on the phase difference information extracted by the phase difference information extraction circuit and a period defining signal that defines a period for averaging the phase difference between the input signals, the input signal averaged in the period. An averaged phase difference detecting means for detecting a phase difference between the two. The averaging phase difference detection means includes: a counting circuit that calculates a total number of pulses according to the phase difference information extracted by the phase difference information extraction circuit within a period defined based on the period defining signal; Operating means for averaging the sum of the number of pulses according to the phase difference information based on the number of times the phase difference information extraction circuit has extracted the phase difference information within the period. The phase difference detection circuit according to claim 1, wherein: The averaging phase difference detection means adds or subtracts the number of pulses according to the phase difference information extracted by the phase difference information extraction circuit within a period defined based on the period defining signal according to the delay or advance of the input signal. 2. The phase difference detecting circuit according to claim 1, further comprising a counting circuit for detecting a phase difference between the input signals averaged in the period. In a phase difference detection circuit that digitally detects a phase difference between input signals,
For each input signal at least one of which is intermittently input, a phase difference information extraction circuit that extracts phase difference information from a reference clock,
The phase difference information extracted by the phase difference information extraction circuit for each of the input signals, and a period defining signal that defines a period for averaging the phase difference information of each of the input signals, based on an average within the period. Averaging for detecting phase difference information of each of the converted input signals, further obtaining a difference between the detected phase difference information of each of the input signals, and detecting a phase difference between the input signals averaged in the period. And a phase difference detecting means. An ultrasonic path length from transmission of ultrasonic waves to reception is equal, a plurality of pairs of ultrasonic oscillators and ultrasonic receivers are provided, and a relative angle amount with respect to a reflecting object that reflects the transmitted ultrasonic waves. In the tilt angle measurement device that detects based on the phase difference between input signals obtained by receiving the ultrasonic waves reflected by the reflecting object by the ultrasonic receivers of each set,
Each of the sets of ultrasonic receivers is obtained by receiving ultrasonic waves reflected from the reflecting object, at least one of which is digitally detects a phase difference between input signals intermittently input. An inclination angle measuring device, comprising: the phase difference detection circuit according to claim 1.

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