JP2004200311A - Logic verifying device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic verifying device which is capable of verifying a large-scale logic circuit with a few FPGA chips. <P>SOLUTION: The logic verifying device comprises FPGAs which can be dynamically reconfigured, a configuration memory storing a plurality of configuration data, and a first selection circuit which repeats a cycle of successively selecting the plurality of configuration data and writing them all in the FPGAs a few times. The logic realized by the configuration data on the FPGAs is successively replaced with new one in each writing operation. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to LSI logic verification, and more particularly, to an apparatus for performing LSI logic verification using a reconfigurable FPGA.
[Prior art]
The FPGA (Field Programmable Gate Array) is a programmable general-purpose logic LSI, in which wiring connection inside the LSI is controlled according to configuration data written in a memory, and realizes a desired hardware configuration. The FPGA is used, for example, as an emulator that executes logic verification in designing a logic circuit.
[0002]
The logic verification device maps a logic circuit on hardware, configures a circuit that operates at high speed as hardware, and performs logic verification. Since this hardware emulator operates at a speed several thousand to tens of thousands times faster than a software simulator, it is very effective for logic verification of a large-scale circuit.
[0003]
When performing logic verification by mapping a logic circuit to an FPGA, the circuit scale of the circuit to be verified may be too large to be mounted on one FPGA chip. In such a case, the conventional technology prepares a plurality of FPGA chips, divides a logic circuit to be verified into a plurality of blocks that can be accommodated in one FPGA chip, and maps the plurality of blocks to each FPGA chip. Was.
[0004]
Also, by reconfiguring an FPGA or the like in the middle of processing so as to realize different logic circuits at different times, a circuit of a scale that cannot be realized by one programmable logic circuit device can be realized. In such a case, by aligning the layout of the reconfigurable circuit to a predetermined size and shape, it is relatively easy to match the shape and size of the free space with the shape and size of the reconfigurable circuit at the time of reconfiguration. There is a conventional technique that can perform the above-described method (Patent Document 1).
[0005]
Also, when the scale of a logic circuit to be realized in an FPGA is large, instead of switching the functions of a plurality of logic blocks all at once, a change in a wiring signal between the logic blocks is detected, and the logic definition information of the logic circuit unit is automatically converted. There is a prior art in which the switching is performed at high speed in accordance with the order (Japanese Patent Application Laid-Open No. H10-163873).
[0006]
[Patent Document 1]
Japanese Patent Application Laid-Open No. H11-017524 [Patent Document 2]
JP 10-173515 A [Problems to be Solved by the Invention]
In a configuration in which a plurality of FPGA chips are prepared, when the scale of the logic circuit to be verified increases, the number of necessary FPGA chips increases, and there is a problem that the operation speed cannot be increased due to a wiring delay between the FPGA chips. In addition, when the number of FPGA chips increases, there is a problem that the device configuration becomes complicated and realization becomes difficult.
[0007]
In view of the above, an object of the present invention is to provide a logic verification device capable of verifying a large-scale logic circuit with a small number of FPGA chips.
[Means for Solving the Problems]
A logic verification device according to the present invention includes a dynamically reconfigurable FPGA, a configuration memory storing a plurality of configuration data, and an operation of sequentially selecting the plurality of configuration data and sequentially writing the configuration data to the FPGA. A first select circuit that repeats a cycle executed for all of the plurality of configuration data a plurality of times, wherein a logic realized on the FPGA by the configuration data is replaced every time the sequential writing operation is performed; I do.
[0008]
In the logic verification device, a series of operations for sequentially selecting and writing a plurality of configuration data to a dynamically reconfigurable FPGA is repeated for a plurality of cycles, and the logic realized on the FPGA by the configuration data is repeated. Replace in order. Thus, if the circuit to be verified is divided into a plurality of logical blocks and the respective configuration data are prepared, even if the circuit size of the circuit to be verified is larger than the size of the reconfiguration area of the FPGA, By sequentially executing the logic blocks, the logic of the entire circuit to be verified can be realized.
[0009]
According to a further aspect of the present invention, the logic verification device includes a circuit state memory for storing, for each of the plurality of configuration data, a circuit state of a circuit realized on the FPGA by writing configuration data. And a second select circuit that reads the circuit state corresponding to the circuit realized on the FPGA from the circuit state memory by writing the configuration data to the FPGA and sets the circuit state on the FPGA. It is further characterized by including.
[0010]
In the above configuration, the circuit state of the circuit realized on the FPGA is stored in the circuit state memory, so that when the circuit is sequentially replaced on the FPGA and realized sequentially, The state can be restored the next time it is restarted.
[0011]
According to still another aspect of the present invention, the logic verification device further includes a storage device, and a wiring circuit capable of freely configuring a wiring connection between the storage device and the FPGA, and further comprising a first cycle. And stores the value output from the circuit realized on the FPGA in the storage device via the wiring circuit, and stores the value of the circuit realized on the FPGA in the storage device in the second cycle The input value is input via the wiring circuit.
[0012]
In the above configuration, in a state where a plurality of logical blocks do not exist at the same time and are realized one by one sequentially, the storage device stores a signal value to transmit a signal between the logical blocks over time. By doing so, mediation between different times can be performed, and further, by using a freely configurable wiring circuit, an appropriate signal path can be provided to different logic blocks at any time.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0014]
FIG. 1 is a configuration diagram showing an example of the configuration of the first embodiment of the logic verification device according to the present invention.
[0015]
1 includes a dynamically reconfigurable FPGA 11, configuration memories 12-1 to 12-N, circuit state memories 13-1 to 13-N, a select circuit 14, a select circuit 15, and a wiring circuit 16. , A storage device 17, a buffer 18, and a control circuit 19. The control circuit 19 supplies a control signal to each memory and each circuit, and controls the operation of each memory and each circuit.
[0016]
The dynamically reconfigurable FPGA 11 implements the logic 11a of the circuit to be verified in a reconfigurable manner based on the configuration data stored in the configuration memories 12-1 to 12-N. Each of the configuration memories 12-1 to 12-N divides a circuit to be verified into a plurality of N logic blocks, and stores configuration data necessary to realize the logic of each logic block.
[0017]
The select circuit 14 selects one of the configuration memories 12-1 to 12-N and writes the configuration data stored therein to the dynamically reconfigurable FPGA 11. As a result, the logic of the logic block of the circuit to be verified corresponding to the selected configuration memory is realized as the logic 11a on the logic verification device 10.
[0018]
For example, the configuration memory 12-1 is selected first, and the corresponding first logic block of the circuit to be verified is realized in the dynamically reconfigurable FPGA 11. Next, the configuration memory 12-2 is selected, and the corresponding second logic block of the circuit to be verified is implemented in the dynamically reconfigurable FPGA 11. The same operation is performed for each logic block, and finally, the configuration memory 12-N is selected, and the Nth logic block of the circuit to be verified is realized in the dynamically reconfigurable FPGA 11. Thus, one cycle is completed. By repeating this cycle, an operation according to each cycle for the entire circuit to be verified is realized.
[0019]
The N circuit state memories 13-1 to 13-N correspond to the N configuration memories 12-1 to 12-N, and the circuit states (internal states) of the logic blocks realized on the dynamically reconfigurable FPGA 11 are stored. (A value of a flip-flop) for each cycle. That is, for example, when the first logical block corresponding to the configuration memory 12-1 is operated on the dynamically reconfigurable FPGA 11, the configuration data of the next second logical block is loaded into the dynamically reconfigurable FPGA 11. Before the operation, the circuit state of the first logic block on the dynamically reconfigurable FPGA 11 is stored (saved) in the circuit state memory 13-1. Thereby, when the first logic block is operated again on the dynamically reconfigurable FPGA 11 in the next cycle, the circuit state is read from the circuit state memory 13-1 and written to the dynamically reconfigurable FPGA 11. The circuit operation can be resumed from the last interrupted state.
[0020]
For this purpose, the select circuit 15 selects a circuit state memory corresponding to the selected configuration memory. The select circuit 15 reads a circuit state from a selected one of the circuit state memories 13-1 to 13-N, and writes the circuit state into the dynamically reconfigurable FPGA 11. Here, each of the circuit state memories 13-1 to 13-N is shown as including a plurality of (three in the figure) memories, which are circuit state data for a plurality of cycles from the past to the present. Is stored. As shown in FIG. 1, the select circuit 15 has an external I / O, and outputs the contents of the circuit state memories 13-1 to 13-N to the outside. Thereby, the state of the logic realized on the dynamically reconfigurable FPGA 11 can be externally observed as necessary.
[0021]
FIG. 2 is a timing chart showing an operation of realizing a plurality of logical blocks by the dynamically reconfigurable FPGA 11.
[0022]
FIG. 2 shows a case where the number N of blocks is 3, and the internal clock is set to a frequency six times that of the external clock. Here, the external clock corresponds to the operation clock of the circuit to be verified, and one cycle of the operation of the circuit to be verified is performed during one cycle of the external clock. The internal clock is a clock for realizing the operation of a plurality of logic blocks during one cycle of the external clock, and has a frequency 2N times that of the external clock when there are N logic blocks. The select circuits 14 and 15 operate in synchronization with the internal clock.
[0023]
In the first cycle of the internal clock shown in FIG. 2, the configuration of the first logic block is executed, and the circuit state of the previously executed third logic block is saved. Is loaded. As a result, the first logical block is realized on the dynamically reconfigurable FPGA 11, and is restored to the circuit state at the time when the operation was interrupted last time. Next, in the second cycle of the internal clock, the operation for one clock of the first logic block is executed.
[0024]
In the third cycle of the internal clock, the configuration of the second logic block is executed, and the circuit state of the first logic block that has been executed before is saved, and thereafter, the configuration of the second logic block is saved. The circuit state is loaded. As a result, the second logic block is realized on the dynamically reconfigurable FPGA 11, and is restored to the circuit state at the time when the operation was interrupted last time. In the fourth cycle of the internal clock, the operation of one clock of the second logic block is executed.
[0025]
In the fifth cycle of the internal clock, the configuration of the third logic block is performed, and the circuit state of the previously executed second logic block is saved. The circuit state is loaded. As a result, the third logic block is realized on the dynamically reconfigurable FPGA 11, and is restored to the circuit state at the time when the operation was interrupted last time. In the sixth cycle of the internal clock, the operation of one clock of the third logic block is executed.
[0026]
As described above, the first to third logic blocks of the circuit to be verified are sequentially realized on the dynamically reconfigurable FPGA 11 during one cycle of the external clock, and the operation for one cycle is executed for each of them.
[0027]
FIG. 3 is a diagram for explaining an operation of loading and saving a circuit state between a dynamically reconfigurable FPGA and a circuit state memory. In FIG. 3, it is assumed that the verification target circuit is divided into three logical blocks.
[0028]
As schematically illustrated in FIG. 3, the logic 11 a realized by the dynamically reconfigurable FPGA 11 includes a flip-flop 21 (which is schematically illustrated as one in FIG. This is expressed as a configuration including a combinational logic circuit 22 that receives the value of the flip-flop 21 as an input and a flip-flop 23 (schematically shown as one in the figure, but may be plural) that stores the output of the combinational logic circuit 22. The select circuit 15 reads the circuit state from the circuit state memory 13-1 when implementing, for example, a first logical block as the logic 11a on the dynamically reconfigurable FPGA 11, and sets the set input S of the flip-flops 21 and 23. Write circuit state data from. Thereby, the first logic block is reproduced so as to have the circuit state at the time of the previous interruption.
[0029]
After the first logic block operates for one clock on the dynamically reconfigurable FPGA 11, the select circuit 15 stores the output value Q of the flip-flops 21 and 23 in the circuit state memory 13-1. As a result, the current circuit state of the first logic block can be saved in the circuit state memory 13-1. After the second and third logical blocks are realized, when the first logical block is realized again with the next clock, the circuit state data stored in the circuit state memory 13-1 is read out, thereby making the circuit It can be restored based on the state.
[0030]
Hereinafter, signal transfer between logical blocks will be described.
[0031]
FIG. 4 is a diagram schematically illustrating logical block division of a circuit to be verified.
[0032]
In the example shown in FIG. 4, the circuit to be verified is divided into a first logic block 31, a second logic block 32, and a third logic block 33. The first logical block 31 is connected to the external I / O 34 via I / O1 and I / O2. The first logic block 31 is further connected to the second logic block 32 via signal paths P1 and P2, and connected to the third logic block 33 via signal paths P3 and P4. The second logic block 32 and the third logic block 33 are connected via signal paths P5 and P6.
[0033]
However, as described above, in the present invention, since each logical block is realized one by one on the dynamically reconfigurable FPGA 11, two or more logical blocks are not realized at the same time. That is, the first logic block 31 to the third logic block 33 schematically shown in FIG. 4 do not exist at the same time, and are realized one by one sequentially with time. Therefore, the signal paths P1 to P6 between the logical blocks need to transfer signals between regions having different timings over time, and realize such a function to support signal transfer between the logical blocks. A mechanism to do this is required.
[0034]
In FIG. 1, a wiring circuit 16 and a storage device 17 are provided to realize signal transfer between logical blocks.
[0035]
The wiring circuit 16 is for emulating signal wiring between the logical blocks, and is realized by, for example, a reconfigurable FPGA chip. The wiring circuit 16 provides a desired signal wiring by configuring a desired logic on the FPGA. Since each logical block is not simultaneously realized on the dynamically reconfigurable FPGA 11, the storage device 17 temporarily stores the value of the transferred signal in order to realize the signal transfer between the logical blocks. It is a memory for mediating. For example, the storage device 17 may be a FIFO (First In First Out) memory that inputs a signal value at a certain clock timing and outputs a signal value at the next clock timing.
[0036]
FIG. 5 is a diagram showing a specific configuration of the wiring circuit 16, the storage device 17, and the buffer 18.
[0037]
As shown in FIG. 5, the wiring circuit 16 is realized as a wiring FPGA, and the storage device 17 is realized as a FIFO. The FIFO 17 includes memory elements b1 to b6 capable of storing six values corresponding to the six signal paths P1 to P6 in FIG. For example, in the m-th cycle of the external clock, by establishing an appropriate wiring connection between the dynamically reconfigurable FPGA 11 and the FIFO 17 by the wiring FPGA 16, the first logic block 31 to the third logic block 33 are established. Are stored in the memory elements b1 to b6 of the FIFO 17 from the respective signal paths P1 to P6. In the next (m + 1) -th cycle of the external clock, the values of the memory elements b1 to b6 are transferred to the memory elements a1 to a6. The values of the memory elements a1 to a6 are transferred to the corresponding signal paths P1 to P6 of the dynamically reconfigurable FPGA 11 by establishing an appropriate wiring connection between the FIFO 17 and the dynamically reconfigurable FPGA 11 by the wiring FPGA 16. Supplied.
[0038]
As shown in FIG. 5, for example, when the first logic block is realized, the signal paths P1 and P3 are connected to the memory elements b1 and b3 by the wiring FPGA 16 and output to the signal paths P1 and P3. Are stored in memory elements b1 and b3, respectively. The values stored in the memory elements b1 and b3 are used in the next cycle. The signal paths P2 and P4 are connected to the memory elements a2 and a4, respectively, by the wiring FPGA 16, and the values stored in the memory elements a2 and a4 are supplied to the signal paths P2 and P4. The values of the memory elements a2 and a4 are the values stored in b2 and b4 in the previous cycle.
[0039]
In addition, the wiring FPGA 16 establishes an appropriate wiring path between the dynamically reconfigurable FPGA 11 and the buffer 18 so that the signal path I for connecting the first logic block 31 to the external I / O 34 is established. Appropriate data transfer via / O1 and I / O2 is realized. Here, the external I / O 34 operates at a speed of 1/6 of the internal clock in synchronization with the external clock shown in FIG. Therefore, in order to realize signal transfer between different clock speeds, a buffer 18 is provided to hold a value exchanged with an external I / O.
[0040]
Hereinafter, a second embodiment of the logic verification device according to the present invention will be described.
[0041]
6A shows a dynamically reconfigurable FPGA provided with configuration data outside the chip, and FIG. 6B shows a dynamically reconfigurable FPGA provided with configuration data inside the chip.
[0042]
3A, the logic block 47 is realized on the dynamically reconfigurable FPGA 41, but the configuration memories 43 to 45 and the select circuit 46 are realized as independent devices outside the dynamically reconfigurable FPGA 41. Is done. On the other hand, in the dynamically reconfigurable FPGA having configuration data inside the chip shown in FIG. 3B, the configuration memories 48 to 50, the select circuit 51, and the logic block 52 are all composed of the dynamically reconfigurable FPGA 42. Realized inside. In this case, the logical configuration is reconfigured only in the logical block 52, and the FPGA portions corresponding to the configuration memories 48 to 50 and the select circuit 51 are fixed to predetermined wiring.
[0043]
In the first embodiment shown in FIG. 1, only the logic 11a of the logic block of the circuit to be verified is realized in the dynamically reconfigurable FPGA 11. On the other hand, as in the configuration shown in FIG. 6B, it is conceivable that a logic configuration other than the circuit to be verified is also realized in a dynamically reconfigurable FPGA.
[0044]
FIG. 7 is a configuration diagram showing an example of the configuration of the second embodiment of the logic verification device according to the present invention.
[0045]
7 includes a dynamically reconfigurable FPGA 60, configuration memories 12-1 to 12-3, circuit state memories 13-1 to 13-3, a select circuit 14, a select circuit 15, and a wiring circuit 16. , A storage device 17, a buffer 18, and a control circuit 19. The control circuit 19 supplies a control signal to each memory and each circuit, and controls the operation of each memory and each circuit. In FIG. 7, the realizing means as a specific hardware as in FIG. 1 is referred to by the same symbol, even if it is realized by a logical configuration.
[0046]
In the logic verification device 10A of FIG. 7, all the circuits constituting the logic verification device 10A are built in the dynamically reconfigurable FPGA 60. These circuits can be easily realized by using the internal logic of the dynamically reconfigurable FPGA 60. As described above, in the second embodiment, the logic verification function is realized by one dynamically reconfigurable FPGA chip.
[0047]
In FIG. 7, all the circuits constituting the logic verification device 10A are built in the dynamically reconfigurable FPGA. However, only specific circuits are built in the FPGA, and the other circuits are provided as independent devices. You may. For example, when a large capacity memory is required as the configuration memory or the circuit state memory, using a dedicated memory device is more efficient than using a part of the FPGA as the memory.
[0048]
As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims.
【The invention's effect】
In the logic verification device according to the present invention, a series of operations of sequentially selecting and writing a plurality of configuration data to a dynamically reconfigurable FPGA is repeated for a plurality of cycles, and is realized on the FPGA by the configuration data. Change logic sequentially. Thus, if the circuit to be verified is divided into a plurality of logical blocks and the respective configuration data are prepared, even if the circuit size of the circuit to be verified is larger than the size of the reconfiguration area of the FPGA, By sequentially executing the logic blocks, the logic of the entire circuit to be verified can be realized.
[0049]
By storing the circuit state of the circuit realized on the FPGA in the circuit state memory, when the circuits are sequentially replaced on the FPGA and realized sequentially, the circuit state of the circuit whose operation has been interrupted is restarted next time. Sometimes it can be restored and restarted from that circuit state.
[0050]
Further, in a state where a plurality of logical blocks are sequentially realized one by one, in order to transmit signals between the logical blocks over time, the storage device stores a signal value to mediate between different times. Further, by using a freely configurable wiring circuit, an appropriate signal path can be provided to different logic blocks as needed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an example of a configuration of a first embodiment of a logic verification device according to the present invention.
FIG. 2 is a timing chart showing an operation of implementing a plurality of logical blocks by a dynamically reconfigurable FPGA.
FIG. 3 is a diagram for explaining an operation of loading and saving a circuit state between a dynamically reconfigurable FPGA and a circuit state memory.
FIG. 4 is a diagram schematically illustrating logical block division of a circuit to be verified.
FIG. 5 is a diagram showing a specific configuration of a wiring circuit, a storage device, and a buffer shown in FIG. 1;
6A is a diagram illustrating a dynamically reconfigurable FPGA having configuration data outside the chip, and FIG. 6B is a diagram illustrating a dynamically reconfigurable FPGA including configuration data inside the chip. .
FIG. 7 is a configuration diagram showing an example of a configuration of a second embodiment of the logic verification device according to the present invention.
[Explanation of symbols]
11 Dynamically Reconfigurable FPGA
12-1 to 12-N Configuration memories 13-1 to 13-N Circuit state memory 14 Select circuit 15 Select circuit 16 Wiring circuit 17 Storage device 18 Buffer 19 Control circuit

Claims (10)

A dynamically reconfigurable FPGA;
A configuration memory for storing a plurality of configuration data;
A first select circuit that repeats a plurality of cycles of sequentially selecting the plurality of configuration data and sequentially writing the plurality of configuration data to the FPGA for all of the plurality of configuration data; A logic verifying device characterized in that the logic implemented above is exchanged for each successive writing operation. 2. The logic verification device according to claim 1, wherein a total circuit size of a plurality of circuits corresponding to the plurality of configuration data is larger than a capacity of the FPGA. A circuit state memory for storing a circuit state of a circuit realized on the FPGA by writing the configuration data for each of the plurality of configuration data;
A configuration further includes a second select circuit that reads the circuit state corresponding to the circuit realized on the FPGA from the circuit state memory by writing the configuration data to the FPGA and sets the circuit state on the FPGA. 2. The logic verification device according to claim 1, wherein: 4. The circuit according to claim 3, wherein the second select circuit stores the circuit state of the executed circuit after the operation is executed in the circuit state memory after the circuit implemented on the FPGA executes the operation. Logic verification device. 4. The logic verification device according to claim 3, wherein the second select circuit includes a path for outputting the circuit status stored in the circuit status memory to the outside of the logic verification device. 2. The logic verification device according to claim 1, wherein the circuit state memory stores the circuit state for each of the plurality of configuration data and for each of the cycles. A storage device,
A wiring circuit that can freely configure a wiring connection between the storage device and the FPGA; and a value output from a circuit realized on the FPGA in a first cycle through the wiring circuit. And inputting the value stored in the storage device to a circuit realized on the FPGA in a second cycle through the wiring circuit. Item 6. The logic verification device according to Item 1. The circuit further includes a buffer circuit provided between the outside of the logic verification device and the wiring circuit, and the wiring circuit is configured to freely configure a wiring connection between the FPGA and the buffer circuit. 8. The logic verification apparatus according to claim 7, wherein said buffer circuit holds a value output from a circuit realized on said FPGA for a predetermined period. 8. The logic verification device according to claim 7, wherein the storage device is a FIFO memory that shifts data in each cycle. 8. The logic verification device according to claim 7, wherein the wiring circuit is realized by an FPGA.

Images