JP2004199404A - Bus arbitration device and semiconductor integrated circuit provided with it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the bus using right is hardly acquired when a low prioritized module requests a bus since the bus is allocated with time division for every constant time period in a conventional bus arbitration method. <P>SOLUTION: This bus arbitration device receives bus requests from a plurality of modules connected to the bus, time-divides a basic bus cycle and makes each module occupied. The bus throughput is improved by providing a storage section 108a for acquiring information regarding the bus request in each basic bus cycle and at least temporarily store the information, and an arbitration processing section 108b for determining a bus occupying period of each module in the respective basic bus cycle on the basis of the information stored in the storage section 108a. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit in which a plurality of modules are connected via a bus, and more particularly, to a bus arbitration device that arbitrates a bus request from the plurality of modules.
[0002]
[Prior art]
Conventionally, when performing data transfer between a plurality of modules via a bus, the IP side sets priorities as a method of acquiring the right to use the bus, and dynamically changes the order to meet different congestion conditions. Was compatible.
[0003]
A conventional multiplexer that dynamically controls the priority of a plurality of bus requesters is disclosed in, for example, Patent Document 1.
[0004]
[Patent Document 1]
JP-A-5-37480
[Problems to be solved by the invention]
However, in the bus arbitration method, since the bus is allocated in a time-division manner in units of a fixed time, it may be difficult to obtain the right to use the bus even if a low priority module requests the bus.
[0006]
[Means for Solving the Problems]
In order to solve the above-described problems, a bus arbitration device of the present invention is a bus arbitration device that receives a bus request from a plurality of modules connected to a bus, and divides a basic bus cycle by time to occupy each module. A bus request status storage unit for acquiring and storing information on a bus request status of each module in a basic bus cycle, and a ratio of a bus occupation period of each module in each basic bus cycle to a basic bus immediately before the basic bus cycle. An arbitration processing unit that is obtained from at least one past basic bus cycle including a cycle and that is determined based on the information stored in the bus request status storage unit.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
The above-described bus arbitration device (first configuration) of the present invention determines the bus occupation time in each basic bus cycle in accordance with the number of bus requests in the past basic bus cycle, thereby responding to the bus usage status. Bus arbitration can be performed dynamically and appropriately.
[0008]
Further, in the bus arbitrating device according to the above-described first configuration, the number of bus requests of each module in each basic bus cycle can be used as the information on the bus request status. Alternatively, as the information on the bus request status, the number of bus requests of each module in each basic bus cycle and the timing of each of the bus requests can be used.
[0009]
In the bus arbitration device of the first configuration described above, the arbitration processing unit monitors a bus request from each module in each basic bus cycle, and the module does not issue a bus request until the occupation period assigned to each module. In this case, it is preferable to cancel the bus assignment to the module. As a result, the overall bus transfer efficiency can be improved. As described above, when the arbitration processing unit cancels the bus assignment to any module in each basic bus cycle, if the length of the basic bus cycle is reduced, the transfer efficiency can be further improved. More preferred.
[0010]
Further, in order to solve the above problem, a bus arbitration device according to a second configuration of the present invention receives a bus request from a plurality of modules connected to a bus, and time-divides a basic bus cycle into each module. In the bus arbitration device to be occupied, a bus request status storage unit that obtains information on a bus request status of each module in each basic bus cycle and stores the information at least temporarily, and information stored in the bus request status storage unit in advance. By comparing with a predetermined condition, the priority of the bus request from each module is determined, and the basic bus is requested so that the bus request of the module determined to have a relatively higher priority is given priority. An arbitration processing unit for changing a bus assignment in a cycle or a next basic bus cycle is provided.
[0011]
With this configuration, it is possible to dynamically and appropriately perform bus arbitration in accordance with the bus usage status and the priority of each bus request.
[0012]
In the bus arbitration device having the second configuration, the arbitration processing unit determines that the occupation period assigned to the module determined to be relatively low in priority in each basic bus cycle is relatively high in priority. It is good also as a structure which changes to the occupation period of the module performed. Alternatively, the arbitration processing unit may assign, in each basic bus cycle, an occupation period of a module determined to be relatively high priority before an occupation period assigned to a module determined to be relatively low priority. May be inserted, and in this case, it is more preferable to extend the length of the basic bus cycle. Alternatively, the arbitration processing unit assigns, in each basic bus cycle, the order of the occupation period assigned to the module determined to be relatively high priority to the module determined to be relatively low priority. It is also possible to replace the occupation period so that it is chronologically earlier than the occupation period.
[0013]
In the bus arbitration device of the second configuration, the arbitration processing unit assigns, at the beginning of the next basic bus cycle, an occupation period to be assigned to a module determined to have a relatively low priority, with a relatively high priority. May be changed to the occupation period of the module determined to be high. Alternatively, the arbitration processing unit determines that the priority is relatively high before the occupation period to be assigned to the module determined to be relatively low in priority at the beginning of the next basic bus cycle. The occupation period of the module may be inserted. In this case, it is more preferable to extend the length of the basic bus cycle in which the occupation period is inserted. Alternatively, the arbitration processing unit replaces the occupation period of each module in the next basic bus cycle such that the occupation period of the module determined to be relatively high in the next basic bus cycle is first. It is good also as composition.
[0014]
In order to solve the above problem, a bus arbitration device according to a third configuration of the present invention receives a bus request from a plurality of modules connected to a bus, and time-divides a basic bus cycle into each module. In the bus arbitration device to be occupied, from each module, data on the allowable time from issuing a bus request to acquiring the bus and data on the desired use time of the bus are obtained, and using the data, each data in the next basic bus cycle is obtained. An arbitration processing unit that determines a ratio of a bus occupation time of a module, wherein the arbitration processing unit shortens a basic bus cycle by discarding a bus request when transfer cannot be started before the allowable time elapses. It is characterized by.
[0015]
With this configuration, bus arbitration can be performed dynamically and appropriately according to the conditions of the bus request from each module.
[0016]
In the bus arbitrating device according to the third configuration, when each module issues a bus request, the module sends to the arbitration processing unit discardability data indicating whether the bus request can be discarded, and the arbitration processing unit When the discardability data indicates that discarding is not possible, it is preferable not to discard the bus request but to extend the basic bus cycle and perform bus assignment for the bus request.
[0017]
Further, a semiconductor integrated circuit provided with the bus arbitration device having any one of the above-described configurations is also an embodiment of the present invention.
[0018]
Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.
[0019]
FIG. 1 is a block diagram illustrating the configuration of the semiconductor integrated circuit according to the present embodiment. In FIG. 1, 101 to 104 are master-side IPs, 105 and 106 are slave-side IPs, 107 is a bus for sharing data, and 108 is an arbiter having a bus arbitration function. In this semiconductor integrated circuit, when a bus request signal is output from the master-side IPs 101 to 104 to the arbiter 108, the arbiter 108 allocates the basic bus cycle to the IPs 101 to 104 in a time-sharing manner.
[0020]
The arbiter 108 at least temporarily stores data relating to the bus request from each IP, such as the number of bus requests, the timing, and the presence or absence of a priority bus request, in the storage unit 108a. The arbitration processing unit 108b performs bus assignment in each basic bus cycle based on the data in the storage unit 108a.
[0021]
Hereinafter, a specific example of the arbitration process in the bus arbitration device according to the present embodiment will be described with reference to FIGS.
[0022]
(1st Embodiment)
In the first embodiment, the number of bus requests from each IP is stored in the storage unit 108a of the arbiter 108 for each basic bus cycle, and the arbitration processing unit 108b determines the bus assignment in each basic bus cycle by This is performed according to the number of bus requests in the previous basic bus cycle.
[0023]
As shown in FIG. 2, it is assumed that in a certain basic bus cycle (t2), the number of bus requests from IP 102 has increased and the number of bus requests from IP 101, IP 103, and IP 104 has not changed. The arbitration processing unit 108b obtains the ratio of the bus occupation time in the next basic bus cycle (t3) by proportional distribution by dividing the number of bus requests from each IP by the total number of bus requests in the basic bus cycle. That is, in the example shown in FIG. 2, in the basic bus cycle t3, the bus occupation time is given to each of IP101, IP102, IP103, and IP104 at a ratio of 1: 2: 1: 1. In FIG. 2, (1) indicates the occupation time assigned to the IP 101, and (2) to (4) similarly indicate the occupation time assigned to each of the IPs 102 to 104. The same applies to FIGS. 3 to 8 described later.
[0024]
As described above, by determining the bus occupation time in each basic bus cycle according to the number of bus requests in the past basic bus cycle, it is possible to dynamically and appropriately perform bus arbitration in accordance with the bus usage status. .
[0025]
In the example of FIG. 2, the bus occupation time in each basic bus cycle is determined using the number of bus requests in the immediately preceding basic bus cycle. Statistics on the number of bus requests in a cycle may be used. Alternatively, it is possible to use the statistics of the basic bus cycle not immediately before but two or more before. In addition to simply proportionally allocating the bus occupation time based on the number of bus requests, for example, increasing or decreasing the number of bus requests in the immediately preceding two or three or more basic bus cycles, and the priority of each IP or each bus request For example, the bus occupation time may be determined in consideration of various factors.
[0026]
(Second embodiment)
In the second embodiment, the number of bus requests from each IP and the timing thereof are stored in the storage unit 108a of the arbiter 108 for each basic bus cycle, and the arbitration processing unit 108b sets the bus allocation in each basic bus cycle. Is performed in accordance with the number of bus requests and its timing in the immediately preceding basic bus cycle.
[0027]
As shown in FIG. 3, it is assumed that there are a total of five bus requests in the order of IP104, IP103, IP102, IP101, and IP102 in a certain basic bus cycle (t2). The storage unit 108a stores the number of times that each of the IPs 101 to 104 has issued a bus request in the basic bus cycle t2, and the timing at which the bus request signal has been issued.
[0028]
The arbitration processing unit 108b determines the bus assignment in the basic bus cycle t3 as follows. First, the length of the unit time occupied by each IP is determined by dividing the length of the basic bus cycle t3 by the total number of bus requests in the basic bus cycle t2. Then, according to the timing (order) of the bus request signal in the basic bus cycle t2, each IP occupies the bus for each unit time.
[0029]
Thereby, as shown in FIG. 3, when the total number of bus requests in the basic bus cycle t2 is five, the length of the basic bus cycle t3 is divided into five equal parts, and the order of the bus requests in the basic bus cycle t2 is changed. (IP104, IP103, IP102, IP101, and IP102) are assigned bus occupation.
[0030]
By performing the arbitration by the arbitration processing unit 108b in this way, the bus arbitration can be dynamically and appropriately performed according to the bus usage status.
[0031]
In the above description, the number of bus requests in the immediately preceding basic bus cycle is used to determine the unit time of bus occupancy. However, for example, the bus requests in the immediately preceding two or more basic bus cycles are used. Statistics of the number of times may be used. Alternatively, it is possible to use the statistics of the basic bus cycle not immediately before but two or more before. Also, the bus occupation time allocated to each IP may not be uniform, and may be determined in consideration of various factors such as the priority of each IP.
[0032]
(Third embodiment)
In the third embodiment, after a basic bus cycle is started according to a schedule once allocated, a bus allocation schedule in the basic bus cycle is changed in accordance with the status of a bus request from each IP. In other words, the arbitration processing unit 108b dynamically changes the bus assignment within each basic bus cycle.
[0033]
For example, with respect to the basic bus cycle t2 shown in FIG. 4, bus occupation times are allocated in the order of IP104, IP103, IP102, and IP101, and after the basic bus cycle t2 is started, the IP 102 itself It is assumed that no bus request signal has been issued to the arbiter 108 by a predetermined time before the start of bus occupation. In this case, as shown in FIG. 4, the arbitration processing unit 108b eliminates the allocation time of the IP 102 in the basic bus cycle t2 and shortens the length of the basic bus cycle t2.
[0034]
Further, for example, with respect to the basic bus cycle t2 shown in FIG. 5, bus occupation times are allocated in the order of IP104, IP103, IP102, IP101, and IP102, and after the basic bus cycle t2 is started, in the basic bus cycle t2, It is assumed that the IP 102 has not issued a bus request signal by a predetermined time before the start of the second bus occupation. In this case, as shown in FIG. 5, the arbitration processing unit 108b eliminates the second allocation time of the IP 102 in the basic bus cycle t2 and shortens the length of the basic bus cycle t2.
[0035]
By performing the arbitration by the arbitration processing unit 108b in this way, the bus arbitration can be dynamically and appropriately performed according to the bus usage status. As a result, the bus cycle can be speeded up as a whole system.
[0036]
In the above description, the basic bus cycle is shortened by eliminating the time for allocating to the IP for which no bus request was issued by the predetermined time. However, the basic bus cycle is not shortened. The allocation time may be allocated to another IP.
[0037]
As a method of allocating buses in advance for each basic bus cycle, an allocation method using past statistics may be used as described in the first or second embodiment, but is not limited to this. An assignment method can be used.
[0038]
(Fourth embodiment)
In the fourth embodiment, after the basic bus cycle is started according to the once assigned schedule, the priority of each IP is determined according to the status of the bus request signal from each IP, and the priority is determined according to the priority. Change the bus allocation schedule in the basic bus cycle. That is, the fourth embodiment is also a method in which the arbitration processing unit 108b dynamically changes the bus assignment within each basic bus cycle.
[0039]
Here, for example, it is assumed that a bus occupation time is assigned in the order of IP104, IP103, IP102, and IP101 for a certain basic bus cycle (t2). As shown in FIG. 6A, for example, when a bus request signal is output from the IP 102 a plurality of times per unit time during the bus transfer of the IP 104, the arbitration processing unit 108b gives the IP 102 a higher priority. The allocation is changed so that the next bus occupation time (the time allocated to the IP 103 here) is set as the IP 102 occupation time.
[0040]
That is, each IP indicates the priority of the bus request according to a predetermined condition (in this example, the number of bus request signals output per unit time) when making a bus request. Then, the arbitration processing unit 108b determines the priority of the bus request from each IP by comparing the bus request signal from each IP with the above-mentioned predetermined condition. The above-described condition may be set so that a plurality of priorities can be expressed, and for example, the higher the number of bus request signals per unit time, the higher the priority.
[0041]
As a method of allocating a bus in advance for each basic bus cycle, an allocation method using past statistics may be used as described in the first or second embodiment, but is not limited to this. An assignment method can be used.
[0042]
Here, in addition to the example shown in FIG. 6A, an example of a method for preferentially processing a bus request determined to have high priority is shown in FIGS. 6B and 6C. Shown in
[0043]
In the example shown in FIG. 6B, it is assumed that the bus occupation time is assigned to the basic bus cycle t2 in the order of IP104, IP103, IP102, and IP101. For example, when a bus request signal is output from the IP 102 a plurality of times per unit time during the bus transfer of the IP 104, the arbitration processing unit 108b assigns a high priority to the IP 102 to execute the bus transfer. The allocation is changed so that the occupation time of the IP 102 is inserted before the next bus occupation time (the time allocated to the IP 103 in this case). Accordingly, the entire length of the basic bus cycle t2 is extended.
[0044]
In the example shown in FIG. 6C, similarly, it is assumed that the bus occupation times are allocated in the order of IP104, IP103, IP102, and IP101 with respect to the basic bus cycle t2. For example, when a bus request signal is output from the IP 102 a plurality of times per unit time during the bus transfer of the IP 104, the arbitration processing unit 108b assigns a high priority to the IP 102 to execute the bus transfer. The bus assignment is changed so that the next bus occupation time (the time assigned to the IP 103 here) and the bus occupation time originally assigned to the IP 102 are interchanged.
[0045]
As described above, in each basic bus cycle, the arbitration processing unit 108b dynamically changes the bus assignment in consideration of the priority of the bus request from each module, and thereby dynamically changes the bus allocation according to the bus usage status. And bus arbitration can be performed appropriately.
[0046]
(Fifth embodiment)
In the fifth embodiment, after the basic bus cycle starts according to the once assigned schedule, the priority of each IP is determined according to the status of the bus request signal from each IP, and the next priority is determined according to this priority. Is determined (changed if already determined) in the basic bus cycle.
[0047]
Here, for example, it is assumed that a bus occupation time is assigned in the order of IP104, IP103, IP102, and IP101 for a certain basic bus cycle (t3). Then, as shown in FIG. 7A, in the last part of the basic bus cycle t2 (here, when the last bus transfer of the basic bus cycle t2 is executed by the IP 101 here), a bus request is issued from the IP 102. If the signal is output a plurality of times per unit time, the arbitration processing unit 108b assigns a high priority to the IP 102, and the arbitration processing unit 108b assigns the first bus occupation time of the next basic bus cycle t3 (here, the IP occupancy time is assigned to the IP 104). Of the IP 102 is changed so that the time of the IP 102 is occupied by the IP 102.
[0048]
That is, as in the fourth embodiment, when making a bus request, each IP responds to the bus request according to a predetermined condition (in this example, the number of bus request signals output per unit time). Indicates priority. Then, the arbitration processing unit 108b determines the priority of the bus request from each IP by comparing the bus request signal from each IP with the above-mentioned predetermined condition. The above-described condition may be set so that a plurality of priorities can be expressed, and for example, the higher the number of bus request signals per unit time, the higher the priority.
[0049]
As a method of allocating a bus in advance for each basic bus cycle, an allocation method using past statistics may be used as described in the first or second embodiment, but is not limited to this. An assignment method can be used.
[0050]
Here, in addition to the example shown in FIG. 7A, an example of a method for preferentially processing a bus request determined to have a high priority is shown in FIGS. 7B and 7C. Shown in
[0051]
In the example shown in FIG. 7B, it is assumed that the bus occupation time is assigned to the basic bus cycle t3 in the order of IP104, IP103, IP102, and IP101. Then, for example, when a bus request signal is output from the IP 102 a plurality of times per unit time during the last bus transfer of the basic bus cycle t2, the arbitration processing unit 108b gives a high priority to the IP 102 to perform the bus transfer. Is executed, the occupation time of the IP 102 is inserted at the beginning of the next basic bus cycle t3. Accordingly, the entire length of the basic bus cycle t3 is extended.
[0052]
In the example shown in FIG. 7C, similarly, it is assumed that the bus occupation time is assigned to the basic bus cycle t3 in the order of IP104, IP103, IP102, and IP101. Then, for example, when a bus request signal is output from the IP 102 a plurality of times per unit time during the last bus transfer of the basic bus cycle t2, the arbitration processing unit 108b gives a high priority to the IP 102 to perform the bus transfer. In order to assign the start of the next basic bus cycle t3 to the IP 102, the occupation time assigned to the IP 104 and the occupation time assigned to the IP 102 are exchanged within the basic bus cycle t3.
[0053]
As described above, the arbitration processing unit 108b dynamically changes the bus assignment in the next basic bus cycle in consideration of the priority of the bus request from each module, so that the arbitration processing unit 108b operates according to the bus usage status. Bus arbitration can be performed appropriately and appropriately.
[0054]
(Sixth embodiment)
In the sixth embodiment, when issuing a bus request, each of the IPs includes a signal indicating a time (allowable time) that the IP can wait until the bus request is accepted, and a signal indicating a cycle necessary for transfer after the bus is occupied. To the arbiter 108. The arbitration processing unit 108b performs bus assignment based on information given by these signals.
[0055]
For example, as shown in FIG. 8, it is assumed that there are bus requests from IP101, IP102, and IP103, respectively. Further, it is assumed that the bus request signal from the IP 101 is accompanied by a signal indicating “1” as the allowable time and a signal indicating “2” as the necessary cycle. It is assumed that the bus request signal from the IP 102 is accompanied by a signal indicating “5” as the allowable time and a signal indicating “3” as the necessary cycle. It is assumed that the bus request signal from the IP 103 is accompanied by a signal indicating “4” as the allowable time and a signal indicating “1” as the necessary cycle. In this case, the arbitration processing unit 108b allocates two cycles in the next basic bus cycle, then one cycle in the IP102, then three cycles in the IP102, and then three cycles in the IP102 so that the allowable time and the required cycle are satisfied. So that
[0056]
If the transfer cannot be started within the given allowable time, the arbitration processing unit 108b discards the bus request signal. Further, when the bus request signal is discarded as described above, the bus throughput can be improved by shortening the basic bus cycle. In this case, each IP sets “0” as the allowable time for the transfer of data that must not discard the bus request, such as the data that must be transferred. The arbitration processing unit 108b performs the bus transfer for the bus request for which “0” is set as the allowable time even if the basic bus cycle is extended.
[0057]
【The invention's effect】
As described above, according to the present invention, the arbiter counts the number and timing of one or more previous bus requests from each IP, and reflects the statistical data in the number and the next basic bus cycle. Thus, for example, in an LSI or the like in which a plurality of applications simultaneously operate in various combinations, a bus arbitration device that dynamically adapts to various congestion conditions can be provided, and the bus throughput can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a semiconductor integrated circuit provided with a bus arbitration device of the present invention. FIG. 2 is an explanatory diagram of an example of bus arbitration processing by the bus arbitration device of the present invention. FIG. 4 is an explanatory diagram of an example of a bus arbitration process performed by the arbitration device. FIG. 4 is an explanatory diagram of an example of a bus arbitration process performed by the bus arbitration device of the present invention. FIG. 6 is a diagram illustrating an example of a bus arbitration process performed by the bus arbitration device according to the present invention. FIG. 7 is a diagram illustrating an example of a bus arbitration process performed by the bus arbitration device according to the present invention. Explanatory drawing of an example of processing [Explanation of reference numerals]
101-104 IP (master side)
105,106 IP (slave side)
107 bus 108 bus arbitration device 108a storage unit 108b arbitration processing unit

Claims (17)

In a bus arbitration device which receives a bus request from a plurality of modules connected to a bus and time-divides a basic bus cycle and occupies each module,
A bus request status storage unit for acquiring and storing information on a bus request status of each module in each basic bus cycle;
The ratio of the bus occupation period of each module in each basic bus cycle is obtained from at least one previous basic bus cycle including the basic bus cycle immediately before the basic bus cycle and stored in the bus request status storage unit. A bus arbitration device, comprising: an arbitration processing unit for determining based on the information. The bus arbitrating device according to claim 1, wherein the information on the bus request status is the number of bus requests of each module in each basic bus cycle. 2. The bus arbitrating device according to claim 1, wherein the information on the bus request status is the number of bus requests of each module in each basic bus cycle and the timing of each of the bus requests. The arbitration processing unit monitors a bus request from each module in each basic bus cycle, and if the module does not issue a bus request within the occupation period assigned to each module, cancels the bus assignment to the module. The bus arbitration device according to any one of claims 1 to 3. The bus arbitration device according to claim 4, wherein when the arbitration processing unit cancels the bus assignment to any module in each basic bus cycle, the arbitration processing unit shortens the length of the basic bus cycle. In a bus arbitration device which receives a bus request from a plurality of modules connected to a bus and time-divides a basic bus cycle and occupies each module,
A bus request status storage unit that acquires information about the bus request status of each module in each basic bus cycle and at least temporarily stores the information;
By comparing the information stored in the bus request status storage unit with a predetermined condition, the priority of the bus request from each module is determined, and the priority of the module determined to be relatively higher is determined. A bus arbitration device comprising an arbitration processing unit that changes a bus assignment in the basic bus cycle or the next basic bus cycle so that a bus request is processed with priority. The arbitration processing unit, in each basic bus cycle, changes the occupation period assigned to the module determined to be relatively low priority to the occupation period of the module determined to be relatively high priority, The bus arbitration device according to claim 6. The arbitration processing unit inserts, in each basic bus cycle, an occupation period of a module determined to be relatively high in priority before an occupation period assigned to a module determined to be relatively low in priority. The bus arbitration device according to claim 6, wherein 9. The bus arbitration device according to claim 8, wherein when the arbitration processing unit inserts an occupation period of any module in each basic bus cycle, the arbitration processing unit extends the length of the basic bus cycle. In each basic bus cycle, the arbitration processing unit assigns the order of the occupation periods assigned to the modules determined to be relatively high in priority to the order of the occupation periods assigned to the modules determined to be relatively low in the priority. 7. The bus arbitration device according to claim 6, wherein the bus arbitration device is replaced so as to be earlier in time series. The arbitration processing unit allocates, at the beginning of the next basic bus cycle, an occupation period to be assigned to a module determined to be relatively low in priority, and an occupation period of a module determined to be relatively high in priority. 7. The bus arbitration device according to claim 6, wherein the bus arbitration device is changed to: The arbitration processing unit, at the beginning of the next basic bus cycle, before the occupation period to be assigned to the module determined to be relatively low in priority, the module determined to be relatively high in priority. 7. The bus arbitration device according to claim 6, wherein an occupancy period is inserted. 13. The bus arbitration according to claim 12, wherein when the arbitration processing unit inserts an occupation period of any module at the beginning of the next basic bus cycle, the arbitration processing unit extends the length of the basic bus cycle into which the occupation period is inserted. apparatus. The arbitration processing unit, in the next basic bus cycle, swaps the occupation period of each module within the basic bus cycle so that the occupation period of the module determined to be relatively high in priority becomes first. Item 7. A bus arbitration device according to item 6. In a bus arbitration device which receives a bus request from a plurality of modules connected to a bus and time-divides a basic bus cycle and occupies each module,
From each module, data on the allowable time from issuing a bus request to acquiring the bus and the desired bus use time is obtained, and the ratio of the bus occupation time of each module in the next basic bus cycle is obtained using the data. Arbitration processing unit that determines
The bus arbitration device, wherein the arbitration processing unit discards a bus request and shortens a basic bus cycle when transfer cannot be started before the permissible time has elapsed. Each module, when issuing a bus request, sends discardability data indicating whether the bus request can be discarded to the arbitration processing unit,
16. The bus arbitration according to claim 15, wherein, if the discardability data indicates that discarding is not possible, the bus arbitration unit does not discard the bus request and extends a basic bus cycle to allocate a bus to the bus request. apparatus. A semiconductor integrated circuit comprising the bus arbitration device according to claim 1.

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