JP2004193727A - Signal processing method and signal processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing method and a signal processing circuit capable of encoding with a low decoding error rate and decoding even when random errors increase in reproducted signals. <P>SOLUTION: An encoding means includes: a symbol error correction encoder 10; and a convolution encoder 20 for attaching at least two kinds of convolution codes with different block lengths to information, and a decoding means includes: a convolution decoder 120 for decoding the convolution code from the reproducted signals; and a symbol error correction decoder 110 for detecting/correcting an error to an output result of the convolution decoder 120 in units of symbols. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technique for encoding and outputting data and decoding an input signal, and more particularly to a signal processing method and circuit for encoding data to be recorded on a recording medium and decoding a signal reproduced from the recording medium. About.
[0002]
[Prior art]
There is an increasing demand for higher recording densities for recording / reproducing devices such as magnetic disk devices (hereinafter referred to as HDDs), and the signal processing technology of the recording / reproducing system supporting this has been responding to the higher recording densities.
[0003]
FIG. 2 shows an example of a data recording / reproducing processing circuit in a conventional HDD. In FIG. 2, on the recording side, the recording data input to the input terminal 1 is subjected to error correction encoding by a symbol error correction encoder 10. A Reed-Solomon code (hereinafter referred to as an RS code) is often used as the error correction code. Further, a parity bit is added by the parity encoder 21 (it may be omitted). This signal is added with a synchronization signal or the like by the recording processing circuit 30 and is recorded as information on the recording medium 60 via the recording amplifier 40 and the recording head 50.
[0004]
On the reproduction side, a signal read from the recording medium 60 by the reproduction head 150 is amplified by the reproduction amplifier 140, the reproduction signal is detected by the reproduction processing circuit 130, and input to the parity decoder 121. The parity decoder 121 corrects a random error using the reliability information and the parity, and the symbol error correction decoder 110 corrects a code error such as a burst error due to a defect generated during recording and reproduction. Output to
[0005]
In a magnetic recording channel, the frequency response can be approximated by a differentiator and a low-pass filter connected in series. Assuming that D is a one-time delay operator, the magnetic recording channel is such that the intersymbol interference is such that the intersymbol interference has a partial impulse response of (1-D) (1 + D) ⁿ (n = 1, 2, 3,. Modeled as a response channel.
[0006]
For such a channel, the reproduction processing circuit 130 uses a Viterbi decoder. A Viterbi decoder is used to perform maximum likelihood estimation of a transmission sequence in a band-limited channel having intersymbol interference. That is, a code sequence that minimizes a distance metric (distance function) related to the received signal sequence, such as the sum of square errors of the received signal sequence, is selected from the possible code sequences.
[0007]
Non-Patent Document 1 proposes a method in which a parity code is added to recording data at a fine cycle in order to correct a random error of a reproduction signal, and the parity code and reliability information of the reproduction signal are used during reproduction. . The error correction method using a parity code cannot correct all the random errors that increase with an increase in the data recording amount or the increase in the data transfer rate, so that sufficient performance cannot be ensured. Was.
[0008]
As a theoretical limit of code performance, a Shannon limit given by the so-called Shannon channel coding theorem is known. As an encoding method showing performance close to the Shannon limit, for example, an encoding / decoding method using a parallel concatenated convolutional code called turbo encoding / decoding described in Patent Document 1 is known. I have.
[0009]
The encoding using the parallel concatenated convolutional code is performed by a device configured by connecting two convolutional encoders and an interleaver in parallel. The decoding of the parallel concatenated convolutional code is performed by a device including two decoding circuits that output a soft-output, information is exchanged between the two decoding circuits, and a final decoding result is output. Is obtained. An encoding method using a cascade convolutional code instead of a parallel concatenation is also known.
[0010]
Patent Document 2 proposes a method of performing error correction by combining the cascade convolutional code and the RS code. FIG. 9 shows a block diagram of a decoding device that realizes this method. Although an encoding circuit is not shown, a cascade convolutional coded modulation scheme is adopted as inner code for data on which RS encoding has been performed as outer code.
[0011]
The received signal is first decoded by the cascade concatenated decoder 91 using a cascade concatenated modulation scheme. The decoding signal is restored by the convolution deinterleaver 92 to restore the order of the input data, and the RS decoder 95 decodes the RS code. The decoding state is output from the cascade decoder 91 to the determination unit 93 that determines the degree of error included in the decoded data, and it is determined whether or not erasure correction is to be performed according to a predetermined criterion. Output to 94. The erasure flag adding unit 94 outputs the erasure flag to the RS decoder 95 based on the above determination, and determines whether to perform normal error correction or erasure correction depending on the presence or absence of the erasure flag.
[0012]
[Non-patent document 1]
Conway, A new target response with parity coding for high density magnetic recording channels. (1998) IEEE Trans Magn, 34 (4).
pp2382-2386.
[Patent Document 1]
U.S. Pat. No. 5,446,747 (columns 7-10, FIGS. 1-4)
[Patent Document 2]
JP-A-2001-285080 (pages 9-11, FIG. 6-9)
[0013]
[Problems to be solved by the invention]
In the erasure correction method, the reliability of the erasure flag is very important, and when the reliability is deteriorated, sufficient performance cannot be obtained.In the simple cascade decoding method, the total performance is improved. There was a problem that it could not be achieved.
[0014]
An object of the present invention is to provide a signal processing method and a signal processing circuit that enable encoding and decoding with a low decoding error rate even when the information density increases.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, in the signal processing circuit of the present invention, the encoding means includes a symbol error correction encoder for adding a code for detecting and correcting an error in symbol units to data to be recorded, A convolutional encoder for adding at least two types of convolutional codes having different block lengths, wherein the decoding means decodes the convolutional code from the reproduced signal, and outputs a symbol to the output result of the convolutional decoder. A symbol error correction decoder for detecting and correcting errors in units.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a block configuration of a magnetic recording / reproducing device such as a magnetic disk device. In FIG. 1, on the recording side, recording data input to an input terminal 1 is subjected to burst error correction encoding by a symbol error correction encoder 10. For example, an RS code is used as the error correction code. The RS code has a capability of performing error correction with a small number of redundant bytes using a byte error correction code.
[0017]
The output of the symbol error correction encoder 10 is subjected to random error correction encoding in bit units by a convolutional encoder 20. Next, in the recording processing circuit 30, a synchronization signal or the like is added, and is input to the recording head 50 via the recording amplifier 40, and is recorded as information on the recording medium 60.
[0018]
On the reproduction side, a signal read from the recording medium 60 by the reproduction head 150 is amplified by the reproduction amplifier 140, and the reproduction processing circuit 130 detects a synchronization signal. The convolutional decoder 120 corrects a random error in the reproduced signal. Next, the symbol error correction decoder 110 corrects a burst error generated at the time of recording and reproduction, and outputs reproduced data to the output terminal 2.
[0019]
FIG. 3 shows the relationship between the data of the error correction code and the parity in this embodiment. For input data, check data (RS parity) of a symbol error correction code (for example, RS code) is calculated and added to, for example, the last part of the data. The position to be added is not limited to the last part.
[0020]
Here, assuming that the number of input data is K (symbol) and the number of parity of the added RS code is M (symbol), the maximum correctable symbol number is M / 2 symbols. Hereinafter, an example in which the maximum number of correctable symbols (M / 2) is 25 symbols and one symbol is 10 bits (the maximum number of correctable bits: 250 bits) will be described. is not.
[0021]
FIG. 4 shows the details of the data and parity structures shown in FIG. Here, for example, the data is divided into units of 245 bits, and a parity P1 of a first convolutional code is calculated and added to the divided data. Note that the parity is not added with all bits, but is partially thinned out (PUNCTURE: thinning out parity bits) and added at a rate of 16 bits to 245 bits.
[0022]
Further, for these encoded data blocks, the parity of the second bit error correction convolutional code is calculated in units of a plurality of blocks (four blocks in FIG. 4), and 36 bits after thinning out the parity are calculated. (Including the end bit of 4 bits).
[0023]
FIG. 5 is a diagram showing a configuration of the convolutional encoder 20. The input data of the encoder 20 is input to the interleaver 1 (22) and the MUX & PUNC circuit 26. The interleaver 1 (22) changes the order of the input data to the set order. This interleaver 1 (22) may be an interleaver having a fixed block structure or a random interleaver for changing data in a random order.
[0024]
The output of the interleaver 1 (22) is input to the first convolutional encoder RSC1 (24) and the interleaver 2 (23). The interleaver 2 (23) performs interleaving different from that of the interleaver 1 (22) as described later. Further, the output of the interleaver 2 (23) is output to the second convolutional encoder RSC2 (25). The outputs of the two convolutional encoders RSC1 (24) and RSC2 (25) are output to the MUX & PUNC circuit 26, and the data and the parity P1 and P2 are switched and output in a data configuration as shown in FIGS. You.
[0025]
FIG. 6 shows an example of the first convolutional encoder RSC1 (24). For example, the input data is encoded using a recursive systematic convolutional code (RSC: Recursive systematic code). As an example, the third-order generator polynomial (1 + D + D ³ ) / (1 + D ² + D ³ ) can be realized by combining two exclusive OR circuits (EXOR circuits) 27 and three delay circuits 28 indicated by D. . The configuration of the second convolutional encoder RSC2 (25) is the same as that of the first convolutional encoder RSC1 (24).
[0026]
FIG. 8 shows the data structure of the interleaver. Here, as an example, an example is shown in which a block interleaver is applied as interleaver 2 (23). The output of the interleaver 1 (22) is processed by the first convolutional encoder RSC1 (24), and the 245-bit data is represented by a matrix of 7 rows and 35 columns. The second and subsequent rows are sequentially shifted left by 5 bits. This matrix is superimposed on four rows to form a matrix of 28 rows and 35 columns, and outputs this data to the second convolutional encoder RSC2 (25).
[0027]
The following paper has been published on the construction of interleavers. Ayumu Matsumoto, ・ Turbo code interleaver construction using Latin square / rectangular structure of random sequence, ・ Transactions of the Institute of Electronics, Information and Communication Engineers (A), June, 2002, vol. J85-A, no. 6, pp. 691-703,.
In a set of two tertiary RSC encoders used in this embodiment, data having a relationship of 1 + D ^7k (k = 1, 2,...) ^{Forms a} termination sequence. As for the parity operation of the first convolutional coder RSC1 (24) and the second convolutional coder RSC2 (25), it is necessary to avoid a combination that becomes the same again after interleaving. For this reason, by writing in the row direction and reading out in the column direction, of the combinations of 2 bits in which 1 + D ^7k (k = 1, 2,...) In the row direction, up to k = 5, It can be seen that a sufficient distance can be obtained in the column direction. Also, for k = 6 or more, due to the above-mentioned 5-bit shift relationship, combinations are also sufficiently separated in the column direction.
[0028]
On the other hand, when the data is read in the column direction, the combinations that result in 1 + D ^7k (k = 1, 2,...) ^Are separated into different convolutional code blocks, so that the distances are also sufficiently large. become.
[0029]
By the way, in the first convolutional encoder RSC1 (24), since the parity is sequentially added from the first half of the input sequence, the parity density for the second half of the sequence is low. In this case, the code word distance of the latter half bit becomes short, which leads to a decrease in performance. Therefore, in the second convolutional encoder RSC2 (25), reading is performed from the rear side of the data structure shown in FIG. 8, as opposed to the first convolutional encoder RSC1 (24). This increases the parity density in the latter half of the sequence in the second convolutional encoder RSC2 (25), so that the parity of the first and second convolutional encoders RSC1 and RSC2 can be equalized.
[0030]
In the decoding method according to the present embodiment, the BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm and the BP (Belief Propagation) algorithm are repeatedly executed. The error probability of each bit obtained by the BP algorithm is fed back to _pt (m, m '). It performs MAP (Maximum A Posterioriability) decoding and SOVA (Soft Out put Viterbi Algorithm) decoding based on the so-called BCJR algorithm.
[0031]
Next, an example of the configuration of the convolutional decoder 120 in FIG. 1 is shown in FIG. 7, and the operation will be described. The output of the reproduction processing circuit 130 is input to the convolutional decoder 120, the posterior probability of the channel output is calculated by a CHAPP (channel output posterior probability calculator) 122, and output to the interleaver 1 (123). Further, the output of the interleaver 1 (123) is output to the DEC1APP (first convolutional code posterior probability calculator) 125 and the interleaver 2 (128). In DEC1APP 125, decoding of the first convolutional code is performed, and the result is output to interleaver 2 (127). Outputs of the two interleavers 2 (127, 128) are input to a DEC2APP (second convolutional code posterior probability calculator) 129, where decoding of the second convolutional code is performed.
[0032]
Further, the output of DEC1APP 125 is returned to CHAPP 122 via deinterleaver 1 (124), and iterative decoding is performed a required number of times. Similarly, the output of DEC2APP 129 is returned to DEC1APP 125 via deinterleaver 2 (126), where iterative decoding is performed.
[0033]
The number of repetitions may be determined in advance, or reliability information or the like may be calculated, and the operation may be stopped when the number exceeds a set value. The result finally obtained is hard-decided and output to the symbol error correction decoder 110 as an output from the convolutional decoder 120.
[0034]
Returning to FIG. 1, the symbol error correction decoder 110 corrects a symbol error. At this time, based on the final reliability information output from the convolutional decoder 120, it is determined whether or not each block encoded in units of 245 bits cannot be corrected. If the blocks cannot be corrected, an erasure flag is output. However, it is also possible to perform erasure correction in symbol units using this.
[0035]
It goes without saying that the present invention based on the above-described embodiments can be appropriately changed without departing from the gist of the present invention. For example, a similar effect can be obtained even if the symbol error correction code is an algebraic geometric code which is an extension of the RS code.
[0036]
【The invention's effect】
As described above, according to the present invention, there is provided a signal processing method and a signal processing circuit capable of securing sufficient performance even with an increase in random errors accompanying an increase in information density and an increase in transfer rate. can do.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a magnetic recording / reproducing apparatus in which a signal processing circuit according to an embodiment of the present invention is mounted.
FIG. 2 is a configuration diagram of a magnetic recording / reproducing apparatus according to the related art.
FIG. 3 is a diagram illustrating a data configuration according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating details of a data configuration according to an embodiment of the present invention.
FIG. 5 is a configuration diagram of a convolutional encoder according to one embodiment of the present invention.
FIG. 6 is a configuration diagram of a first convolutional encoder RSC1 according to one embodiment of the present invention;
FIG. 7 is a configuration diagram of a convolutional decoder according to one embodiment of the present invention.
FIG. 8 is a diagram illustrating a data configuration and interleaving according to an embodiment of the present invention.
FIG. 9 is a configuration diagram of a decoder of a conventional magnetic recording / reproducing apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Symbol error correction encoder, 20 ... Convolution encoder, 22, 23 ... Interleaver, 24, 25 ... Convolution encoder RSC, 26 ... MUX & PUNC circuit, 27 ... Exclusive OR circuit, 28 ... Delay circuit, 30 ... Recording processing circuit, 40 ... Recording amplifier, 50 ... Recording head, 60 ... Recording medium, 110 ... Symbol error correction decoder, 120 ... Convolution decoder, 122 ... CHAPP (channel output posterior probability calculator), 123,127, 128 interleaver, 124, 126 deinterleaver, 125, 129 DECAPP (convolutional code posterior probability calculator)
130: reproduction processing circuit, 140: reproduction amplifier, 150: reproduction head.

Claims (10)

Error detection / correction codes are added to information in symbol units, and at least two types of convolution codes are added and output. At least two types of convolution codes are decoded from an input signal, and error detection / correction is performed in symbol units. A signal processing method characterized by performing. An error detection / correction code is added to the recording data in symbol units, a first convolutional code is added in units of the divided data, and a second convolutional code is added in units of a plurality of the divided data. A signal processing method comprising: adding and outputting a decoded signal; decoding a first convolutional code with respect to a reproduced signal; subsequently decoding a second convolutional code; and performing symbol error detection and correction. 3. The signal processing method according to claim 1, wherein the error detection / correction code added in symbol units is a Reed-Solomon code or an algebraic geometric code. 4. The signal processing method according to claim 1, wherein the two types of convolutional codes or the first and second convolutional codes are recursive systematic convolutional codes. 5. The decoding method according to any one of claims 1 to 4, wherein as a result of decoding the two types of convolutional codes or the first and second convolutional codes, when error correction is impossible, at least erasure correction is performed in the symbol error correction. The signal processing method according to claim 1. Encoding means comprising: a symbol error correction encoder for adding an error detection / correction code to information in a symbol unit; and a convolutional encoder for adding at least two types of convolutional codes to an output of the symbol error correction encoder. And a decoding means having a convolutional decoder for decoding at least two types of convolutional codes from an input signal, and a symbol error correction decoder for performing error detection / correction on a symbol basis at an output of the convolutional decoder. A signal processing circuit. A symbol error correction encoder for adding an error detection / correction code to recording data in symbol units, and a first convolution for dividing an output of the symbol error correction encoder and adding a first convolution code in divided units Encoding means having an encoder; a second convolutional encoder for adding a second convolutional code in units of a plurality of outputs of the first convolutional encoder; A first convolutional code posterior probability calculator that decodes a convolutional code, a second convolutional code posterior probability calculator that decodes a second convolutional code with respect to the output of the first convolutional code posterior probability calculator, And a symbol error correction decoder for performing a symbol error correction on an output of the second convolutional code posterior probability calculator. 8. The signal processing circuit according to claim 6, wherein the error detection / correction code added by the symbol error correction encoder is a Reed-Solomon code or an algebraic geometric code. The signal according to any one of claims 6 to 8, wherein the convolutional code added by the convolutional encoder or the first and second convolutional encoders is a recursive systematic convolutional code. Processing circuit. As a result of decoding by the convolutional decoder or the first and second convolutional code posterior probability calculators, when error correction is impossible, at least erasure correction is performed in the symbol error correction decoder. The signal processing circuit according to claim 6.

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