JP2004185640A5 - - Google Patents
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- JP2004185640A5 JP2004185640A5 JP2004020685A JP2004020685A JP2004185640A5 JP 2004185640 A5 JP2004185640 A5 JP 2004185640A5 JP 2004020685 A JP2004020685 A JP 2004020685A JP 2004020685 A JP2004020685 A JP 2004020685A JP 2004185640 A5 JP2004185640 A5 JP 2004185640A5
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- selectors
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- storage system
- access request
- memories
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Claims (7)
複数の記憶装置、及び
前記複数の記憶装置又は中央処理装置とに接続される制御装置とを有し、
前記制御装置は、前記複数の記憶装置又は前記中央処理装置と接続される複数のプロセッサセクション、前記複数のプロセッサセクションと接続される複数のセレクタ、及び、前記複数のセレクタと接続される複数のメモリとを有し、
前記複数のメモリの各々は、前記複数の記憶装置に格納されるデータが格納される第１の領域及び該記憶システムを制御するための制御情報が格納される第２の領域を有し、
前記複数のセレクタの各々は、前記複数のプロセッサセクションのいずれかから前記第２の領域に対するアクセス要求のコマンドを受信した場合には、前記コマンドを該セレクタが有するバッファに一旦格納して、前記複数のメモリのうち該当するメモリに送信することを特徴とする記憶システム。 A storage system,
A plurality of storage devices, and a control device connected to the plurality of storage devices or the central processing unit,
The control device includes a plurality of processor sections connected to the plurality of storage devices or the central processing unit, a plurality of selectors connected to the plurality of processor sections, and a plurality of memories connected to the plurality of selectors. And
Each of the plurality of memories has a first area in which data stored in the plurality of storage devices is stored and a second area in which control information for controlling the storage system is stored.
When each of the plurality of selectors receives an access request command for the second area from any of the plurality of processor sections, the plurality of selectors temporarily store the command in a buffer included in the selector, and A storage system that transmits the data to a corresponding memory.
前記複数のセレクタの各々は、前記複数のプロセッサセクションのいずれかから前記第１の領域に対するアクセス要求のコマンドを受信した場合には、前記コマンドを該セレクタが有するバッファを用いずに、前記複数のメモリのうち該当するメモリに送信することを特徴とする記憶システム。 The storage system of claim 1,
When each of the plurality of selectors receives an access request command for the first area from any one of the plurality of processor sections, the plurality of selectors do not use the buffer included in the selector, and the plurality of selectors A storage system that transmits data to a corresponding memory.
前記第１の領域及び前記第２の領域はアドレスによって区別されており、前記複数のセレクタの各々は、受信するアクセス要求に含まれるアドレスに応じて、前記複数のメモリのうち、該当するメモリの前記第１の領域または第２の領域に、受信したアクセス要求を送信することを特徴とする記憶システム。 The storage system according to claim 2,
The first area and the second area are distinguished from each other by an address, and each of the plurality of selectors has a corresponding memory among the plurality of memories according to an address included in the received access request. A storage system, wherein the received access request is transmitted to the first area or the second area.
前記複数のセレクタの各々が受信するアクセス要求には、前記第１の領域または前記第２の領域を指定する情報が含まれており、前記複数のセレクタの各々は、前記情報にしたがって、前記複数のメモリのうち、該当するメモリの前記第１の領域または前記第２の領域に、受信したアクセス要求を送信することを特徴とする記憶システム。 The storage system according to claim 2,
The access request received by each of the plurality of selectors includes information specifying the first area or the second area, and each of the plurality of selectors includes the plurality of the plurality of selectors according to the information. The received access request is transmitted to the first area or the second area of the corresponding memory among the memories.
前記複数のセレクタの各々が受信するアクセス要求には、前記第１の領域をアクセスするための第１のプロトコルに従うアクセス要求と前記第２の領域をアクセスするための第２のプロトコルに従うアクセス要求とがあり、前記複数のセレクタの各々は、前記プロトコルに応じて、前記複数のメモリのうち、該当するメモリの前記第１の領域または前記第２の領域に、受信したアクセス要求を送信することを特徴とする記憶システム。 The storage system according to claim 2,
The access request received by each of the plurality of selectors includes an access request according to a first protocol for accessing the first area and an access request according to a second protocol for accessing the second area. And each of the plurality of selectors transmits the received access request to the first area or the second area of the corresponding memory among the plurality of memories according to the protocol. A featured storage system.
前記複数のプロセッサセクションは前記複数のセレクタの全てと接続されており、前記複数のメモリは、前記複数のセレクタの全てと接続されており、前記複数のプロセッサセクション、前記複数のセレクタ及び前記複数のメモリを繋ぐ経路が独立して複数存在することを特徴とする記憶システム。 6. The storage system according to claim 5, wherein
The plurality of processor sections are connected to all of the plurality of selectors, and the plurality of memories are connected to all of the plurality of selectors, the plurality of processor sections, the plurality of selectors, and the plurality of the plurality of selectors. A storage system characterized in that a plurality of paths that connect memories exist independently.
前記複数のセレクタの各々は、前記複数のメモリの各々が有する前記第１の領域へ前記アクセス要求を送信する場合と前記第２の領域へ前記アクセス要求を送信する場合で異なる経路を使用することを特徴とする記憶システム。
The storage system according to claim 6, wherein
Each of the plurality of selectors uses a different path when transmitting the access request to the first area of each of the plurality of memories and when transmitting the access request to the second area. A storage system characterized by
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004020685A JP4173110B2 (en) | 2004-01-29 | 2004-01-29 | Storage system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004020685A JP4173110B2 (en) | 2004-01-29 | 2004-01-29 | Storage system |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13271298A Division JP3657428B2 (en) | 1998-04-27 | 1998-04-27 | Storage controller |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005128856A Division JP4179303B2 (en) | 2005-04-27 | 2005-04-27 | Storage system |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2004185640A JP2004185640A (en) | 2004-07-02 |
| JP2004185640A5 true JP2004185640A5 (en) | 2005-09-02 |
| JP4173110B2 JP4173110B2 (en) | 2008-10-29 |
Family
ID=32768136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004020685A Expired - Lifetime JP4173110B2 (en) | 2004-01-29 | 2004-01-29 | Storage system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4173110B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4471947B2 (en) * | 2005-04-28 | 2010-06-02 | Ｎｅｃエレクトロニクス株式会社 | Data processing apparatus and data processing method |
| JP4997784B2 (en) * | 2006-02-16 | 2012-08-08 | 日本電気株式会社 | Data storage system, data storage method, and data storage program |
| WO2014009994A1 (en) | 2012-07-10 | 2014-01-16 | Hitachi, Ltd. | Disk subsystem and method for controlling memory access |
-
2004
- 2004-01-29 JP JP2004020685A patent/JP4173110B2/en not_active Expired - Lifetime
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