JP2004178671A - Readout control circuit and fifo control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a readout control circuit and a FIFO(First-in First-out) control circuit which can shorten a period of time from the start of write-in to the start of reading. <P>SOLUTION: The readout control circuit 22a is provided with an enable signal generating circuit 21a which generates an enable signal ES by detecting the start of write-in based on a write-in clock CLK<SB>1</SB>at the time of write-in operation and a reset signal generating circuit 6 which outputs a reset signal RS to the enable signal generating circuit 21a by detecting the completion of write-in. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a FIFO control circuit, and more particularly, to a read control circuit that controls data reading.
[0002]
[Prior art]
A first-in first-out (FIFO) memory 1 as shown in FIG. 7 is widely used for a buffer memory, a data delay circuit, and the like of a communication control device. The FIFO memory 1 is a memory from which data can be read in the order of writing. The FIFO memory 1 includes a plurality of registers connected in parallel. The write counter 112 counts the write clock CLK ₁ output from the write clock terminal 11 and supplies a write address to the FIFO memory 1. On the other hand, the read counter 113 counts the read clock CLK ₂ output from the read clock terminal 12 and supplies a read address to the FIFO memory 1. As described above, the write counter 112 sequentially selects the registers in the FIFO memory 1 and writes the data. Thereafter, the read counter 113 sequentially selects the register in which the data is stored and reads the data. As a result, a first-in first-out operation is performed. The address determination circuit 114 determines the write address and the read address, and controls the read start and end timings of the read counter 113.
[0003]
[Patent Document]
JP-A-7-65568
[Problems to be solved by the invention]
The address determination circuit 114 illustrated in FIG. 7 requires a certain determination time when determining the write address and the read address. Therefore, there is a problem that the reading cannot be started immediately after the writing is started. Further, the FIFO memory 1 needs to have a storage capacity necessary for the determination time of the address determination circuit 114.
[0005]
In view of the above problems, an object of the present invention is to provide a read control circuit and a FIFO control circuit that can reduce the time from the start of writing to the start of reading.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a first feature of the present invention is that (a) a reset signal generation circuit that detects the end of writing based on a write address and a read address and outputs a reset signal; A read control circuit including an enable signal generation circuit that outputs an enable signal based on the first rising edge of a write clock that is driven only at the time and stops outputting the enable signal based on a reset signal.
[0007]
According to the read control circuit according to the first aspect, the enable signal generation circuit generates the enable signal from the write clock without using the write address. As a result, the enable signal can be generated without determining the write address and the read address. Therefore, it becomes possible to start reading immediately from the start of writing. Further, when the write clock and the read clock have the same frequency, the number of registers in the FIFO memory can be reduced. Even if a setup / hold violation occurs, an enable signal can be generated stably.
[0008]
A second feature of the present invention is that (a) a write counter that counts a write clock driven only at the time of a write operation and supplies a write address to a FIFO memory; (b) counts a read clock and stores a read address in a FIFO memory. A reset signal generating circuit for detecting the end of writing based on the write address and the read address and outputting a reset signal; and (d) enabling the read counter based on the first rise of the write clock. A gist is a FIFO control circuit including an enable signal generation circuit that outputs a signal and stops outputting an enable signal based on a reset signal.
[0009]
According to the FIFO control circuit according to the second feature, not only the start of reading but also the start of reading can be executed immediately, and the stop of reading can be executed stably.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, first to third embodiments of the present invention will be described with reference to the drawings. In the drawings of the first to third embodiments, the same or similar parts are denoted by the same or similar reference numerals.
[0011]
(First Embodiment)
FIFO control circuit 23a according to the first embodiment of the present invention, as shown in FIG. 1 supplies a read address RAD ₁ to FIFO memory 1 to the write counter 2, the FIFO memory 1 supplies a write address WAD ₁ The read counter 3 includes a read control circuit 22a for controlling the operation timing of the read counter 3. The write counter 2 has a clock input terminal CK electrically connected to the write clock terminal 11. The read counter 3 has a clock input terminal CK connected to the read clock terminal 12. The read control circuit 22a includes an enable signal generation circuit 21a and a reset signal generation circuit 6. Reset signal generating circuit 6 detects the end of the writing based on the write address WAD ₁ and the read address RAD _1, and outputs a reset signal RS to the enable signal generation circuit 21a. Enable signal generating circuit 21a, based on the first rising of the write clock CLK ₁ which is driven only during a write operation, and outputs to the counter 3 reads the enable signal ES, and stops the output of the enable signal ES based on the reset signal RS .
[0012]
As shown in FIG. 1, the enable signal generation circuit 21a includes a clock input terminal CK connected to the write clock terminal 11, a data input terminal D connected to the high power supply VDD, and a reset terminal connected to the reset signal generation circuit 6. A first latch circuit 4a having a CLR is provided. As the first latch circuit 4a, for example, a D flip-flop can be used.
[0013]
As shown in FIG. 2, the reset signal generation circuit 6 includes a second latch circuit 31 connected to the write counter 2 shown in FIG. 1, a third latch circuit 32 connected to the second latch circuit 31, 1 includes a fourth latch circuit 33 connected to the read counter 3, a third latch circuit 32, and an address comparison circuit 34 connected to the fourth latch circuit 33. Second latch circuit 31, a third latch circuit 32, and the fourth latch circuit 33 has a clock input terminal CK for inputting a read clock CLK ₂ respectively. Address comparison circuit 34, if the address value and the address value of the read address RAD ₂ of the write address WAD ₃ and match, outputs a reset signal RS. The address comparison circuit 34 is connected to the reset terminal CLR of the first latch circuit 4a shown in FIG.
[0014]
Next, the operation of the FIFO control circuit 23a according to the first embodiment will be described with reference to FIGS.
[0015]
(A) During a write operation, the write clock CLK ₁ shown in FIG. The write clock CLK ₁ input via the write clock terminal 11 is transmitted to the first latch circuit 4a and the write counter 2 shown in FIG. Write counter 2 counts the write clock CLK _1, and generates a write address WAD _1. Then, the write counter 2 outputs the write address WAD ₁ shown in FIG. 3B to the FIFO memory 1 and the reset signal generation circuit 6.
[0016]
(B) it is a write clock CLK ₁ shown in FIG. 1 (a), when it is transmitted to the first latch circuit 4a, a first latch circuit 4a is synchronized with the first rise of the write clock CLK _1, high The high level signal from the power supply VDD is latched. That is, when the first latch circuit 4a latches the high-level signal from the high potential power supply VDD at time t _1, as shown in FIG. 3 (c), the enable signal via the output terminal Q of the first latch circuit 4a ES is output. The enable signal ES output from the enable signal generation circuit 21a is input to the enable signal input terminal ENB of the read counter 3. Incidentally, in the conventional FIFO control circuit, the enable signal ES is output at time _{t 2} in FIG.
[0017]
When the enable signal ES is inputted to the (c) read counter 3, as shown in FIG. 3 (e), and counts the read clock CLK ₂ in FIG. 3 (d), it generates a read address RAD _1. The read address RAD ₁ output from the read counter 3 is supplied to the FIFO memory 1 and the reset signal generation circuit 6.
[0018]
Second latch circuit 31 shown in (D) 2, as shown in FIG. 4 (d), in synchronization with latching the leading edge of the clock CLK ₂ reads the write address WAD _1. Furthermore, a third latch circuit 32, as shown in FIG. 4 (e), in synchronization with latching the leading edge of the clock CLK ₂ reads the write address WAD ₂ of the second latch circuit 31 outputs. On the other hand, the fourth latch circuit 33, as shown in FIG. 4 (h), latches in synchronization with the rising edge of the clock CLK ₂ reads the read address RAD ₁ to read counter 3 outputs.
[0019]
In (e) wherein, when the write clock CLK ₁ shown in FIG. 4 (a) was stopped, namely, the case where write is completed. When the write clock CLK ₁ stops, WAD ₁ output from the write counter 2 is not counted up. As a result, the read address RAD ₂ illustrating the write address WAD ₃ and 4 shown in FIG. 4 (e) (h), coincide at time _{t 3.} If the read address RAD ₂ matches the write address WAD _3, the address comparison circuit 34 outputs a reset signal RS to the reset terminal CLR of the first latch circuit 4a. When the reset signal RS is output to the reset terminal CLR of the first latch circuit 4a, a first latch circuit 4a is reset, it falls to the low level enable signal ES is time t ₃ when shown in FIG. 4 (f) . When the enable signal ES falls to a low level, the read counter 3 stops counting.
[0020]
Thus, according to the first embodiment, to shorten the time from the writing start to start reading only for the period of time t ₁ ~t _2. That is, it is possible to provide the FIFO control circuit 23a that can start reading immediately after starting writing. Therefore, it is not necessary to provide the FIFO memory 1 with a storage capacity necessary for determining an address. In addition, the read operation can be stably executed.
[0021]
(Second embodiment)
The FIFO control circuit 23b according to the second embodiment of the present invention differs from FIG. 1 in that the enable signal generation circuit 21b further includes a switch circuit 5b as shown in FIG. The switch circuit 5b has one input terminal A connected to the write clock terminal 11, and the other input terminal B connected to the low power supply VSS. As the switch circuit 5b, for example, a multiplexer can be used. The first latch circuit 4b includes a clock input terminal CK connected to the output terminal Y of the switch circuit 5b, a data input terminal D connected to the high power supply VDD, a reset terminal CLR connected to the reset signal generation circuit 6, and a switch. The circuit 5b has an output terminal Q connected to the switching signal input terminal S. Other configurations are the same as those in FIG. The switch circuit 5b outputs a signal input to the input terminal A via the output terminal Y when the enable signal ES output from the first latch circuit 4b is at a low level. On the other hand, when the enable signal ES is at a high level, a signal input to the input terminal B is output via the output terminal Y.
[0022]
Next, the operation of the FIFO control circuit 23b according to the second embodiment will be described with reference to FIGS. However, for the same operation as that of the FIFO control circuit 23a according to the first embodiment, a duplicate description will be omitted.
[0023]
(B) a write clock CLK ₁ shown in FIG. 3 (a) is input to the input terminal A and a write counter 2 of the switch circuit 5b. When the write clock CLK ₁ is inputted to the input terminal A of the switch circuit 5b, write clock CLK ₁ through the output terminal Y from the switch circuit 5b is output.
[0024]
When a write clock CLK ₁ from (b) switching circuit 5b is output, the first latch circuit 4b is a high-level signal from the high power supply VDD, and synchronization with the latch and the first rising edge of the write clock CLK _1. As a result, as shown in FIG. 3C, the first latch circuit 4b outputs the enable signal ES via the output terminal Q. The enable signal ES output from the first latch circuit 4b is input to the enable signal input terminal ENB of the read counter 3 and the switching signal input terminal S of the switch circuit 5b.
[0025]
(C) When the enable signal ES is input to the switch circuit 5b, the input of the switch circuit 5b switches from the input terminal A to the input terminal B. When the input of the switch circuit 5b switches from the input terminal A to the input terminal B, the switch circuit 5b outputs a low-level signal from the lower power supply VSS via the output terminal Y. The low level signal output from the switch circuit 5b via the output terminal Y is input to the clock input terminal CK of the first latch circuit 4b.
[0026]
(D) When the low level signal is input to the clock input terminal CK of the first latch circuit 4b, the high level state of the enable signal ES is maintained. When the reset signal RS is output from the reset signal generation circuit 6, the enable signal ES falls to a low level.
[0027]
As described above, according to the second embodiment, the input of the clock input terminal CK of the first latch circuit 4b is switched by the switch circuit 5b. As a result, even if a malfunction occurs in the first latch circuit 4b, the high level state of the enable signal ES can be maintained. Therefore, the enable signal ES can be generated quickly and stably.
[0028]
(Third embodiment)
As shown in FIG. 6, the FIFO control circuit 23c according to the third embodiment of the present invention includes one input terminal A connected to the write clock terminal 11, and the other input terminal B connected to the low power supply VSS. , A clock input terminal CK connected to the read clock terminal 12, a set terminal SET connected to the output terminal Y of the switch circuit 5c, a reset terminal CLR connected to the reset signal generation circuit 6, and a switch circuit 5c. 1 in that a first latch circuit 4c having an output terminal Q connected to the switching signal input terminal S is provided. For example, a synchronous RS flip-flop can be used as the first latch circuit 4c. Other configurations are the same as those in FIG.
[0029]
Next, the operation of the FIFO control circuit 23c according to the third embodiment will be described with reference to FIGS. However, for the same operation as that of the FIFO control circuit 23a according to the first embodiment, a duplicate description will be omitted.
[0030]
(B) a write clock CLK ₁ shown in FIG. 3 (a) is input to the input terminal A and a write counter 2 of the switch circuit 5c. When write clock CLK ₁ to the input terminal A of the switch circuit 5c is input, the switch circuit 5c outputs the write clock CLK _1, a set terminal SET of the first latch circuit 4c via the output terminal Y.
[0031]
When (b) write clock CLK ₁ to the set terminal SET of the first latch circuit 4c is input, the first latch circuit 4c is an enable signal ES in synchronization with the write clock CLK ₁ and the read clock CLK _2, The signal is output to the switching signal input terminal S of the switch circuit 5c via the output terminal Q. When the enable signal ES is input to the switch circuit 5c, the input of the switch circuit 5c switches from the input terminal A to the input terminal B.
[0032]
(C) When the input of the switch circuit 5c is switched to the input terminal B, a low-level signal from the lower power supply VSS is output to the set terminal SET of the first latch circuit 4c via the output terminal Y. As a result, the first latch circuit 4c continues to output the enable signal ES until the reset signal RS is input to the reset terminal CLR.
[0033]
In this manner, according to the third embodiment, since it generates an enable signal ES with a clock CLK ₂ and the read write clock CLK _1, it is possible to generate a more accurately enable signal ES.
[0034]
(Other embodiments)
As described above, the present invention has been described with reference to the first to third embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.
[0035]
In the first and second embodiments, an example in which a D flip-flop is used as the first latch circuits 4a and 4b has been described. In the third embodiment, an example has been described in which a synchronous RS flip-flop is used as the first latch circuit 4c. However, various latch circuits such as a JK flip-flop and an RST flip-flop can be used as the first latch circuits 4a, 4b, and 4c.
[0036]
In the second and third embodiments, an example has been described in which a multiplexer is used as the switch circuits 5b and 5c. However, the switching operation can be realized by using, for example, transistors having different polarities in place of the multiplexer. Here, the transistors include a bipolar transistor, a MOS transistor, a junction field effect transistor (JFET), a Schottky barrier type field effect transistor (MESFET), an electrostatic induction transistor (SIT), and a high electron mobility transistor (HEMT). And various other transistors can be used. Alternatively, the switch operation may be realized by a logic circuit such as an AND circuit, an OR circuit, a NOT circuit, a NOR circuit, and a NAND circuit.
[0037]
Further, the FIFO control circuits 23a, 23b, and 23c according to the first to third embodiments can be integrated on the same semiconductor substrate to configure a semiconductor integrated circuit. Further, the FIFO control circuits 23a, 23b, 23c and the FIFO memory 1 according to the first to third embodiments can be integrated on the same semiconductor substrate.
[0038]
Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the matters specifying the invention described in the claims appropriate from this disclosure.
[0039]
【The invention's effect】
According to the present invention, it is possible to provide a read control circuit and a FIFO control circuit capable of reducing the time from the start of writing to the start of reading.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a FIFO control circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of a reset signal generation circuit according to the first embodiment of the present invention.
FIG. 3 is a time chart illustrating an operation of the enable signal generation circuit according to the first embodiment of the present invention.
FIG. 4 is a time chart illustrating an operation of the reset signal generation circuit according to the first embodiment of the present invention.
FIG. 5 is a circuit diagram of a FIFO control circuit according to a second embodiment of the present invention.
FIG. 6 is a circuit diagram of a FIFO control circuit according to a third embodiment of the present invention.
FIG. 7 is a circuit diagram of a conventional FIFO control circuit.
[Explanation of symbols]
1 FIFO memories 2, 112 Write counters 3, 113 Read counters 4a, 4b, 4c First latch circuits 5b, 5c Switch circuit 6 Clock stop detection circuit 11 Write clock terminal 12 Read clock terminal 21a , 21b, 21c ... enable signal generation circuits 22a, 22b, 22c ... read control circuits 23a, 23b, 23c ... FIFO control circuit 31 ... second latch circuit 32 ... third latch circuit 33 ... fourth latch circuit 34 ... Address comparison circuit 114: address determination circuit

Claims (10)

A reset signal generation circuit that detects the end of writing based on the write address and the read address, and outputs a reset signal;
Read control comprising: generating an enable signal based on a first rising edge of a write clock driven only during a write operation; and stopping output of the enable signal based on the reset signal. circuit. The enable signal generation circuit includes a first latch circuit having a clock input terminal connected to a write clock terminal, a data input terminal connected to a higher power supply, and a reset terminal connected to the reset signal generation circuit. The read control circuit according to claim 1, further comprising: The enable signal generation circuit includes:
A switch circuit having one input terminal connected to the write clock terminal and the other input terminal connected to the lower power supply;
A clock input terminal connected to an output terminal of the switch circuit, a data input terminal connected to a high-order power supply, a reset terminal connected to the reset signal generation circuit, and a switching signal input terminal of the switch circuit. The read control circuit according to claim 1, further comprising: a first latch circuit having a first output terminal and a first latch circuit. The enable signal generation circuit includes:
A switch circuit having one input terminal connected to the write clock terminal and the other input terminal connected to the lower power supply;
A clock input terminal connected to the read clock terminal, a set terminal connected to the output terminal of the switch circuit, a reset terminal connected to the reset signal generation circuit, and a switching signal input terminal of the switch circuit. The read control circuit according to claim 1, further comprising: a first latch circuit having a first output terminal and a first latch circuit. The reset signal generation circuit includes:
A second latch circuit that latches the write address in synchronization with a read clock;
A third latch circuit for latching the output of the second latch circuit in synchronization with the read clock;
A fourth latch circuit for latching the read address in synchronization with the read clock;
5. The semiconductor device according to claim 1, further comprising: an address comparison circuit configured to compare the write address output from the third latch circuit with the read address output from the fourth latch circuit. 3. The read control circuit according to 1. A write counter that counts a write clock that is driven only during a write operation and supplies a write address to the FIFO memory;
A read counter that counts a read clock and supplies a read address to the FIFO memory;
A reset signal generation circuit that detects completion of writing based on the write address and the read address, and outputs a reset signal;
A FIFO control circuit, comprising: an enable signal generation circuit that outputs an enable signal to the read counter based on a first rising of the write clock and stops outputting the enable signal based on the reset signal. The enable signal generation circuit includes a first latch circuit having a clock input terminal connected to a write clock terminal, a data input terminal connected to a higher power supply, and a reset terminal connected to the reset signal generation circuit. The FIFO control circuit according to claim 6, further comprising: The enable signal generation circuit includes:
A switch circuit having one input terminal connected to the write clock terminal and the other input terminal connected to the lower power supply;
A clock input terminal connected to an output terminal of the switch circuit, a data input terminal connected to a high-order power supply, a reset terminal connected to the reset signal generation circuit, and a switching signal input terminal of the switch circuit. 7. The FIFO control circuit according to claim 6, further comprising: a first latch circuit having an output terminal. The enable signal generation circuit includes:
A switch circuit having one input terminal connected to the write clock terminal and the other input terminal connected to the lower power supply;
A clock input terminal connected to the read clock terminal, a set terminal connected to the output terminal of the switch circuit, a reset terminal connected to the reset signal generation circuit, and a switching signal input terminal of the switch circuit. 7. The FIFO control circuit according to claim 6, further comprising: a first latch circuit having an output terminal. The reset signal generation circuit includes:
A second latch circuit having a clock input terminal connected to the read clock terminal and connected to the write counter;
A third latch circuit having a clock input terminal connected to the read clock terminal and connected to the second latch circuit;
A fourth latch circuit having a clock input terminal for inputting the read clock and connected to the read counter;
10. An address comparison circuit according to claim 7, further comprising: an address comparison circuit having one input terminal connected to said third latch circuit and the other input terminal connected to said fourth latch circuit. The FIFO control circuit according to claim 1.

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