JP2004172653A - Mobile terminal device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of disturbances or line disconnections to other mobile terminals and a base station due to misoperations of adjusting transmission timing, when line quality is deteriorated. <P>SOLUTION: A transmission clock circuit 51 of a transmission timing adjusting unit 5 applies timing adjustment to frequency divided output of a system clock (SYSCLK) according to timing control data Dt outputted from a control circuit 57, and outputs a transmission clock (TXCLK) synchronized with a reproduction clock (RXCLK). When a phase difference Do, between the reproduction clock to be outputted from a phase comparing circuit 53 and the transmission clock, varies abnormally within a reception period, the phase difference abnormality detecting circuit 56 outputs an alarm signal D3. A control circuit 57, when the alarm signal D3 is received and line quality information Dq from a line quality estimating circuit 52 indicates deterioration in line quality, since the reproduction clock is unstable the control circuit 57 stops the timing adjustment processing of the transmission clock. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a mobile terminal, and more particularly, to a transmission timing adjustment function applied to a TDMA (Time Division Multiplexing) mobile terminal.
[0002]
[Prior art]
In TDMA (time division multiplexing) communication, the timing of a transmission slot and the timing of a reception slot are determined in advance. Each mobile terminal communicates with the base station according to different transmission slot timing and reception slot timing allocated by the base station.
[0003]
By the way, if a timing shift occurs in the transmission slot, this becomes an interference wave for other mobile terminals and base stations, and in the worst case, communication is disconnected.
[0004]
In order to prevent interference with other mobile terminals and the base station or disconnection of communication due to such a shift in transmission timing, for example, on the mobile terminal side, an optimal timing based on the distance between the base station and the mobile terminal is set. Measurement is performed and automatic adjustment is performed so that the transmission timing does not shift. (For example, refer to Patent Document 1.)
[Patent Document 1]
JP-A-10-322765 (page 1-2)
[0005]
[Problems to be solved by the invention]
However, in the above-described conventional example, when the line quality is temporarily deteriorated due to fading or the like and the measurement result is disturbed, the transmission timing is automatically adjusted due to an erroneous measurement result. As a result, there is a problem that other mobile terminals and base stations are interfered with or the line is disconnected.
[0006]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a mobile terminal capable of preventing interference with another mobile terminal and a base station and disconnection of a line due to a malfunction of transmission timing adjustment when the line quality is deteriorated.
[0007]
[Means for Solving the Problems]
A mobile terminal according to the present invention includes a transmitting unit that outputs a transmission slot according to a transmission clock, a receiving unit that generates and demodulates a reproduction clock synchronized with a reception slot, and outputs a divided output of a system clock to the reproduction clock. A mobile terminal comprising: a transmission timing adjustment unit that adjusts timing so as to synchronize and outputs the transmission clock as the transmission clock, wherein the transmission timing adjustment unit monitors a phase difference between the reproduction clock and the transmission clock, and When the fluctuation width of the phase difference exceeds a predetermined value within the period, the timing adjustment processing of the transmission clock is stopped.
[0008]
Further, the transmission timing adjustment unit has means for estimating a channel quality based on an average value of a bit error rate in demodulation of the reception unit, and when the channel quality is deteriorated from a preset state, the transmission Stop the clock timing adjustment process.
[0009]
More specifically, a transmitting unit that outputs a transmission slot according to a transmission clock, a receiving unit that generates and demodulates a reproduction clock synchronized with a reception slot, and synchronizes a divided output of a system clock with the reproduction clock. A transmission timing adjustment unit that adjusts the timing and outputs the transmission clock as the transmission clock, the transmission timing adjustment unit includes a phase comparison circuit that detects a phase difference between the reproduction clock and the transmission clock, and a reception slot. A phase difference abnormality detection circuit that detects a phase difference abnormality when the fluctuation width of the phase difference exceeds a predetermined value within a period of time, and a transmission clock generation that generates the transmission clock in response to the system clock and the timing control information A circuit for generating the timing control information so that the phase difference is set to 0; When normal detection circuit detects a phase difference abnormality and a control circuit for stopping the timing adjusting process of the transmission clock generation circuit.
[0010]
Further, the transmission timing adjustment unit calculates a bit error rate based on phase information between a signal point of a received signal and a normal signal point in demodulation of the reception unit, and calculates a bit error rate over a period longer than at least a reception slot period. A line quality estimating circuit for estimating a line quality state by calculating an average value of the line quality state, even when the phase difference abnormality is not detected, when the line quality state is degraded from a preset state. Stops the transmission clock timing adjustment process.
[0011]
Further, the transmission timing adjusting unit has a phase difference average value circuit for calculating an average value of the phase difference during a reception slot period, and the control circuit does not detect the phase difference abnormality and sets the line quality state. Even if the state is better than a preset state, the timing adjustment processing of the transmission clock is stopped when the average phase difference value is within a preset lock area.
[0012]
Still further, the transmission timing adjustment unit has a phase difference distribution circuit that measures a distribution state of the phase difference within a reception slot period, and the control circuit is configured to control a distribution state of the phase difference within the reception slot period based on the distribution state of the phase difference. The presence or absence of a phase difference abnormality may be detected, and the control circuit of the transmission timing adjustment unit may not detect the phase difference abnormality and the line quality state may be better than a preset state, The timing adjustment process of the transmission clock may be stopped when the phase difference distribution state is concentrated and distributed in a preset lock area.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described with reference to the drawings.
[0014]
FIG. 1 is a block diagram showing one embodiment of the present invention, and shows a configuration example of a mobile terminal having a transmission timing adjustment function.
[0015]
The mobile terminal outputs a transmission signal (transmission slot) St according to an antenna 1, an antenna duplexer 2 for sharing transmission and reception of the antenna, and a transmission clock (TXCLK) output from a transmission timing adjustment unit 5. A transmitting unit 3, a receiving unit 4 that receives a received signal (receiving slot) Sr, generates a reproduced clock (RXCLK) synchronized with the receiving slot, and demodulates received data, and the transmission clock (TXCLK) whose timing is adjusted And a transmission timing adjustment unit 5 for outputting the same.
[0016]
Here, as shown in FIG. 1, the receiving unit 4 converts the frequency of the received signal Sr into an IF signal (intermediate frequency signal), and performs demodulation based on the recovered clock (RXCLK). (RXCLK).
[0017]
Then, the reception demodulation circuit 41 outputs the phase information Dp indicating the phase difference between the signal point of the reception data and the normal signal point, and detects the synchronization word of the reception data to indicate the reception completion of the reception slot. An interrupt signal (RXINT) is output. Further, the reproduction clock generation circuit 42 receives the system clock (SYSCLK) and the phase information Dp, and generates a reproduction clock (RXCLK) synchronized with the reception slot.
[0018]
As shown in FIG. 1, the transmission timing adjustment unit 5 generates a transmission clock (TXCLK) from the system clock (SYSCLK) and a line quality based on the phase information Dp output from the reception unit 4. , A line quality estimating circuit 52 that outputs line quality information Dq, a phase comparing circuit 53 that detects a phase difference between the transmission clock (TXCLK) and the recovered clock (RXCLK), and a position that the phase comparing circuit 53 outputs. A phase difference instantaneous value circuit 54 that latches the phase difference data Do and outputs an instantaneous value D1 of the phase difference; a phase difference average value circuit 55 that outputs an average value D2 of the phase difference based on the phase difference data Do; A phase difference abnormality detection circuit 56 which detects a phase difference abnormality based on Do and outputs a warning signal D3; a phase difference instantaneous value D1; a phase difference average value D2; Issue D3, and a control circuit (CPU) 57 for controlling the reception completion interrupt signal (RXINT) and transmit respectively receive the channel quality information Dq clock generation circuit 51.
[0019]
Here, the transmission clock (TXCLK) generated by the transmission clock generation circuit 51 is a clock signal having the same frequency and the same phase as the reproduction clock (RXCLK) generated by the reception unit 4, and forms a PLL loop to generate the transmission clock. It is generated by controlling the circuit 51.
[0020]
In general, the frequency of the system clock (SYSCLK) is higher than the frequency of the transmission clock (TXCLK), for example, 64 times the frequency of the transmission clock.
[0021]
For example, when the frequency of the system clock (SYSCLK) is 64 times the transmission clock, the transmission clock generation circuit 51 divides the system clock (SYSCLK) by 64 and outputs the divided output from the control circuit 57. By adjusting the timing according to the control information Dt, a transmission clock (TXCLK) synchronized with the reproduction clock is output.
[0022]
The phase comparison circuit 53 uses a counter that counts up the system clock (SYSCLK) when detecting the phase difference between the transmission clock (TXCLK) and the recovered clock (RXCLK).
[0023]
FIG. 2 is a diagram showing a phase difference detection operation of the phase comparison circuit 53.
[0024]
The phase comparison circuit 53 resets the counter at the rising edge of the reproduction clock (RXCLK), starts counting up the system clock (SYSCLK), and latches the count value at the rising edge of the transmission clock (TXCLK).
[0025]
The latched count value indicates the phase difference between the reproduction clock (RXCLK) and the transmission clock (TXCLK).
[0026]
For example, when the frequency of the system clock (SYSCLK) is 64 times the frequency of the transmission clock (TXCLK), the count value to be latched is any one of “0” to “63”, and this count value is the phase difference. It is output as data Do for each reception clock. Here, a case where the count value “7” is output as the phase difference data Do is shown.
[0027]
The count value indicating the phase difference is, for example, a range of “0” to “7” or a range of “56” to “63” as a lock region, a range of “8” to “31” as a delay region, and “32”. "To" 55 "are set as advance areas.
[0028]
Note that in order to improve the detection accuracy of the phase difference data, the cycle of the system clock (SYSCLK) may be made sufficiently shorter than the cycle of the reproduction clock.
[0029]
The phase difference data Do is output to a phase difference instantaneous value circuit 54, a phase difference average value circuit 55, and a phase difference abnormality detection circuit 56, respectively.
[0030]
The phase difference instantaneous value circuit 54 latches the phase difference data Do periodically output for each reception slot, and outputs the phase difference instantaneous value D1 in response to access from the control circuit 57.
[0031]
The phase difference average value circuit 55 calculates the average value of the phase difference data Do in the reception slot period, and outputs the phase difference average value D2 in response to the access from the control circuit 57. Further, the phase difference abnormality detection circuit 56 monitors the fluctuation of the phase difference data Do during the reception slot period, and generates a warning signal D3 when the fluctuation of the phase difference exceeds a predetermined value and an abnormal fluctuation occurs. Output.
[0032]
If the reception slot period is, for example, 280 times the reception (transmission) clock cycle, the phase difference data Do is output 280 times during the reception slot period. The detection circuit 56 executes an average value calculation process and an abnormality detection process based on the phase difference data Do output during the reception slot period.
[0033]
FIG. 3 is a diagram for explaining the phase difference abnormality detection in the phase difference abnormality detection circuit 56.
[0034]
Now, a phase lock range provided around a point where the phase of the transmission clock (TXCLK) matches the phase of the reproduction clock (RXCLK) is defined as a lock region, and a range of a phase delay up to 180 degrees beyond this lock region is delayed. Further, a range of phase advance up to 180 degrees beyond the lock region is referred to as a leading region.
[0035]
Here, during the reception slot period, the phase difference between the transmission clock (TXCLK) and the recovered clock (RXCLK) changes from the lock area to the advance area after passing through the delay area, or from the lock area to the advance area. And enters a delay region, and determines that an abnormal fluctuation (fluctuation) has occurred, and outputs a warning signal D3.
[0036]
The reason why the warning signal D3 is output is that, for example, when the vehicle enters the advance region due to further delay after passing through the delay region, erroneous information that the phase is advanced is output.
[0037]
Such a short-term phase difference fluctuation in the reception slot period may be caused, for example, when the mobile terminal is in a fading environment or when receiving an interference wave, because the reception state has deteriorated and the recovered clock (RXCLK ) Is considered to occur when sudden instability occurs.
[0038]
When the control circuit 57 receives the warning signal D3 from the phase difference abnormality detection circuit 56, the reproduction clock (RXCLK) is unstable, and there is a possibility that the timing may be incorrectly adjusted. It is determined that it should not be executed, and the process of adjusting the timing of the transmission clock is stopped.
[0039]
By the way, since the warning signal D3 is output based on the result of the phase difference fluctuation within the reception slot period, it is possible to cope with the fluctuation of the reception state within a short time. However, it is impossible to detect a change in the reception state in a period longer than the reception slot period. For this reason, a line quality estimating circuit 52 is provided to estimate fluctuations in the reception state over a relatively long period.
[0040]
The channel quality estimating circuit 52 calculates a bit error rate based on the phase information Dp output from the receiving unit 4, and integrates the bit error rate over a preset period (at least a period longer than the reception slot period). An average value is obtained, and line quality information Dq indicating a predetermined line quality state corresponding to the average bit error rate is output.
[0041]
For example, when the average bit error rate is less than 0.3%, the line quality information Dq is set to “0”, and when the average bit error rate is 0.3% or more to less than 1.0%, it is set to “1” and 1.0% or more. When it is less than 3.0%, it is “2”, and when it is more than 3.0%, it is “3”. This line quality information Dq is output to control circuit 57.
[0042]
The control circuit 57 determines that the reception state is unstable when the line quality state is degraded beyond a preset quality state, for example, when the line quality information Dq is “3” (average bit error rate is 0.3% or more). Therefore, it is determined that the transmission timing adjustment operation should not be performed, and the transmission timing adjustment processing is stopped.
[0043]
FIG. 4 is a flowchart showing the operation of the control circuit 57.
[0044]
Here, the control circuit 57 determines whether or not to execute transmission timing adjustment and generates timing control information Dt during reception of the reception slot, and executes control of transmission timing adjustment after the reception of the reception slot is completed.
[0045]
First, it waits for the reception completion interrupt signal (RXINT) indicating the reception completion of the reception slot (step 101). Then, when receiving the reception completion interrupt signal (RXINT), it checks whether or not there is a warning signal D3 (step 102).
[0046]
If the warning signal D3 is output, it is determined that the reception state of the reception slot is unstable and the transmission timing adjustment process should not be executed (step 102), and the generated timing control information Dt is invalidated and transmitted. The timing adjustment process of the clock (TXCLK) is stopped (step 103), and the process returns to step 101.
[0047]
If the warning signal D3 has not been output (step 102), the line quality information Dq is read (step 104). Here, when the line quality state is worse than the preset state, it is determined that the reception state of the reception slot is unstable and the transmission timing adjustment processing should not be executed (step 105), and the transmission clock The (TXCLK) timing adjustment process is stopped, and the process returns to step 101 (step 103).
[0048]
If the line quality state is better than the preset state (step 105), the phase difference average value D2 is read (step 106).
[0049]
Here, when the phase difference average value D2 is within the preset lock region, there is no need to perform the timing adjustment processing of the transmission clock (TXCLK) (Step 107), and therefore, Step 101 is performed without performing the timing adjustment processing. Return to (Step 103).
[0050]
If the average phase difference value D2 exceeds the preset lock area, it is necessary to adjust the timing of the transmission clock (TXCLK) (step 107), so that the phase difference is generated based on the instantaneous phase difference value D1. The received timing control information Dt is transmitted to the transmission clock generation circuit 51 after the reception of the reception slot is completed to perform the timing adjustment processing (step 108), and the process returns to step 101.
[0051]
The instantaneous phase difference value D1 used to generate the timing control information Dt uses a predetermined time point of the reception slot, for example, the instantaneous phase difference instantaneous value D1 of the reception slot.
[0052]
As described above, the disturbance of the reproduction clock is monitored for each slot, and when a disturbance equal to or greater than a preset value is detected, the transmission timing adjustment function is stopped, and the line is transmitted for a period longer than the reception slot period. By monitoring the quality status and stopping the transmission timing adjustment function when the line quality is lower than the preset line quality, it is possible to prevent malfunction of the transmission timing adjustment under a fading environment, and to prevent other operations due to transmission timing deviation. It is possible to prevent interference such as interference with mobile terminals and base stations and disconnection of lines.
[0053]
FIG. 5 is a block diagram showing another embodiment of the transmission timing adjustment unit.
[0054]
The difference between the transmission timing adjustment section 6 shown in FIG. 5 and the transmission timing adjustment section 5 shown in FIG. 1 is that the phase difference average value circuit 55 and the phase difference abnormality detection circuit 56 shown in FIG. The point is that a phase difference distribution circuit 65 for measuring the distribution state of the phase difference within the slot period is provided.
[0055]
That is, the transmission timing adjustment unit 6 estimates the line quality based on the transmission clock generation circuit 61 that generates the transmission clock (TXCLK) from the system clock (SYSCLK) and the phase information Dp output from the reception unit 4, and determines the line quality. A line quality estimating circuit 62 for outputting information Dq, a phase comparing circuit 63 for detecting a phase difference between the transmission clock (TXCLK) and the recovered clock (RXCLK), and a latch for the phase difference data Do output from the phase comparing circuit 63. Phase difference instantaneous value circuit 64 for outputting an instantaneous value D1 of the phase difference, and a phase difference distribution circuit for measuring the distribution state of the phase difference in the reception slot period based on the phase difference data Do and outputting phase difference distribution information D4. 65, phase difference instantaneous value D1, phase difference distribution information D4, reception completion interrupt signal (RXINT) and line quality information Dq. And a control circuit 66 for controlling the transmission clock generation circuit 61 receives been.
[0056]
For example, when the frequency of the system clock (SYSCLK) is 64 times the transmission clock, the phase difference distribution circuit 65 outputs the phase difference data Do (count values “0” to “63” of the counter) output from the phase comparison circuit 63. ), For example, as shown in FIG. 6, the distribution state of the phase difference during the reception slot period is obtained and output as phase difference distribution information D4. Note that, here, the count value indicating the phase difference ranges from “0” to “7” or “56” to “63” as the lock region.
[0057]
The control circuit 66 monitors the distribution state of the phase difference during the reception slot period based on the phase difference distribution information D4, and when the distribution state is such that the phase difference is abnormally distributed outside the lock region, It is determined that the reproduction clock (RXCLK) is unstable and the transmission timing adjustment process should not be executed, and the transmission clock timing adjustment process is stopped.
[0058]
FIG. 7 is a flowchart showing the operation of the control circuit 66.
[0059]
The control circuit 66 waits for generation of a reception completion interrupt signal (RXINT) indicating reception completion of the reception slot (step 201). Then, when receiving the reception completion interrupt signal (RXINT), the phase difference distribution information D4 is read (step 202).
[0060]
Here, when the phase difference distribution state is abnormal, it is determined that the reception state of the reception slot is unstable and the transmission timing adjustment process should not be executed (step 203), and the generated timing control information Dt is determined. The timing adjustment process of the transmission clock (TXCLK) is stopped as invalid (step 204), and the process returns to step 101.
[0061]
If the phase difference distribution state is normal (step 203), the line quality information Dq is read (step 205). Here, when the line quality state is worse than the preset state, it is determined that the reception state of the corresponding reception slot is unstable and the transmission timing adjustment process should not be executed (step 206), and the transmission clock The (TXCLK) timing adjustment process is stopped (step 204), and the process returns to step 101.
[0062]
When the line quality state is better than the state set in advance, it is determined whether or not the phase difference is concentrated and distributed in the lock area based on the phase difference distribution information D4. If so (step 207), the process returns to step 101 without performing the timing adjustment processing of the transmission clock (TXCLK) (step 204).
[0063]
If the phase difference is not concentrated and distributed in the lock region, the timing control information Dt generated based on the instantaneous phase difference value D1 is sent to the transmission clock generation circuit 51 to perform a timing adjustment process (step S1). 208), and the process returns to the step 101.
[0064]
As described above, even if the phase difference distribution state during the reception slot period is monitored and the phase difference distribution state indicates abnormal fluctuation of the phase difference, the transmission timing adjustment function is stopped, and the same effect is obtained. can get.
[0065]
【The invention's effect】
As described above, according to the present invention, the disturbance of the reproduction clock is monitored for each slot, and when the disturbance of a predetermined value or more is detected, a means for stopping the transmission timing adjustment function is provided. By monitoring the line quality state for a period longer than the slot period and providing a means for stopping the transmission timing adjustment function when the line quality has deteriorated to a value equal to or greater than a preset value, the transmission timing adjustment function in a fading environment is provided. Malfunctions can be prevented, and interference such as interference with other mobile terminals and base stations due to transmission timing deviation and line disconnection can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a diagram showing a phase difference detection operation of a phase comparison circuit 53 shown in FIG.
FIG. 3 is a diagram illustrating detection of a phase difference abnormality in the phase difference abnormality detection circuit 56 shown in FIG. 1;
FIG. 4 is a flowchart showing an operation of a control circuit 57 shown in FIG. 1;
FIG. 5 is a block diagram illustrating another embodiment of a transmission timing adjustment unit;
6 is a diagram illustrating an example of phase difference distribution information D4 output by the phase difference distribution circuit 65 illustrated in FIG. 5;
FIG. 7 is a flowchart showing an operation of the control circuit 66 shown in FIG.
[Explanation of symbols]
3 Transmission section 4 Receiving sections 5 and 6 Transmission timing adjustment sections 51 and 61 Transmission clock generation circuits 52 and 62 Line quality estimation circuits 53 and 63 Phase comparison circuits 54 and 64 Phase difference instantaneous value circuit 55 Phase difference average value circuit 56 Phase difference Abnormality detection circuits 57 and 66 Control circuit 65 Phase difference distribution circuit

Claims (7)

A transmitting unit that outputs a transmission slot according to a transmission clock, a receiving unit that generates and demodulates a reproduction clock synchronized with the reception slot, and adjusts the timing so that the frequency-divided output of the system clock is synchronized with the reproduction clock. In a mobile terminal including a transmission timing adjustment unit that outputs as a transmission clock, the transmission timing adjustment unit monitors a phase difference between the reproduction clock and the transmission clock, and detects a phase difference of the phase difference within a period of the reception slot. The mobile terminal characterized in that when the fluctuation range exceeds a predetermined value, the timing adjustment process of the transmission clock is stopped. The transmission timing adjustment unit has means for estimating the channel quality based on the average value of the bit error rate in the demodulation of the reception unit, and when the channel quality is deteriorated from a preset state, the transmission clock The mobile terminal according to claim 1, wherein the timing adjustment process is stopped. A transmitting unit that outputs a transmission slot according to a transmission clock, a receiving unit that generates and demodulates a reproduction clock synchronized with the reception slot, and adjusts the timing so that the frequency-divided output of the system clock is synchronized with the reproduction clock. In a mobile terminal including a transmission timing adjustment unit that outputs a transmission clock, the transmission timing adjustment unit includes a phase comparison circuit that detects a phase difference between the recovered clock and the transmission clock; and A phase difference abnormality detection circuit that detects a phase difference abnormality when a variation width of the phase difference exceeds a predetermined value; a transmission clock generation circuit that receives the system clock and the timing control information to generate the transmission clock; The timing control information is generated so that the phase difference becomes zero, and the phase difference abnormality detection circuit is generated. Mobile terminal when detecting a phase difference abnormality, characterized in that a control circuit for stopping the timing adjusting process of the transmission clock generation circuit. The transmission timing adjustment unit calculates a bit error rate based on phase information between a signal point of a received signal and a normal signal point in demodulation of the reception unit, and calculates an average of the bit error rates over at least a period longer than a reception slot period. A line quality estimating circuit for estimating a line quality state by obtaining a value, wherein the control circuit does not detect the phase difference abnormality, and when the line quality state deteriorates from a preset state, 4. The mobile terminal according to claim 3, wherein the timing adjustment process of the transmission clock is stopped. The transmission timing adjustment unit has a phase difference average value circuit that calculates an average value of the phase difference during a reception slot period, and the control circuit does not detect the phase difference abnormality and sets the line quality state in advance. 5. The movement according to claim 3, wherein the timing adjustment processing of the transmission clock is stopped when the phase difference average value is within a preset lock area, even if the phase is better than the state of the movement. Terminal. The transmission timing adjustment unit includes a phase difference distribution circuit that measures a distribution state of the phase difference within a reception slot period, and the control circuit performs a phase difference abnormality within a reception slot period based on the distribution state of the phase difference. The mobile terminal according to claim 3, wherein presence / absence of presence is detected. The control circuit of the transmission timing adjustment unit is configured such that even if the phase difference abnormality is not detected and the line quality state is better than a preset state, the distribution state of the phase difference is within a preset lock area. 7. The mobile terminal according to claim 6, wherein the timing adjustment process of the transmission clock is stopped when the distribution is concentrated on the mobile terminal.

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