JP2004172609A - Photoelectric conversion element and method for producing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photoelectric conversion element including a photodetector in which high photo-detection efficiency is realized, and time or labor required for production process is reduced, and to provide a method for producing the element. <P>SOLUTION: The photodetector (photoelectric conversion element) includes an Si layer 4 and a photo-detection part 6 having an SiGe layer 5 embedded within a groove formed in the Si layer 4. Width of the groove is set to be larger than critical thickness indicating the maximum thickness at which lattice-mismatch does not occur in the SiGe layer 5 when the layer 5 is stacked in a contact manner on the Si layer 4, and set to be a value not more than twice as the critical thickness. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a photoelectric conversion element and a method of manufacturing the same, and more particularly, to a configuration of a photoelectric conversion unit made of two kinds of semiconductor materials forming a heterojunction.

Among general semiconductor materials, silicon-germanium (SiGe) has a smaller band gap than silicon (Si). For example, a light-receiving element using SiGe as a light-receiving layer (photoelectric conversion layer) has a light-receiving element using Si. It is known that light having a longer wavelength than an element can be received. By setting the Ge concentration of the SiGe layer to an appropriate value, it is possible to realize an optical receiver that can cope with 1.3 μm band and 1.5 μm band wavelengths used in current optical communication technology. . Light receiving elements having a structure using a SiGe layer or a Si / SiGe superlattice layer as a light receiving layer have been proposed (for example, see Non-Patent Document 1, Patent Document 1, and Patent Document 2).
TPPEARSALL et al., "Avalanche Gain in GexSi1-x / Si Infrared Waveguide Detectors", IEEE ELECTRON DEVICE LETTERS, VOL. EDL-7, No.5, MAY 1986 JP-A-7-231113 JP-A-11-274315

  FIG. 13 is a cross-sectional view showing a conventional light receiving element using a Si / SiGe superlattice layer as a light receiving layer. FIG. 14 is a cross-sectional view showing only the light receiving layer. In this light receiving element, as shown in FIGS. 13 and 14, a high-concentration n-type buried layer 102 is formed on the surface of a p-type single-crystal Si substrate 101, and a p-type Si layer 103 is formed thereon. I have. The upper portion of the p-type Si layer 103 is processed into a mesa shape, and a Si / SiGe superlattice layer in which a number of Si layers 104 and SiGe layers 105 are alternately stacked on the p-type Si layer 103 in the mesa shape portion. 106, a high concentration p-type Si layer 107 is formed in this order from the bottom. And an electrode 110 whose surface is covered with an insulating film 108 and connected to the high-concentration n-type buried layer 102 via the high-concentration n-type extraction layer 109; An electrode 111 connected to the high-concentration p-type Si layer 107 is formed.

  In a conventional light-receiving element using a SiGe layer in the light-receiving portion, when a single-layer thick SiGe layer is formed to increase the light-receiving efficiency, strain caused by lattice mismatch between Si and SiGe is relaxed and lattice defects occur. In addition, there is a problem that a leak current occurs due to a lattice defect. Therefore, in order to use a plurality of SiGe layers, and to make the total of these SiGe film thicknesses equal to or more than the critical film thickness, it is common practice to use a Si / SiGe superlattice structure that suppresses the influence of strain as the light receiving layer. I have. The “critical film thickness” refers to an upper limit film thickness at which lattice defects due to strain relaxation do not occur when the film thickness is increased. For example, in Non-Patent Document 1 described above, the thickness of each SiGe layer is 3 nm, the thickness of each Si layer is 29 nm (about 10 times the thickness of SiGe), and the total thickness is 600 nm (total of 40 in the number of stacked layers). An example of a light-receiving layer is described. However, even when a superlattice structure is adopted, there is a problem that the film thickness is limited, and it is difficult to increase the light receiving efficiency.

  In the superlattice structure, the thickness of one SiGe layer cannot exceed the critical thickness. In addition, the critical thickness of the SiGe layer has a correlation with the Ge concentration, and the higher the Ge concentration, the larger the deviation of the lattice constant from Si becomes. Here, in particular, when the Ge concentration of the SiGe layer is increased so as to absorb light of a long wavelength, the critical film thickness becomes very small, so that the actual film thickness of each SiGe layer is further reduced.

  However, when the thickness of the SiGe layer becomes extremely thin, subbands such as E1 and E2 are formed due to the quantum effect as shown in the energy band diagram of the Si / SiGe superlattice layer in FIG. I will. As a result, while using the SiGe layer to cope with long-wavelength light, as shown in FIG. 16, the amount of light absorbed on the long-wavelength side decreases, that is, the light-receiving efficiency of long-wavelength light decreases. There was a problem. In a normal superlattice structure, the thickness of the SiGe layer must be equal to or less than the critical thickness, so that this problem cannot be avoided.

  Further, from the viewpoint of the manufacturing process, a very large number of films must be stacked to form a superlattice structure (as described above, about 40 layers in the example of Non-Patent Document 1). There was a problem that it took time and effort.

  The present invention has been made in order to solve the above-described problems, and realizes a high light receiving efficiency and a photoelectric conversion element including a light receiving element capable of reducing the time and labor required for a manufacturing process, and manufacturing the same. The aim is to provide a method.

  In order to achieve the above object, a photoelectric conversion element according to the present invention includes a photoelectric conversion element including a first semiconductor layer and a second semiconductor layer embedded in a groove formed in the first semiconductor layer. A conversion unit is provided. The width of the groove is a critical value that indicates the maximum film thickness at which lattice mismatch does not occur in the second semiconductor layer when the second semiconductor layer is stacked in contact with the first semiconductor layer. It is desirable that the thickness be larger than the film thickness and equal to or less than twice the critical film thickness. The terms “first semiconductor layer” and “second semiconductor layer” used herein have relatively close lattice constants and form a heterojunction. For example, the first semiconductor layer may be made of Si, SiGe is used as the semiconductor layer.

  The photoelectric conversion element of the present invention has a configuration in which a second semiconductor layer is embedded in a groove formed in a first semiconductor layer. In order to realize this configuration, a second semiconductor layer is formed along the inner wall surface of the groove of the first semiconductor layer at the time of manufacturing, and the second semiconductor layer grows from both side surfaces of the groove. Then, the second semiconductor layer can be finally buried in the entire inside of the groove. At this time, if the width of the groove is formed so as to be larger than the critical film thickness of the second semiconductor layer and equal to or less than twice the critical film thickness, the film thickness to be formed becomes the critical film thickness. Even below, a second semiconductor layer having a thickness equal to or greater than the critical thickness is formed inside the groove. As a result, it is possible to obtain a photoelectric conversion element having desired characteristics without a problem such as a decrease in efficiency due to a quantum effect.

  For example, when a light receiving element is configured by using the first semiconductor layer as Si and the second semiconductor layer as SiGe, the thickness of the SiGe embedded in the groove can be equal to or more than the critical thickness, and the influence of the quantum effect is reduced. Therefore, the light receiving efficiency on the long wavelength side can be improved as compared with the case where the conventional superlattice structure is used. Although the light receiving efficiency is also affected by the volume of the SiGe film, in the structure of the present invention, the volume of the SiGe film is determined by the depth of the groove, and the light receiving efficiency can be increased as the depth of the groove increases. There is no limit due to the critical film thickness as in the superlattice structure described above. When the thickness of the light receiving layer is limited due to the performance such as high-speed response of the device, the light receiving efficiency is determined by the ratio between the Si portion and the SiGe portion. However, in the case of the structure of the present invention, the light receiving efficiency is determined by the ratio of the groove width. The light receiving efficiency can be increased by improving the performance of the manufacturing apparatus or devising the process. In order to reduce the amount of strain as in the conventional superlattice structure, the Si portion does not have to be ten times as large as the SiGe portion as described in the above-mentioned paper, and is equal to or greater than the superlattice structure. The above light receiving efficiency can be realized.

  As a manufacturing process, at least three steps of “first semiconductor layer film formation”, “groove formation in the first semiconductor layer by etching or the like”, and “second semiconductor layer film formation” are required. The time and labor required for the manufacturing process can be reduced as compared with the conventional process in which several tens of / SiGe superlattice layers are alternately formed.

In addition, it is preferable that a plurality of the grooves are formed, and a second semiconductor layer filling each of the grooves covers the upper surface of the first semiconductor layer and is connected to each other.
In this configuration, the volume occupied by the second semiconductor layer can be relatively increased. For example, when the second semiconductor layer is made of SiGe, the second semiconductor layer can improve the light receiving efficiency particularly on the long wavelength side. The characteristics of the second semiconductor layer can be further utilized.

It is preferable that an etching stop layer is further provided on the lower surface of the first semiconductor layer, and the bottom surface of the groove is formed of the etching stop layer.
In this configuration, when a groove is formed by etching on the first semiconductor layer, the etching can be stopped at the etching stop layer, so that the depth of the groove can be easily controlled, and the performance can be improved. Stabilization can be achieved.
For example, the first semiconductor layer can be made of Si, the second semiconductor layer can be made of SiGe, and the etching stop layer can be made of SiGe.
In the case of this configuration, an etching agent such as EPW (a mixed solution of ethylenediamine / pyrocatechol / water) can be used, and a vertically steep groove is formed by utilizing the anisotropy of the etching agent with respect to Si etching. can do.

In addition, a plurality of photoelectric conversion units each including the first semiconductor layer and the second semiconductor layer may be stacked in the thickness direction of the first semiconductor layer.
In this configuration, even when the depth of the groove is a processing limit due to the performance of the manufacturing apparatus or the like, a photoelectric conversion unit having a deep groove structure is formed by stacking a plurality of photoelectric conversion units having a shallow groove structure. The same performance can be obtained.

Further, a configuration may further be provided that further includes a groove width adjusting layer between at least a side wall surface of the groove and the second semiconductor layer.
In this configuration, as described above, when the width of the groove is controlled to be larger than the critical film thickness and equal to or less than twice the critical film thickness, a narrow groove is formed due to the processing limit of the manufacturing apparatus. Even in the case where the groove cannot be formed, the groove can be narrowed by forming the groove width adjusting layer on at least the side wall surface of the groove, and the second semiconductor layer having a desired film thickness can be formed. .

In the present invention, there is provided a photoelectric conversion unit formed by alternately stacking a plurality of first semiconductor layers made of silicon and a plurality of second semiconductor layers containing silicon and germanium, wherein the second semiconductor The thickness of the layer is larger than a critical film thickness that indicates a maximum film thickness at which no lattice mismatch occurs in the second semiconductor layer, and is equal to or less than twice the critical film thickness. What you do.
In the present invention, the second semiconductor layer is formed by crystal growth based on the first semiconductor layers on both sides sandwiching the second semiconductor layer, and has a thickness of the second semiconductor layer. A phase shift plane of a crystal lattice resulting from a coupling portion of semiconductor crystals grown from both of the first semiconductor layers may be formed at a central portion in the direction.
If the film is simply formed with a film thickness larger than the critical film thickness, a large number of lattice mismatch portions are generated in the second semiconductor layer during film formation. Therefore, if the second semiconductor layer is formed so as to grow a crystal from both of the first semiconductor layers facing each other at a position sandwiching the second semiconductor layer, one side of the first semiconductor layer A second semiconductor layer having a thickness equal to or less than the critical thickness grown from the first semiconductor layer and a second semiconductor layer having a thickness equal to or less than the critical thickness grown from the other semiconductor layer. Therefore, it is possible to obtain a second semiconductor layer having a thickness up to twice the original critical thickness and having no lattice mismatching portion.

According to the method of manufacturing a photoelectric conversion element of the present invention, a step of forming a first semiconductor layer made of a first semiconductor material on a substrate, a step of forming a groove in the first semiconductor layer, Forming a second semiconductor layer by embedding a second semiconductor material.
According to the method for manufacturing a photoelectric conversion element of the present invention, a photoelectric conversion element having desired characteristics as described above and capable of simplifying the manufacturing process can be obtained.

  Forming the groove by etching, and before forming the first semiconductor layer, further comprising a step of forming an etching stop layer between the substrate and the first semiconductor layer to prevent the etching. Is also good. The method may further include, after the formation of the groove, a step of forming a groove width adjusting layer that covers at least a side wall surface of the groove and reduces the width of the groove, and thereafter, the second semiconductor layer may be formed. .

According to the manufacturing method of the present invention, the photoelectric conversion has a structure in which a plurality of first semiconductor layers made of Si and a plurality of second semiconductor layers containing at least Si and high-concentration Ge are alternately stacked on a substrate. A method of manufacturing a photoelectric conversion element having a portion, wherein the second semiconductor layer laminated on the first semiconductor layer has a lower thickness than the critical thickness of the second semiconductor layer having a high Ge concentration. After stacking the pre-generation layers having a Ge concentration, removing at least a portion of the plurality of pre-generation layers corresponding to the photoelectric conversion portions by etching after the lamination, the pre-generation layers are formed of Si existing at positions sandwiching the removed pre-generation layers. Crystal growth is performed based on the first semiconductor layer, and a second semiconductor layer having a high Ge concentration thicker than the critical film thickness is formed in the removed portion to fill the removed portion. But it's fine.
If the second semiconductor film is simply formed to have a thickness larger than the critical thickness, a large number of lattice mismatch portions occur in the second semiconductor layer at the time of film formation. Therefore, if the semiconductor layer is formed so as to grow the crystal from both of the first semiconductor layers facing each other at the position sandwiching the second semiconductor layer, the first semiconductor layer is grown from one side of the first semiconductor layer. A semiconductor layer having a thickness equal to or less than the critical thickness and a semiconductor layer having a thickness equal to or less than the critical thickness grown from the other semiconductor layer side can be joined to form one second semiconductor layer. A second semiconductor layer having a thickness up to twice the thickness and having no lattice mismatch portion can be obtained.

  In the manufacturing method of the present invention, the second Ge layer having a high Ge concentration contains Ge in a range of 50 to 100%, and the pre-generation layer having a low Ge concentration contains Ge in a range of 5 to 40%. May be used.

  As described above in detail, according to the present invention, it is possible to obtain a photoelectric conversion element having desired characteristics in which the light conversion efficiency does not decrease even on the high wavelength side, and to reduce the time and labor required for the manufacturing process of the photoelectric conversion element. Can be reduced.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a cross-sectional view illustrating a light receiving element (photoelectric conversion element) according to the present embodiment.
In the light receiving element of the present embodiment, as shown in FIG. 1, a high-concentration n-type buried layer 2 is formed on the surface of a p-type single-crystal Si substrate 1, and a p-type Si layer 3 is formed thereon. ing. The upper part of the p-type Si layer 3 is processed into a mesa-shaped shape, and a light-receiving part 6 (photoelectric conversion part) composed of a non-doped Si layer 4 and a SiGe layer 5 is formed on the mesa-shaped part of the p-type Si layer 3. And a high concentration p-type Si layer 7 is formed thereon. And an electrode 10 in which the mesa-shaped portion and the other surface of the p-type Si layer 3 are covered with the insulating film 8 and connected to the high-concentration n-type buried layer 2 via the high-concentration n-type extraction layer 9; An electrode 11 connected to the high-concentration p-type Si layer 7 is formed.

  As shown in FIG. 2, the configuration of the light receiving section 6 is such that a Si layer 4 (first semiconductor layer) having a thickness of, for example, about 0.6 μm is formed on the p-type Si layer 3 and the thickness direction of the Si layer 4 is changed. And a plurality of grooves 4a extending in one direction (a direction perpendicular to the paper surface of FIG. 2). That is, when the Si layer 4 is viewed in a plan view, a portion where Si is present and a portion of the groove are arranged in stripes, and the depth of the groove 4a is 0.6 μm which is equal to the film thickness of the Si layer 4. Has become. The width W of the groove 4a is set to be larger than the critical thickness of the SiGe layer 5 to be formed thereon and equal to or less than twice the critical thickness of the SiGe layer 5. The critical film thickness of the SiGe layer 5 varies depending on the Ge concentration. For example, when the Ge concentration is 30%, it is about 0.05 μm. Therefore, in this case, the width of the groove is about 0.05 μm to 0.1 μm. In this example, the plurality of grooves 4a are assumed to extend only in one direction. However, for example, in addition to this groove, a configuration having another plurality of grooves extending in a direction intersecting with the groove (that is, a plan view) As shown in FIG.

  Then, SiGe is embedded in the plurality of grooves 4 a formed in the Si layer 4, and SiGe integrated with the SiGe inside each groove 4 a is formed on the upper surface of the Si layer 4, thereby forming the SiGe layer. 5 (second semiconductor layer). When the SiGe layer 5 is formed, SiGe also grows from the side wall surface of the groove 4a. Therefore, the inside of the groove 4a is completely buried by forming a film of SiGe having a thickness of at least half the width of the groove 4a. be able to.

Next, a method for manufacturing the light receiving element having the above configuration will be described with reference to FIGS. 4 is a manufacturing process diagram of the entire light receiving element, and FIG. 3 is a manufacturing process diagram particularly showing only the light receiving portion 6.
First, as shown in FIGS. 4A, 3A and 3B, a high-concentration n-type buried layer 2 is formed on the surface of a p-type single-crystal Si substrate 1, and a p-type buried layer 2 is formed thereon. The type Si layer 3 and the Si layer 4 are sequentially laminated. Since the film forming temperature at the time of forming the Si layer 4 is before forming the SiGe layer, it can be set to 500 ° C. or more. Next, an etching mask 13 for forming the groove 4a in the Si layer 4 is formed on the Si layer 4. Generally, a resist film is used as the etching mask 13, but a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN _x ) may be patterned and used as an etching mask due to a problem of etching resistance. In this embodiment, a resist film is used when the groove is relatively shallow, and when a deep groove or anisotropic etching by wet etching is performed, a SiO ₂ film or a SiN _x film is used instead of the resist film. It is patterned to form an etching mask 13.

  Next, as shown in FIGS. 4B and 3C, the Si layer 4 in a portion to be the light receiving section 6 is etched to form a groove 4a, and then the etching mask 13 is removed. At this time, the width of the groove 4a is set to be one to twice the critical thickness of the SiGe layer to be formed later. The etching used here may be either dry etching or wet etching. However, if dry etching is used, the bottom of the groove 4a may be damaged depending on the condition, which may cause a leak current. Can be avoided. If the upper surface of the Si layer 4 is made to have a (110) crystal plane when forming the Si layer 4, the side wall surface of the groove 4a becomes a (111) crystal plane. For example, when an alkaline etchant such as EPW (a mixture of ethylenediamine / pyrocatechol / water) is used, etching proceeds on the (110) plane of Si, but does not proceed on the (111) plane. Therefore, anisotropic etching can be performed, and the vertically steep groove 4a can be formed. In the method of the present embodiment, since the underlying layer of the Si layer 4 is also the p-type Si layer 3 which is the same silicon film, the end point of the etching is controlled by the etching time. According to this method, a vertical groove can be formed without damaging the base, and a leak current can be suppressed.

  Next, as shown in FIG. 4C, a SiGe layer 5 is formed by burying SiGe inside the trench 4a, and then a high-concentration p-type Si layer 7 is formed. At this time, as shown in FIG. 3D, the SiGe layer 5 grows from both side walls and the bottom surface of the groove 4a, and the width of the groove 4a is 1-2 times the critical thickness of the SiGe layer 5. Therefore, as shown in FIG. 3E, before the thickness of the SiGe layer 5 exceeds the critical thickness (at the time when the thickness of at least half the width of the groove 4a is formed), as shown in FIG. The inside of the groove 4 a is filled with the SiGe layer 5. In this manner, the SiGe layer 5 having a thickness equal to or greater than the critical film thickness is formed inside the groove 4a as a state after the film formation, although the film thickness is equal to or less than the critical film thickness. Thereafter, as shown in FIG. 3F, a high-concentration p-type Si layer 7 is formed.

  Next, as shown in FIG. 4D, a part of the high-concentration p-type Si layer 7, the SiGe layer 5, the Si layer 4, and the p-type Si layer 3 is patterned and processed into a mesa shape. And Thereafter, as shown in FIG. 4E, an insulating film 8 is formed on the surface of the mesa-shaped light receiving portion 6 and the other p-type Si layer 3, and a high-concentration n-type lead layer 9 and electrodes 10 and 11 are formed. Form sequentially. Through the above steps, the light receiving element of the present embodiment is completed.

  In the light receiving element of the present embodiment, the SiGe layer 5 can be embedded in the entire groove 4a by forming the SiGe layer 5 along the inner wall surface of the groove 4a formed in the Si layer 4. At this time, since the width of the groove 4a is in the range of 1 to 2 times the critical film thickness of the SiGe layer 5, the film thickness of the SiGe layer 5 is less than the critical film thickness and the inside of the groove 4a is not more than the critical film thickness. In this case, a SiGe layer 5 having a thickness greater than the critical thickness is formed. As a result, the effect of the quantum effect can be reduced, so that the light receiving efficiency on the long wavelength side can be improved as compared with the case where the conventional superlattice structure is used. The light receiving efficiency also depends on the volume of the SiGe layer 5, but in the structure of the present invention, the volume of the SiGe layer 5 is determined by the depth of the groove 4a, and the light receiving efficiency is increased as the groove 4a is deeper. And there is no limit due to the critical film thickness unlike the conventional superlattice structure. When the thickness of the light receiving portion 6 is limited due to the performance such as high-speed response of the device, the light receiving efficiency is determined by the ratio between the Si portion and the SiGe portion. In the case of the structure of the present embodiment, however, the light receiving efficiency is determined by the ratio of the groove width. Therefore, the light receiving efficiency can be sufficiently increased by improving the performance of the manufacturing apparatus or devising the process. Also in the manufacturing process, the time and labor required for the manufacturing process can be significantly reduced as compared with the conventional process in which several tens of superlattice layers of Si / SiGe are alternately formed.

[Second embodiment]
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 5 is a cross-sectional view showing only a light-receiving portion of the light-receiving element of the present embodiment, and FIG. 6 is a process cross-sectional view showing a manufacturing process thereof.
The basic configuration of the light receiving element of this embodiment is the same as that of the first embodiment, except for the configuration of the light receiving section. Therefore, the description of the basic configuration will be omitted below, and only the configuration of the light receiving unit will be described. 5 and 6, the same reference numerals are given to the same components as those in FIGS. 2 and 3.

  Also in the light receiving section 16 of the present embodiment, as shown in FIG. 5, a groove 4a having a width of 1 to 2 times the critical thickness of the SiGe layer 5 is formed in the Si layer 4, and SiGe is formed inside the groove 4a. Is embedded to form a SiGe layer 5. This configuration is the same as in the first embodiment. On the other hand, the difference from the first embodiment lies in that the etching stop layer 15 is formed on the lower surface side of the Si layer 4 (between the Si layer and the p-type Si layer). In the case of the present embodiment, the etching stop layer 15 is made of a material having resistance to etching of Si, in particular, alkaline wet etching, and when EPW is used as an etching agent, for example, the film thickness is 5 to 10 nm. A SiGe film having a Ge concentration of about 5% or more can be used. When the SiGe film functions as the etching stop layer 15 of the present embodiment, the Ge concentration is desirably 5 to 10%.

A method for forming the light receiving unit 16 having the above configuration will be described with reference to FIG.
As shown in FIG. 6A, an etching stop layer 15 made of the SiGe film is formed on the p-type Si layer 3, and an Si layer 4 is formed thereon. Next, as shown in FIG. 6B, an etching mask 13 for forming a groove on the Si layer 4 is formed. Here, a silicon nitride film (Si ₃ N ₄ ) is used as the etching mask 13. This is because the resist film has no resistance to anisotropic wet etching. Therefore, after forming a Si ₃ N ₄ film on the Si layer 4, it is patterned by a photolithography process to form an etching mask 13.

  Next, as shown in FIG. 6C, a groove 4a is formed in the Si layer 4 by wet etching. In the case of this embodiment, similarly to the first embodiment, when an alkaline etchant such as EPW is used, etching proceeds on the (110) plane of Si, while etching proceeds on the (111) plane. Since the etching does not proceed, the vertical groove 4a can be formed by setting the upper surface of the Si layer 4 to the (110) crystal plane. However, in the case of the first embodiment, since the base of the Si layer 4 is also the p-type Si layer 3, the end point of the etching has to be controlled over time. On the other hand, in the case of the present embodiment, since the etching stop layer 15 made of the SiGe film is provided under the Si layer 4, the etching reaches the etching stop layer 15, and the SiGe film is formed on the bottom surface of the groove 4a. Stop when exposed. The alkaline etchant such as EPW used in the present embodiment has etching anisotropy due to the crystal plane and also has etching selectivity to Si / SiGe. According to this method, the depth of the groove 4a can be easily controlled without controlling the etching time. After forming the groove 4a, the etching mask 13 is removed.

  Next, as shown in FIG. 6D, the SiGe layer 5 is formed by burying SiGe inside the trench 4a. At this time, since the width of the groove 4a is set to be 1 to 2 times the critical film thickness of the SiGe layer 5, even if the film to be formed is less than the critical film thickness, the inside of the groove 4a remains in the state after film formation. A SiGe layer 5 having a thickness equal to or greater than the critical thickness is formed. Thereafter, as shown in FIG. 6E, a high-concentration p-type Si layer 7 is formed.

  Also in the present embodiment, the same effects as in the first embodiment, such as a simple manufacturing process and a light receiving element having excellent light receiving efficiency, can be obtained. In addition, in the case of the present embodiment, since the etching stop layer 15 is provided on the lower surface of the Si layer 4, by performing a slight over-etching, the Si layer 4 does not remain on the bottom surface of the groove 4a. Etching of the Si layer 4 is stopped in a state where the etching stop layer 15 is securely exposed to the bottom surface of the groove 4a, that is, in a state where the Si layer 4 is completely removed in the thickness direction. Therefore, in the first embodiment, when the over-etching is performed, it is conceivable that the p-type Si layer 3 underlying the Si layer 4 may be clogged, and the depth of the groove 4a may vary. In the case of the present embodiment, the depth of the groove 4a matches the thickness of the Si layer 4, and the depth of the groove 4a is determined by the thickness of the Si layer 4. As described above, according to the method of the present embodiment, a variation in the depth of the groove 4a due to etching does not occur, and a light receiving element having stable characteristics can be provided.

[Third Embodiment]
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS.
FIG. 7 is a cross-sectional view showing only the light-receiving portion of the light-receiving element of the present embodiment, and FIG. 8 is a process cross-sectional view showing the manufacturing process.
The basic configuration of the light receiving element of this embodiment is the same as that of the first embodiment, except for the configuration of the light receiving section. Therefore, the description of the basic configuration will be omitted below, and only the configuration of the light receiving unit will be described. 7 and 8, the same reference numerals are given to the same components as those in FIGS. 2 and 3.

  In the light receiving section 26 of the present embodiment, similarly to the first and second embodiments, as shown in FIG. 7, the groove 4a having a width of 1 to 2 times the critical thickness of the SiGe layer 5 The SiGe layer 5 is formed in the layer 4 and SiGe is buried inside the groove 4a. Further, the point that an etching stop layer 15 made of SiGe or the like is formed on the lower surface side of the Si layer 4 (between the Si layer 4 and the p-type Si layer 3) is the same as in the second embodiment. However, the difference from the second embodiment is that the bottom surface of the groove 4a is not constituted by the etching stop layer 15, but the bottom surface of the groove 4a is constituted by an Si layer. Next, a manufacturing process will be described. In the case of the present embodiment, after a groove is formed in the first Si layer 41, the second layer is formed along the upper surface of the first Si layer 41, the side wall surface and the bottom surface of the groove 4a. Such a configuration is obtained by forming the Si layer 42 (groove width adjusting layer) as a layer.

A method for forming the light receiving section having the above configuration will be described with reference to FIG.
As shown in FIG. 8A, after an etching stop layer 15 made of a SiGe film and a Si layer 41 are laminated on the p-type Si layer 3, an etching mask 13 made of Si3N4 or the like is formed on the Si layer 4. Next, as shown in FIG. 8B, a groove 4b is formed in the Si layer 41 by wet etching. In the case of this embodiment, as in the first and second embodiments, the vertical groove 4b can be formed by using anisotropic etching with an alkaline etchant such as EPW. The groove width at this point is W. Further, since the etching stop layer 15 made of a SiGe film is provided under the Si layer 4, the depth of the groove 4b can be easily controlled without controlling the etching time. After forming the groove 4b, the etching mask 13 is removed. The above steps are the same as in the second embodiment.

  Next, as shown in FIG. 8C, a thin Si layer 42 (groove width adjusting layer) is formed on the entire surface of the substrate. At this time, the thickness of the Si layer 42 is set to be equal to or less than half the width W of the groove 4b so that the groove 4b formed in the previous step is not filled with the Si layer 42. Then, a thin Si layer 42 is formed along the upper surface of the Si layer 41, the side wall surface and the bottom surface of the groove 4b, and the first Si layer 41 and the second Si layer 42 are integrated with each other. The width of the groove 4a is reduced. That is, assuming that the thickness of the Si layer 42 to be formed is t, the groove width is adjusted to a dimension W ′ represented by W ′ = W−2t.

  Next, as shown in FIG. 8D, a SiGe layer 5 is formed by burying SiGe inside the trench 4a. At this time, since the width of the groove 4a is set to be one to two times as large as the critical thickness of the SiGe layer 5, even if the film to be formed is less than the critical thickness, the inside of the groove 4a remains in the state after the film formation. A SiGe layer 5 having a thickness equal to or greater than the critical thickness is formed. Thereafter, as shown in FIG. 8E, a high-concentration p-type Si layer 7 is formed.

  Also in this embodiment, the same effects as in the first and second embodiments, such as a simple manufacturing process and a light receiving element having excellent light receiving efficiency, can be obtained. Further, by providing the etching stop layer 15, the same effect as in the second embodiment can be obtained, such that a variation in groove depth is small and a light receiving element having stable characteristics can be obtained. In particular, in the case of the present embodiment, a method is employed in which a groove 4b is once formed in the Si layer 41, and then a thin Si layer 42 is formed again along the inner surface of the groove 4b. Can be made narrower than the limit of fine processing by photolithography technology. Therefore, for example, when the Ge concentration in the SiGe layer 5 is increased in order to manufacture a light-receiving element having a high light-receiving efficiency on the long wavelength side, the critical film thickness decreases with an increase in the Ge concentration. Even if the width has to be narrower than the limit of the fine processing by the photolithography technology, the method according to the present embodiment can cope with it. At this time, the width of the groove 4a can be adjusted by adjusting the thickness of the Si layer 42 to be formed later.

  In the present embodiment, the once formed groove 4b is narrowed by using the Si layer 42. However, the material of the layer formed for adjusting the width of the groove is not limited to Si, and is not limited to Si. As long as the material has good lattice matching, a material other than Si, such as SiC, may be used.

[Fourth Embodiment]
Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG.
FIG. 9 is a cross-sectional view showing only the light receiving portion of the light receiving element of the present embodiment.
The basic configuration of the light receiving element of this embodiment is the same as that of the first embodiment, except for the configuration of the light receiving section. Therefore, the description of the basic configuration will be omitted below, and only the configuration of the light receiving unit will be described. Also, in FIG. 9, the same reference numerals are given to the same components as those in FIG.

In the case of the present embodiment, as shown in FIG. 9, a structure in which a plurality of light receiving portions 6 (three stages in FIG. 9) having a structure in which a SiGe layer 5 is embedded in a groove 4a of a Si layer 4 is repeatedly formed. It has become.
In this configuration, even when the depth of the groove cannot be made too large due to the limitations of the film forming technology, the etching technology, and the like, the light receiving portion 6 having the shallow groove structure is stacked in a plurality to form the deep groove structure. Performance equal to or higher than that of the light receiving unit can be obtained. Further, in the case of this configuration, since the Si layer 4 and the SiGe layer 5 are alternately stacked, the SiGe layer 5 constituting the light receiving unit 6 itself can be used as an etching stop layer when forming the groove 4a. Function.

[Fifth Embodiment]
Hereinafter, a fifth embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a cross-sectional view illustrating a light receiving element (photoelectric conversion element) according to the present embodiment. Among the elements described below, the same elements as those of the first embodiment described above are used. Are denoted by the same reference numerals, and detailed description of those portions will be omitted.
In the light receiving element of the present embodiment, as shown in FIG. 10, a high-concentration n-type buried layer 2 is formed on the surface of a p-type single-crystal Si substrate 1, and a p-type Si layer 3 is formed thereon. ing. The upper portion of the p-type Si layer 3 is processed into a mesa shape, and a non-doped Si layer (first semiconductor layer) 24 and a SiGe layer (second semiconductor layer) are formed on the mesa-shaped portion of the p-type Si layer 3. ) 25 are formed, and a light receiving portion 26 (photoelectric conversion portion) is formed by laminating a plurality of such layers, and a high-concentration p-type Si layer 7 is formed thereon. And an electrode 10 in which the mesa-shaped portion and the other surface of the p-type Si layer 3 are covered with the insulating film 8 and connected to the high-concentration n-type buried layer 2 via the high-concentration n-type extraction layer 9; An electrode 11 connected to the high-concentration p-type Si layer 7 is formed.

That is, in the configuration of the fifth embodiment, the light receiving unit (photoelectric conversion unit) 6 including the non-doped Si layer 4 and the SiGe layer 5 of the components of the first embodiment described above is shown in FIG. It is characterized in that it is a light receiving section (photoelectric conversion section) 26 composed of a non-doped Si layer 24 and a SiGe layer 25 having a plurality of layers alternately stacked in the thickness direction showing the cross-sectional structure. In the configuration of this embodiment, the SiGe layer 25 is larger than the critical thickness of the SiGe layer that can be formed as a single layer without generating lattice defects due to strain relaxation by a normal film forming method. It is set to less than twice the value.
Normally, the critical thickness of the SiGe layer changes depending on the Ge concentration, but is, for example, about 0.05 μm when the Ge concentration is 30%. Therefore, in the case of the fifth embodiment, the thickness of the SiGe layer 25 is about 0.05 μm to 0.1 μm.

Next, a manufacturing method capable of alternately stacking the SiGe layers 25 thicker than the critical film thickness on the Si layer 24 will be described below with reference to FIG. FIG. 12 shows only a light receiving section (photoelectric conversion section) 26 of the light receiving element (photoelectric conversion element) according to the fifth embodiment and describes a manufacturing method thereof. The description is omitted.
First, as in the first embodiment, a high-concentration n-type buried layer 2 is formed on the surface of a p-type single-crystal Si substrate 1 and, as shown in FIG. The type Si layer 3 is laminated. The manufacturing steps up to here may be basically the same as the steps described in the case of the manufacturing method of the configuration of the first embodiment based on FIG.
Next, on the p-type Si layer 3, a required number of layers of a low Ge concentration SiGe layer (preliminary layer) 35 and a non-doped Si layer 24 are alternately laminated. At this time, the Ge concentration of the SiGe layer 35 is set in a range of about 5 to 40%, and the thickness is set to 1 to 2 times the critical thickness of the high-Ge-concentration SiGe layer to be formed later. Since the Ge concentration is low, the film formation temperature at the time of forming the SiGe layer 35 can be set to 500 ° C. or more, for example, 500 to 650 ° C. Here, when the Ge concentration is 30%, the critical thickness of the SiGe layer is about 0.05 μm, but when the Ge concentration is 20%, the critical thickness is about 0.15 μm, and when the Ge concentration is 10%, Since the critical thickness is about 0.8 μm and the critical thickness when the Ge concentration is 5% is about 5 μm, depending on the Ge concentration, the critical thickness of the high-Ge-concentration SiGe layer to be formed later is 1 to 2 times. It can be understood that the SiGe layer 35 having twice the thickness and having a low Ge concentration can be formed.

After the alternate lamination of the low-Ge-concentration SiGe layer 35 and the non-doped Si layer 24 is completed, the high-concentration p-type Si layer 27 and the insulating film 28 are laminated on the uppermost Si layer 24 to form an etching mask.
Next, by dry etching, a plan view is taken to a position sandwiching both sides of the region to be the light receiving section 26 shown in FIG. 10 and a depth reaching the upper surface of the p-type Si layer 3 as shown in FIG. The rectangular holes 30 are formed. Next, a selective etching process is performed through these holes 30. An etchant that etches the SiGe layer and does not etch the Si layer during the selective etching process is used. The etchant used here can be a mixture of hydrofluoric nitric acid, hydrofluoric acid, aqueous hydrogen peroxide, and acetic acid.
By this selective etching process, only the low-Ge-concentration SiGe layer 35 around the holes 30, 30 as shown in FIG. By this processing, a cavity 36 is formed between the holes 30, 30 and in the vicinity thereof, where only the low-Ge-concentration SiGe layer 35 is removed.
Note that, here, the SiGe layer 35 outside the periphery of the hole 30 is also partially removed, but the selective etching in this step mainly removes the SiGe layer 35 at the position sandwiching both sides of the region to be the light receiving portion 26. Since only the SiGe layer 35 between the holes 30 and 30 and the SiGe layer 35 around the holes 30 and 30 remain, and the SiGe layer 35 formed in other peripheral portions remains, the Si layer remaining between the holes 30 and 30 24 is left in a multi-layer bridge state, and a plurality of hollow portions 36 are formed between them.

Next, a SiGe layer 25 having a high Ge concentration is formed on the inner surfaces of the holes 30, 30 and the inner surface of the cavity 36 and on the insulating layer 28 by a film forming method using a reaction gas such as MOCVD, LPCVD, or UHV-CVD. (Ge concentration: 50 to 100%).
Here, when the SiGe layer is formed in each cavity 36 from the state shown in FIG. 12C, the SiGe layer grows with good consistency from the surface of the Si layer which partitions the plurality of cavities 36. Therefore, even if the height of each cavity 36 is in the range of 1 to 2 times the critical thickness of the SiGe layer having a high Ge concentration, both the ceiling layer and the Si layer forming the bottom surface of the cavity 36 are formed. As a result, a SiGe layer having a high Ge concentration within the critical film thickness can be grown until the cavity portion 36 is completely filled, and as a result, the defect-free SiGe layer is thicker than the critical film thickness. The hollow portion 36 can be filled with 25, and the SiGe layer 25 having a thickness in the range of 1 to 2 times the normal critical film thickness can be generated.
Thereafter, the insulating film 28 is etched into a required shape, and the SiGe layer remaining on the uppermost portion is removed by lift-off, whereby the light receiving section 26 having a laminated structure can be formed. Note that, on both sides of the light receiving portion 26, a structure in which the SiGe layer 25 having a high Ge concentration is adhered to the inner surfaces of the holes 30, 30 remains, but this portion is left as it is, and the holes 30, 30 do not appear. When viewed from a cross-sectional direction (a cross-sectional direction crossing 90 ° with the cross-sectional direction shown in FIG. 12), the same process as in the first embodiment shown in FIGS. By forming the n-type extraction layer 9, the electrode 10, and the electrode 11, the structure shown in FIG. 10 can be obtained.
In the case where the extraction layer 9 and the electrodes 10 and 11 are formed by performing the same steps as those of the first embodiment shown in FIGS. 4C to 4E, the hole 30 is formed by etching. , 30 may be removed, and then the high-concentration n-type extraction layer 9, the electrode 10, and the electrode 11 may be formed.
Further, when the alternately laminated structure of the Si layer 24 and the SiGe layer 25 is formed by employing the method described above, as shown in FIGS. 12D and 12E, the Si layer between the holes 30, 30 is formed. 24 has a structure in which both ends are covered with a high-Ge-concentration SiGe layer 25. This portion may be removed by etching in a later step, but may be left.

According to the structure obtained by the above-described manufacturing method, since the SiGe layer 25 having a high Ge concentration and constituting the light receiving portion 26 is formed to be thick in the range of 1 to 2 times the critical film thickness, a quantum effect occurs. Since the generation of sub-bands is difficult, the light absorption efficiency does not decrease even on the high frequency side, and a light receiving element with good light conversion efficiency can be obtained. In other words, there is an effect that the light conversion efficiency in a high wavelength region is higher than that of a light receiving element having a superlattice structure in which SiGe layers having a thickness equal to or less than a normal critical thickness are stacked.
Next, in this type of light receiving element, the light receiving efficiency is also determined by the volume of the SiGe layer. In this aspect, in the present invention, since the stacked structure is formed using the low-Ge-concentration SiGe layer 35 at one end, the number of stacked low-Ge-concentration SiGe layers 35 that are not easily affected by distortion can be increased. For example, when the thickness of the light-receiving layer is limited due to the performance such as high-speed response of the device, the light-receiving efficiency is determined by the ratio between the Si layer portion and the SiGe layer portion. Therefore, the Si layer portion must be formed thick and the SiGe layer portion must be formed thin. For example, as described in Non-Patent Document 1 described above, the Si layer had to be about 10 times as thick as the SiGe layer. On the other hand, according to the structure of the present invention, a SiGe layer having a low Ge concentration is formed once without being restricted by the strain amount of the SiGe layer having a high Ge concentration, and after removing the SiGe layer, a SiGe layer having a high Ge concentration is removed. Since it is formed, the thickness of the Si layer can be made smaller than that of the structure of Non-Patent Document 1, so that performance equivalent to or higher than that of the conventional structure can be expected from the viewpoint of high-speed response.

  Further, in the above-described manufacturing process, three large processes such as lamination of a required number of Si layers / low-Ge-concentration SiGe layers, etching of the Si layers, and formation of a high-Ge-concentration SiGe layer are required. In the formation of the Si layer / high-Ge-concentration SiGe layer, the film-forming rates of the Si film and the high-Ge-concentration SiGe layer are significantly different. Since it was necessary to change the film forming temperature, it took a very long time to raise and lower the temperature, and the film forming time was long. However, as shown in this example, the film formation of the Si layer / low-Ge-concentration SiGe layer If so, the film can be formed without changing the temperature, so that the film formation time can be greatly reduced. That is, according to the manufacturing method of the present embodiment, the high-Ge-concentration SiGe layer needs to be formed only once so as to fill the cavity 36. The number of times the temperature needs to be raised and lowered several tens of times is reduced to one, and the process time can be greatly reduced.

As described above, when the SiGe layer 25 having a high Ge concentration is formed by crystal growth from both the Si layer 24 on the ceiling side and the Si layer 24 on the bottom side of the cavity 36, the center of the cavity 36 in the height direction is formed. The high-Ge-concentration SiGe layer 25 grown from the ceiling-side Si layer 24 and the high-Ge-concentration SiGe layer 25 grown from the bottom-side Si layer 24 are joined to fill the cavity 36. In other words, a portion where the phase of the crystal lattice is shifted occurs in the central portion in the thickness direction of the SiGe layer 25 having a high Ge concentration. Therefore, there is a plane whose phase is shifted at the center in the thickness direction of the SiGe layer 25 having a high Ge concentration.
Further, in the fifth embodiment, instead of the SiGe layer, the second semiconductor layer may be composed of a SiGeC layer, a GeC layer, or the like having a composition in which C is partially added.

  In addition, the technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, the specific configuration of the light receiving element used in the above embodiment, for example, the description of the material, dimensions, film thickness, shape, manufacturing process, and the like of each layer is merely an example, and various modifications are possible. Examples of a combination of two kinds of semiconductor materials constituting the hetero junction of the photoelectric conversion unit include GaAs / Ge, ZnSe / Ge, ZnSe / GaAs, AlAs / GaAs, GaP / Si, ZnTe / InAs, etc., in addition to Si / SiGe. It can also be used. In the above embodiment, the example of the light receiving element has been described. However, the present invention can be applied to not only the light receiving element but also other photoelectric conversion elements including the light emitting element.

FIG. 2 is a cross-sectional view illustrating the light receiving element according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a light receiving unit of the light receiving element. FIG. 4 is a process cross-sectional view showing the same method of forming the light receiving unit. FIG. 4 is a process cross-sectional view showing the same method of manufacturing the light receiving element. It is a sectional view showing the light sensing portion of the light sensing element of a 2nd embodiment of the present invention. FIG. 4 is a process cross-sectional view showing the same method of forming the light receiving unit. It is a sectional view showing the light sensing portion of the light sensing element of a 3rd embodiment of the present invention. FIG. 4 is a process cross-sectional view showing the same method of forming the light receiving unit. It is a sectional view showing the light sensing portion of the light sensing element of a 4th embodiment of the present invention. It is a sectional view showing a light receiving element of a fifth embodiment of the present invention. FIG. 4 is a cross-sectional view showing a light receiving unit of the light receiving element. FIG. 4 is a process cross-sectional view showing the same method of forming the light receiving unit. It is a sectional view showing an example of the conventional light sensing element. FIG. 4 is a cross-sectional view showing a light receiving unit of the light receiving element. It is a band diagram in a Si / SiGe superlattice structure. FIG. 4 is a diagram illustrating wavelength-absorption characteristics when a subband is formed.

Explanation of reference numerals

4, 24... Si layer (first semiconductor layer), 4a, 4b.
5, 25 ... SiGe layer (second semiconductor layer),
6, 16, 23, 26 ... light receiving unit (photoelectric conversion unit),
15: etching stop layer, 42: groove width adjusting layer, W, W ': groove width,
30: hole, 35: low-Ge-concentration SiGe layer (pre-generation layer), 36: cavity.

Claims (15)

A photoelectric conversion element, comprising: a photoelectric conversion unit having a first semiconductor layer and a second semiconductor layer embedded in a groove formed in the first semiconductor layer. The width of the groove is a critical film thickness that indicates the maximum film thickness at which lattice mismatch does not occur in the second semiconductor layer when the second semiconductor layer is stacked in contact with the first semiconductor layer. The photoelectric conversion element according to claim 1, wherein the photoelectric conversion element is larger than the threshold value and is equal to or less than twice the critical thickness. 3. The device according to claim 1, wherein a plurality of the grooves are formed, and the second semiconductor layers filling the respective grooves are connected to each other over an upper surface of the first semiconductor layer. 4. Photoelectric conversion element. 4. The photoelectric conversion device according to claim 1, further comprising an etching stop layer on a lower surface of the first semiconductor layer, wherein a bottom surface of the groove is formed by the etching stop layer. 5. element. 5. A photoelectric conversion unit comprising the first semiconductor layer and the second semiconductor layer, wherein a plurality of photoelectric conversion units are formed in a stacking direction in a thickness direction of the first semiconductor layer. The photoelectric conversion element according to claim 1. The photoelectric conversion element according to any one of claims 1 to 5, further comprising a groove width adjustment layer between at least a side wall surface of the groove and the second semiconductor layer. The photoelectric conversion element according to claim 1, wherein the first semiconductor layer is made of silicon, and the second semiconductor layer is made of silicon-germanium. 5. The method according to claim 4, wherein the first semiconductor layer is made of silicon, the second semiconductor layer is made of silicon germanium, and the etching stop layer is made of silicon germanium. Photoelectric conversion element. A photoelectric conversion unit is provided in which a plurality of first semiconductor layers made of silicon and a plurality of second semiconductor layers containing silicon and germanium are alternately stacked, and a thickness of the second semiconductor layer is provided. Is larger than a critical film thickness that indicates a maximum film thickness at which no lattice mismatch occurs in the second semiconductor layer, and is equal to or less than twice the critical film thickness. . The second semiconductor layer is formed by crystal growth based on the first semiconductor layers on both sides located at the position sandwiching the second semiconductor layer, and is formed at the center in the thickness direction of the second semiconductor layer. 10. The photoelectric conversion device according to claim 9, wherein a phase shift portion of a crystal lattice caused by a coupling portion of the semiconductor crystal grown from both of the first semiconductor layers is formed. Forming a first semiconductor layer made of a first semiconductor material on a substrate; forming a groove in the first semiconductor layer; and embedding a second semiconductor material in the groove to form a second semiconductor layer. Forming a semiconductor layer of the above. Forming the groove by etching, and before forming the first semiconductor layer, further comprising a step of forming an etching stop layer between the substrate and the first semiconductor layer to prevent the etching. The method for manufacturing a photoelectric conversion element according to claim 11, wherein: After the formation of the groove, the method further includes a step of forming a groove width adjustment layer that covers at least a side wall surface of the groove and narrows the width of the groove, and thereafter, forms the second semiconductor layer. A method for manufacturing a photoelectric conversion element according to claim 11. A photoelectric conversion element including a photoelectric conversion unit having a structure in which a plurality of first semiconductor layers made of Si and a plurality of second semiconductor layers containing at least Si and high-concentration Ge are alternately stacked on a substrate. And forming, as the second semiconductor layer laminated on the first semiconductor layer, a low-Ge-concentration pre-generation layer thicker than the critical thickness of the high-Ge-concentration second semiconductor layer. After laminating and removing at least portions of the plurality of preliminary generation layers corresponding to the photoelectric conversion portions by etching after the lamination, the first semiconductor layer made of Si present at a position sandwiching each of the removed preliminary generation layers is used as a base. Forming a second semiconductor layer having a high Ge concentration thicker than the critical film thickness in the removed portion and filling the removed portion. As the second semiconductor layer having a high Ge concentration, one containing Ge in a range of 50 to 100% is used, and as the preliminary generation layer having a low Ge concentration, one containing Ge in a range of 5 to 40% is used. The method for manufacturing a photoelectric conversion element according to claim 14, wherein:

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