JP2004172405A - Lateral semiconductor component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lateral semiconductor component that has an appropriate blocking characteristic for a high-frequency signal even if microfabrication is applied thereto. <P>SOLUTION: The lateral semiconductor component is provided with a semiconductor substrate 110; a source layer 140 and a drain layer 150 that are formed in a surface area of the semiconductor substrate; a gate electrode 130 that is formed above a channel area between the source layer and the drain layer; insulation films 122, 124, 126, and 128 formed on the source layer or the drain layer; a plurality of contact holes 160 and 180 that are formed in the insulation films so as to reach the source layer and the drain layer; and a source electrode 170 or a drain electrode 190 that includes contact areas 172 and 192 that are connected with the source layer or the drain layer through the contact hole, and are apart from the gate electrode by a first distance and wiring areas 174 and 194 that are formed apart from the gate electrode by a second distance larger than the first distance. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a lateral semiconductor device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, an LDMOS (Lateral Diffused Metal Oxide Semiconductor) has been frequently used in a semiconductor relay circuit or the like which performs a switching operation. In this case, a high-frequency signal is supplied to the source electrode, the drain electrode, and the gate electrode of the LDMOS.
[0003]
FIG. 6 shows a schematic plan view of a typical LDMOS 100. FIG. As shown in FIG. 6, the gate electrode 30 extends on the semiconductor substrate 10. The contact holes 60 and the contact holes 80 are indicated by broken lines in FIG. The contact holes 60 and 80 extend substantially parallel to the direction in which the gate electrode 30 extends. The source electrode 70 and the drain electrode 90 also extend substantially parallel to the direction in which the gate electrode 30 extends.
[0004]
FIG. 7 is a sectional view taken along the line XX shown in FIG. Gate insulating film 20 is formed on the surface of semiconductor substrate 10. Gate electrode 30 is formed on gate insulating film 20. A source diffusion layer 40 and a drain diffusion layer 50 are formed in a surface region of the semiconductor substrate 10. Source electrode 70 is connected to source diffusion layer 40 via contact hole 60. The drain electrode 90 is connected to the drain diffusion layer 50 via the contact hole 80.
[0005]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 62-242365 [Patent Document 2]
JP-A-11-340468
[Problems to be solved by the invention]
In recent years, with the miniaturization of semiconductor elements, the distance Dds between the source electrode 70 and the drain electrode 90 has been reduced. Thereby, the source-drain capacitance Cds increases.
[0007]
Further, as the distance Dds between the source electrode 70 and the drain electrode 90 is reduced, the distance Dgs between the source electrode 70 and the gate electrode 30 and the distance Dgd between the drain electrode 90 and the gate electrode 30 are also reduced. Become. Therefore, the gate-source capacitance Cgs and the gate-drain capacitance Cgd also increase.
[0008]
When the source-drain capacitance Cds increases, the source electrode 70 and the drain electrode 90 are easily connected when a high-frequency signal is applied between the source electrode 70 and the drain electrode 90. When the gate-source capacitance Cgs increases, the gate electrode 30 and the source electrode 70 are easily connected when a high-frequency signal is applied between the gate electrode 30 and the source electrode 70. When the gate-drain capacitance Cgd increases, the source electrode 70 and the drain electrode 90 are easily connected when a high-frequency signal is applied between the gate electrode 30 and the drain electrode 90. In other words, as the capacitances Cds, Cgd, and Cgs increase, the cutoff characteristics of the high-frequency signal in the LDMOS 100 deteriorates.
[0009]
As the LDMOS 100 is miniaturized, the interval Dds, the interval Dgs, and the interval Dgd become narrower, so that the capacitance Cds, the capacitance Cgd, and the capacitance Cgs increase. That is, there is a trade-off relationship between the miniaturization of the LDMOS 100 and the cutoff characteristics of the high-frequency signal.
[0010]
Accordingly, an object of the present invention is to provide a horizontal semiconductor device having a good high-frequency signal cutoff characteristic even when miniaturized.
[0011]
[Means for Solving the Problems]
A lateral semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, a source layer and a drain layer provided in a surface region of the semiconductor substrate, and a channel region between the source layer and the drain layer. A gate electrode, an insulating film provided on the source layer or the drain layer, a plurality of contact holes formed in the insulating film to reach the source layer and the drain layer, A contact region connected to the source layer or the drain layer via a plurality of contact holes and separated from the gate electrode by a first distance, and a second region larger than the first distance from the gate electrode A source electrode or a drain electrode including a separately formed wiring region.
[0012]
Preferably, the source electrode and the drain electrode are formed in a comb shape, and the plurality of contact regions protrude from the wiring region toward the gate electrode.
[0013]
Preferably, the contact region included in the source electrode and the contact region included in the drain electrode alternately protrude toward the gate electrode.
[0014]
Preferably, the contact region of the source electrode projects substantially toward the middle of the contact region adjacent to the drain electrode,
The contact region of the drain electrode protrudes substantially toward the center between two adjacent contact regions of the source electrode.
[0015]
Preferably, the contact region is formed in an arc shape toward the gate electrode when viewed from above a surface of the semiconductor substrate.
[0016]
Preferably, the plurality of contact holes are formed in an arc shape toward the gate electrode when viewed from above a surface of the semiconductor substrate.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. Even if the conductivity type of each component in the embodiment is switched between p-type and n-type, the effect of the present invention is not lost.
[0018]
FIG. 1 is a schematic enlarged plan view of an LDMOS 200 according to an embodiment of the present invention. As shown in FIG. 1, the gate electrode 130 extends on the semiconductor substrate 110. The contact holes 160 and 180 are indicated by broken lines in FIG. A plurality of contact holes 160 and a plurality of contact holes 180 are formed, and are arranged discretely substantially parallel to the direction in which the gate electrode 30 extends.
[0019]
The source electrode 170 has a comb shape as shown in FIG. 1, and includes a contact region 172 and a wiring region 174. The contact region 172 projects from the wiring region 174 toward the gate electrode 130. The contact region 172 is connected to the source diffusion layer 140 (see FIG. 3) formed in the surface region of the semiconductor substrate 110 via a contact hole 160. The wiring region 174 extends substantially parallel to the direction in which the gate electrode 130 extends.
[0020]
Similarly to the source electrode 170, the drain electrode 190 has a comb shape, and includes a contact region 192 and a wiring region 194. The contact region 192 protrudes from the wiring region 194 toward the gate electrode 130. The contact region 192 is connected via a contact hole 180 to a drain diffusion layer 150 (see FIG. 3) formed in a surface region of the semiconductor substrate 110. The wiring region 194 extends substantially parallel to the direction in which the gate electrode 130 extends.
[0021]
The source electrode 170 is arranged to face the drain electrode 190 with the gate electrode 130 interposed therebetween. Although the source electrode 170 and the drain electrode 190 have symmetric shapes, the contact regions 172 and the contact regions 192 included therein alternately project toward the gate electrode 130. In other words, the contact region 172 and the contact region 192 may alternately protrude toward the gate electrode 130. The contact region 172 is located substantially in the middle between two contact regions 192 adjacent to each other. The contact region 192 is located substantially in the middle between two contact regions 172 adjacent to each other. That is, the source electrode 170 and the drain electrode 190 face each other, and the contact region 172 and the contact region 192 may be shifted by a half pitch.
[0022]
Contact holes 160 and 180 have a semicircular shape toward gate electrode 130. Contact regions 172 and 192 are also formed in an arc shape toward gate electrode 130 according to contact holes 160 and 180. These semicircular curvatures may be set arbitrarily.
[0023]
FIG. 2 is an enlarged plan view of the LDMOS 200 shown in FIG. FIG. 3 is a sectional view taken along line AA shown in FIG. FIG. 4 is a sectional view taken along line BB shown in FIG. FIG. 5 is a sectional view taken along the line CC shown in FIG.
[0024]
As shown in FIG. 3, the semiconductor substrate 110 is made of a P ⁻ type semiconductor. A gate insulating film 120 is formed on the surface of the semiconductor substrate 110. The gate electrode 130 is formed on the gate insulating film 120.
[0025]
An N ⁻ type electric field relaxation layer 152 is formed in a surface region on the drain side of the semiconductor substrate 110. An N ⁺ type drain layer 150 is formed inside the electric field relaxation layer 152 in the surface region of the semiconductor substrate 110. The drain layer 150 is electrically connected to the drain electrode 190 via the contact hole 180.
[0026]
A P-type lateral diffusion layer 142 and a source layer 140 are formed in a source-side surface region of the semiconductor substrate 110. The source layer 140 is formed inside the lateral diffusion layer 142 in the surface region of the semiconductor substrate 110.
[0027]
Over the gate electrode 120, an interlayer insulating film 124 and an interlayer insulating film 126 are provided. On the source layer 140 and the drain layer 150, an interlayer insulating film 122 is provided. Further, a protective film 128 is formed on the interlayer insulating film 126. The source electrode 170 and the drain electrode 190 are formed on the protective film 128. Note that, as shown in FIG. 2, the AA line does not cross the contact hole 160, so that the contact region 172 does not appear in FIG.
[0028]
The semiconductor substrate 110 is typically a silicon single crystal, but may be a semiconductor containing gallium. Gate electrode 130 is typically doped polysilicon, but may be a gate made of metal. The source electrode 170 and the drain electrode 190 are typically aluminum, but may be a metal containing copper. The gate insulating film 120, the interlayer insulating films 122, 124, 126, and the protective film 128 are typically silicon oxide films, but may be silicon nitride films or the like.
[0029]
The distance between contact hole 180 and gate electrode 130 is equal to the distance between contact hole 80 and gate electrode 30 shown in FIG. Therefore, the distance Dgd1 between the gate electrode 130 and the drain electrode 190 shown in FIG. 3 is equal to the distance Dgd shown in FIG.
[0030]
On the other hand, since the source electrode 170 is not connected to the source layer 140 in the cross-sectional view shown in FIG. 3, the distance Dds1 between the source electrode 170 and the drain electrode 190 is larger than the distance Dds shown in FIG. As a result, the capacitance Cds between the source and the drain of the LDMOS 200 becomes smaller than that of the conventional example. Distance Dgs1 between source electrode 170 and gate electrode 130 is larger than distance Dgs shown in FIG. As a result, the capacitance Cgs between the source and the gate of the LDMOS 200 becomes smaller than that of the conventional example.
[0031]
In the cross-sectional view along the line BB shown in FIG. 2, there is a contact hole 160 as shown in FIG. Therefore, the distance between contact hole 160 and gate electrode 130 is equal to the distance between contact hole 60 and gate electrode 30 shown in FIG. Therefore, the distance Dgs2 between the gate electrode 130 and the source electrode 170 shown in FIG. 4 is equal to the distance Dgs shown in FIG.
[0032]
On the other hand, in FIG. 4, the contact hole 180 does not appear. Since the drain electrode 190 is not connected to the drain layer 150 in the cross-sectional view shown in FIG. 4, the distance Dds2 between the source electrode 170 and the drain electrode 190 is larger than the distance Dds shown in FIG. As a result, the capacitance Cds between the source and the drain of the LDMOS 200 becomes smaller than that of the conventional example. The distance Dgd2 between the drain electrode 190 and the gate electrode 130 is larger than the distance Dgd shown in FIG. As a result, the capacitance Cgd between the drain and the gate of the LDMOS 200 becomes smaller than that of the conventional example.
[0033]
The distance Dds2 may be equal to the distance Dds1. This facilitates designing of a mask for forming the source electrode 170 and the drain electrode 190.
[0034]
The source electrode 170 connects the source layer 140 and the P ⁺ type ground layer 144.
[0035]
In the cross-sectional view taken along the line CC shown in FIG. 2, neither of the contact holes 160 and 180 appear as shown in FIG. Therefore, the distance Dds3 between the source electrode 170 and the drain electrode 190 is significantly larger than the distance Dds shown in FIG. The distance Dds3 is even larger than the distance Dds1 shown in FIG. 3 and the distance Dds2 shown in FIG. As a result, the capacitance Cgd between the drain and the gate of the LDMOS 200 becomes smaller than that of the conventional example.
[0036]
The distance Dgd3 between the drain electrode 190 and the gate electrode 130 is larger than the distance Dgd shown in FIG. As a result, the capacitance Cds between the drain and the gate of the LDMOS 200 becomes smaller than that of the conventional example.
[0037]
Further, distance Dgs3 between source electrode 170 and gate electrode 130 is greater than distance Dgs shown in FIG. As a result, the capacitance Cgs between the source and the gate of the LDMOS 200 becomes smaller than that of the conventional example. As a result, the capacitance Cgs between the source and the gate of the LDMOS 200 becomes smaller than that of the conventional example.
[0038]
Note that the distance Dgd3 is equal to the distance Dgd2 shown in FIG. The distance Dgs3 is equal to the distance Dgd1 shown in FIG. This facilitates designing of a mask for forming the source electrode 170 and the drain electrode 190.
[0039]
Each electrode of the LDMOS 200 is connected in parallel with each electrode in the cross-sectional area along the line AA, each electrode in the cross-sectional area along the line BB, and each electrode in the cross-sectional area along the line CC. Can be considered to be formed. When considered in this way, the capacitance of each electrode of the LDMOS 200 is the capacitance between each electrode in the cross-sectional area along the line AA, the capacitance between each electrode in the cross-sectional area along the line BB, and C- This is the total capacitance between the electrodes in the cross-sectional area along the line C. Therefore, in the LDMOS 200, the source-drain capacitance Cds, the source-gate capacitance Cgs, and the drain-gate capacitance Cgd are all smaller than the conventional LDMOS 100. As a result, even if the LDMOS 200 according to the present embodiment is miniaturized, the cutoff characteristic of the high-frequency signal is improved as compared with the conventional example.
[0040]
According to the present embodiment, the contact area between source electrode 170 and source layer 140 and the contact area between drain electrode 190 and drain layer 150 are smaller than in the conventional example. Therefore, there is a concern that the ON resistance Ron of the LDMOS 200 may increase. However, the problem can be solved by sufficiently increasing the impurity concentration of the source layer 140 and the drain layer 150.
[0041]
Further, in the conventional example, when the distance between the source electrode 70 and the drain electrode 90 is increased, the distance between the contact hole 60 and the contact hole 80 also needs to be increased. However, according to the present embodiment, source electrode 170 and drain electrode 190 are comb-shaped, and contact region 172 and contact region 192 are shifted by a half pitch. Therefore, even if the distance between the wiring region 174 of the source electrode 170 and the wiring region 194 of the drain electrode 190 is increased, the distance between the contact holes 160 and 180 does not need to be changed. Therefore, even if the distance between the wirings between the source electrode and the drain electrode is increased, an increase in the on-resistance Ron is prevented.
[0042]
Contact region 172 and contact region 192 are shifted by a half pitch. That is, the contact regions 172 and the contact regions 192 project alternately. Therefore, even in the portions where the contact regions 192 and 172 protrude, the distances Dds1 and Dds2 can be made larger than before.
[0043]
Further, the contact region 172 is located substantially in the middle between two contact regions 192 adjacent to each other, and the contact region 192 is located almost in the middle between two contact regions 172 adjacent to each other. Thus, in the process of forming the source electrode 170 and the drain electrode 190, the distances Dds1 and Dds2 can be kept large even if the alignment of photolithography is shifted to some extent in the vertical direction in FIG.
[0044]
Further, according to the present embodiment, contact region 172 is formed in an arc shape toward gate electrode 130. Accordingly, the distance from contact region 172 to gate electrode 130 or drain electrode 190 can be made longer than when contact region 172 is formed in a rectangular shape. That is, the minimum distance Dgs2 from the contact region 172 to the gate electrode 130 or the minimum distance Dds2 from the contact region 172 to the drain electrode 190 is reduced.
[0045]
Similarly, contact region 192 is formed in an arc shape toward gate electrode 130. Accordingly, the distance from contact region 192 to gate electrode 130 or source electrode 170 can be increased as compared with the case where contact region 192 is formed in a rectangular shape. That is, the minimum distance Dgd1 from the contact region 192 to the gate electrode 130 or the minimum distance Dds1 from the contact region 192 to the source electrode 170 is reduced.
[0046]
By reducing the capacitance between the gate electrode 130, the source electrode 170, and the drain electrode 190, these electrodes are less likely to be short-circuited to a high-frequency signal.
[0047]
Japanese Patent Application Laid-Open No. 62-242365 discloses a MOS type output circuit element having a structure in which a source diffusion layer and a drain diffusion layer enter each other in a comb-like manner and surrounds the periphery of the drain diffusion layer with a gate electrode. .
[0048]
However, this configuration does not consider the capacitance between the electrodes. Rather, by adopting such a configuration, the distance between the electrodes is reduced, and as a result, the capacitance between the electrodes is increased.
[0049]
Japanese Patent Application Laid-Open No. H11-340468 discloses an LDMOS having a substantially comb-shaped drain region. According to this configuration, the output capacitance can be reduced by reducing the area of the drain electrode.
[0050]
However, in this configuration, since the distance between the electrodes is invariable, a measure for reducing the output capacitance is essentially different from that of the present embodiment.
[0051]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to the horizontal semiconductor element according to this invention, the cutoff characteristic of a high frequency signal is favorable even if it is miniaturized.
[Brief description of the drawings]
FIG. 1 is a schematic enlarged plan view of an LDMOS 200 according to an embodiment of the present invention.
FIG. 2 is an enlarged plan view of the LDMOS 200 shown in FIG. 1;
FIG. 3 is a sectional view taken along the line AA shown in FIG. 2;
FIG. 4 is a sectional view taken along the line BB shown in FIG. 2;
FIG. 5 is a sectional view taken along the line CC shown in FIG. 2;
FIG. 6 is a schematic plan view of a typical LDMOS 100.
FIG. 7 is a sectional view taken along the line XX shown in FIG. 6;
[Explanation of symbols]
200 LDMOS
Reference Signs List 110 semiconductor substrate 120 gate insulating films 122, 124, 126 interlayer insulating film 128 protective film 130 gate electrode 140 source layer 142 lateral diffusion layer 150 drain layer 160, 180 contact hole 170 source electrode 172 contact region 174 wiring region 190 drain electrode 192 Contact region 194 Wiring region Cgs Source-gate capacitance Cds Source-drain capacitance Cgd Drain-gate capacitance

Claims (6)

A semiconductor substrate;
A source layer and a drain layer provided in a surface region of the semiconductor substrate;
A gate electrode formed above a channel region between the source layer and the drain layer;
An insulating film provided on the source layer or the drain layer,
A plurality of contact holes formed in the insulating film to reach the source layer and the drain layer;
A contact region connected to the source layer or the drain layer via the plurality of contact holes and separated from the gate electrode by a first distance; and a second distance larger than the first distance from the gate electrode. A lateral semiconductor element including a source electrode or a drain electrode including a wiring region formed only apart from each other. The source electrode and the drain electrode are formed in a comb shape,
2. The lateral semiconductor device according to claim 1, wherein the plurality of contact regions protrude from the wiring region toward the gate electrode. The lateral semiconductor device according to claim 1, wherein the contact region included in the source electrode and the contact region included in the drain electrode alternately protrude toward the gate electrode. 4. . The contact region of the source electrode projects substantially toward the middle of the contact region adjacent to the drain electrode,
4. The lateral semiconductor device according to claim 3, wherein the contact region of the drain electrode protrudes toward substantially the middle between two contact regions adjacent to the source electrode. 5. 2. The lateral semiconductor device according to claim 1, wherein the contact region is formed in an arc shape toward the gate electrode when viewed from above a surface of the semiconductor substrate. 3. 6. The lateral semiconductor device according to claim 5, wherein the plurality of contact holes are formed in an arc shape toward the gate electrode when viewed from above a surface of the semiconductor substrate.

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