JP2004172336A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring structure in which a cap film that does not worsen wiring delays is formed by using a cap film preventing the rise of wiring resistances and the diffusion of copper and consisting of an insulating film having an oxidation resistance and a hydrofluoric acid resistance on wiring at the necessary minimum. <P>SOLUTION: A method of manufacturing a semiconductor device includes steps of: forming a copper oxide film 21 only on the surface of wiring 15 embedded in an interlayer insulating film 12 and composed of copper or a copper alloy; selectively removing the copper oxide film 21; and forming the cap film 31 which prevents the diffusion of copper only on areas from which the copper oxide film 21 is removed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and more particularly to a method of manufacturing a semiconductor device suitable for forming a multilayer wiring by using a trench wiring technique such as a damascene method and a dual damascene method, and a method of manufacturing the same. And a semiconductor device manufactured by the same.
[0002]
[Prior art]
Copper (Cu) wiring provides lower resistance, lower capacitance, and higher reliability than aluminum (Al) alloy wiring, and thus is becoming increasingly important in microelements in which circuit delay due to wiring parasitic resistance and parasitic capacitance is dominant. Have been. Generally, copper is not easy to dry-etch unlike aluminum-based alloys, and therefore, a trench wiring technique such as a damascene method is widely used to form copper wiring. The groove wiring technique is to form a groove for forming a predetermined wiring in an interlayer insulating film such as a silicon oxide (SiO ₂ ) film in advance, bury a wiring material in the groove, and then perform a chemical mechanical polishing of the surplus wiring material. This is a wiring forming process formed by removing by a CMP (Chemical Mechanical Polishing) method or the like.
[0003]
Further, a trench wiring technique called a dual damascene method has been proposed in which after forming a connection hole (via hole) and a wiring portion (trench), a wiring material is buried in a lump and excess wiring material is removed. For example, see Patent Document 1.) This groove wiring technique is effective in reducing the number of processes and manufacturing costs.
[0004]
Copper wiring is generally used in a multilayered form, but since there is no barrier metal on the copper surface immediately after CMP for preventing diffusion to the interlayer insulating film, it functions as a copper diffusion preventing layer before forming an upper wiring. A cap film is formed on the entire surface. Since copper is easily oxidized at a low temperature of 150 ° C. in an atmosphere containing oxygen, a silicon nitride film (SiN) containing no oxygen or a silicon carbide film (SiC) is usually used as the cap film. Have been.
[0005]
However, since silicon nitride and silicon carbide have a higher dielectric constant than silicon oxide, the effective dielectric constant of a semiconductor device is opposite despite the fact that copper is used as the main material of the wiring to lower the wiring resistance. As a whole, a large improvement in the RC delay (resistance delay and capacitance delay) of the wiring cannot be expected. Therefore, as a method that is advantageous for RC delay without using a cap film made of a silicon nitride film or a silicon carbide film that is disadvantageous for RC delay, a method of selectively covering the copper surface after CMP with cobalt tungsten phosphorus (CoWP) is available. Used. As a method for selectively forming a CoWP film on a copper surface, there is an electroless plating method, and a method for forming CoWP using a copper surface as a catalyst is known. There is also known a method in which a copper surface is subjected to palladium (Pd) substitution plating, and electroless plating is performed using the substituted palladium as a catalyst core.
[0006]
[Patent Document 1]
JP-A-11-45887 (page 3, FIG. 1)
[0007]
[Problems to be solved by the invention]
However, although the CoWP film as the cap film functions as a copper diffusion preventing layer, it has poor oxidation resistance and needs to be formed to a certain thickness, so that the wiring resistance is increased and the overall resistance is increased. On the contrary, the wiring delay worsens. Alternatively, there is a proposal that a cap film made of an insulating film such as silicon carbide or silicon nitride is formed thinly after CoWP is formed in order to suppress an increase in wiring resistance and further improve oxidation resistance and hydrofluoric acid resistance. However, the use of an insulating film having a high dielectric constant, such as silicon carbide or silicon nitride, remains the same, so that the problem that the wiring delay deteriorates remains.
[0008]
[Means for Solving the Problems]
The present invention is a method for manufacturing a semiconductor device and a semiconductor device which have been made to solve the above problems.
[0009]
The method of manufacturing a semiconductor device according to the present invention includes a step of forming a copper oxide film only on the surface of a wiring made of copper or a copper alloy embedded in an insulating film, a step of removing the copper oxide film, and a step of removing the copper oxide film. Forming a cap film for preventing the diffusion of copper only in the region from which copper has been removed.
[0010]
In the method of manufacturing a semiconductor device, a copper oxide film is formed only on the surface of the wiring, and after removing only the copper oxide film, a cap film for preventing diffusion of copper is formed only on the removed portion. The cap film can be formed only on the minimum part. Therefore, the cap film has oxidation resistance and hydrofluoric acid resistance without significantly increasing the capacitance between wirings and without significantly increasing wiring resistance. It becomes possible to use silicon nitride. Therefore, as compared with the case where a cap film is formed on the entire surface, the capacity of the cap film for preventing the diffusion of copper, which has been one of the major causes of RC delay in the copper wiring structure, is reduced, and the effective efficiency of the entire semiconductor device is reduced. The dielectric constant is reduced.
[0011]
The semiconductor device of the present invention has a cap film for preventing copper diffusion only in a region where the copper oxide film is removed after forming a copper oxide film only on the surface of the wiring made of copper or copper alloy embedded in the insulating film. It is provided.
[0012]
In the above-described semiconductor device, a copper oxide film is formed only on the surface of the wiring made of copper or copper alloy embedded in the insulating film, and then a cap film for preventing diffusion of copper only in a region where the copper oxide film is removed is provided. For this reason, the cap film is formed only on the minimum necessary portion. Therefore, the cap film has oxidation resistance and hydrofluoric acid resistance without significantly increasing the capacitance between wirings and without significantly increasing wiring resistance. It becomes possible to use silicon nitride. Therefore, as compared with the structure in which the cap film is formed not only on the wiring but also on the interlayer insulating film as in the conventional semiconductor device, it is one of the major causes of the RC delay in the copper wiring structure. The capacity of the cap film for preventing the diffusion of copper is reduced, and the effective dielectric constant of the entire semiconductor device is reduced.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
One embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the schematic cross-sectional view of FIG.
[0014]
As shown in FIG. 1A, for example, an interlayer insulating film 12 made of silicon oxide (SiO ₂ ) is formed on a substrate 11 on which devices are formed. Next, a groove 13 is formed in the interlayer insulating film 12 by a technique for forming a normal groove wiring, and copper (for example) is formed in the groove 13 via a barrier layer 14 formed of, for example, a tantalum nitride (TaN) film. The wiring 15 made of Cu) is formed. The base 11 refers to, for example, a substrate on which devices such as transistors are formed. Note that the device is not shown in the figure and is handled as one layer of the base 11.
[0015]
Next, as shown in FIG. 1B, only the surface of the wiring 15 is oxidized to form a copper oxide film 21 on the wiring 15. For example, the exposed surface of the wiring 15 is exposed to an oxygen plasma atmosphere to oxidize only the surface of the wiring 15, and a copper oxide film 21 is formed on the wiring 15. The copper oxidation rate at this time is not particularly limited, but is preferably a rate of 20 nm / min or less in order to improve the uniformity of the copper oxide film 21 and to suppress the peeling of the copper oxide film 21. Oxidation is good. The copper oxide film 21 can be made as thin as the precision of the flattening step of the cap film to be performed later allows. However, since the cap film needs to have a function of preventing copper diffusion, a film of 5 nm or more is required. Thickness is required. On the other hand, the copper oxide film 21 is desirably formed to a thickness of 50 nm or less in order not to reduce the removal accuracy and the effect of reducing the wiring capacitance. Therefore, the copper oxide film 21 is desirably formed to a thickness of 5 nm or more and 50 nm or less.
[0016]
Next, as shown in FIG. 1C, the copper oxide film 21 is selectively etched with respect to the interlayer insulating film 12, the wiring 15 and the barrier layer 14 by wet etching using, for example, 10% oxalic acid. Then, the copper oxide film 21 on the wiring 15 is completely removed. Here, the etching solution for removing the copper oxide film 21 is not limited to 10% oxalic acid, but is, for example, a 10% hydrochloric acid / 10% H ₂ O ₂ aqueous solution, a 10% nitric acid aqueous solution, a 10% nitric acid / 10% H solution. There is no problem with ₂ O ₂ aqueous solution. In consideration of the etching accuracy, a single solution such as 10% oxalic acid, 10% hydrochloric acid, and 10% nitric acid is more preferable. Further, the concentration of each of the above etching solutions is not limited to 10%, and can be appropriately selected. As a result of the wet etching, a groove 22 is formed on the wiring 15.
[0017]
After performing post-processing (for example, cleaning) after the wet etching, as shown in FIG. 1D, a groove formed by removing the copper oxide film 21 (see FIG. 1C). A cap film 31 of a copper wiring is formed on the interlayer insulating film 12 by, for example, an SiN film so as to fill the interlayer insulating film 22. At this time, the cap film 31 needs to be formed thicker than the depth of the groove 22 (that is, equivalent to the thickness of the copper oxide film 21). Further, if the cap film 31 can be left in the groove 22 at a thickness of 5 nm or more after the next flattening process, there is no upper limit to the thickness of the cap film 31. -In consideration of cost, the thickness is preferably 100 nm or less.
[0018]
After that, the surplus cap film 31 on the interlayer insulating film 12 is removed by, for example, chemical mechanical polishing (hereinafter, referred to as CMP; CMP stands for Chemical Mechanical Polishing). Here, the polishing amount of the cap film 31 is not particularly limited. However, in order to prevent copper of the wiring 15 from diffusing into the interlayer insulating film 12, the cap film 31 is formed on the wiring 15 to have a thickness of 5 nm or more. Need to leave. Therefore, the cap film 31 is formed on the wiring 15 to a thickness of 5 nm or more and 50 nm or less corresponding to the depth of the groove 22. In this manner, as shown in FIG. 1 (5), the formation of the first layer wiring in which the cap film 31 for selectively preventing the diffusion of copper is formed on the wiring 15 is completed.
[0019]
Thereafter, although not shown, the next interlayer insulating film is formed of, for example, a silicon oxide (SiO ₂ ) film, and the so-called dual damascene method disclosed in Japanese Patent Application No. 10-143914 (for example, a trench wiring). By the wiring forming method for simultaneously forming plugs connected to the lower part of the trench wiring, the steps described with reference to FIG. 1 may be repeated by the number of layers required for forming the copper wiring.
[0020]
In the above embodiment, the formation of the copper oxide film 21 may be performed as follows. That is, for example, the surface of the wiring 15 is brought into contact with a hydrogen peroxide (H ₂ O ₂ ) aqueous solution to form the copper oxide film 15 on the surface of the wiring 15. At this time, the concentration of the aqueous hydrogen peroxide solution is preferably such that copper is oxidized at a rate of 20 nm / min or less in order to improve the uniformity of the copper oxide film 21 and to suppress peeling of the copper oxide film 21. It is good to set to density.
[0021]
Thus, even in the case of oxidation using an aqueous hydrogen peroxide solution, the copper oxide film 21 needs to have a thickness of 5 nm or more in order to form a cap film having a function of preventing diffusion of copper. In order not to reduce the removal accuracy of the copper oxide film 21 and the effect of reducing the wiring capacitance, it is desirable that the thickness be 50 nm or less. Therefore, the copper oxide film 21 is desirably formed to a thickness of 5 nm or more and 50 nm or less. The chemical solution used to oxidize the surface of the copper wiring 15 is not limited to the aqueous hydrogen peroxide solution, but any chemical solution (with any concentration) that satisfies the copper oxidation rate and the thickness of the copper oxide film 21 is used. Include).
[0022]
Further, the combination of the interlayer insulating film 12 and the cap film 31 is not limited to silicon oxide (SiO ₂ ) and silicon nitride (SiN), respectively, as described in the above-described embodiment. Is applied to an interlayer insulating film using a so-called low dielectric constant insulating film such as a fluorine-added silicon oxide film (FSG), hydrogen silsequiosane (HSQ), silicon carbide oxide film (SiOC), and polyallyl ether (PAE). The cap film 31 can be applied to any insulating film such as silicon nitride or silicon carbide that does not contain oxygen for the purpose of preventing copper from being diffused or oxidized, which is generally used after chemical mechanical polishing of copper. However, it is necessary to employ a material having resistance to a chemical used when the copper oxide film 21 is removed by wet etching as the interlayer insulating film 12.
[0023]
In the method of manufacturing the semiconductor device, the copper oxide film 21 is formed only on the surface of the wiring 15, and after removing only the copper oxide film 21, the cap film 31 for preventing diffusion of copper is formed only on the removed portion. For this reason, the cap film 31 can be formed only in the minimum necessary portion. Therefore, without significantly increasing the capacitance between wirings and without significantly increasing wiring resistance, the cap film 31 has oxidation resistance and hydrofluoric acid resistance, and is also excellent in copper diffusion prevention function. Or silicon nitride. Therefore, as compared with the prior art in which a cap film is formed on the entire surface, the capacitance of the cap film 31 for preventing the diffusion of copper, which has been one of the major causes of RC delay in the copper wiring structure, is reduced. Is reduced.
[0024]
Next, an embodiment of the semiconductor device of the present invention will be described with reference to the schematic configuration sectional view of FIG. The semiconductor device described here is formed by the manufacturing method described with reference to FIG.
[0025]
As shown in FIG. 2, for example, an interlayer insulating film 12 made of silicon oxide (SiO ₂ ) is formed on a substrate 11 on which devices are formed. A groove 13 is formed in the interlayer insulating film 12 by a technique for forming a normal groove wiring. In the groove 13, for example, a barrier layer 14 made of a tantalum nitride (TaN) film and a copper ( A wiring 15 made of Cu) is formed. Here, the base 11 refers to a substrate on which devices such as transistors are formed. Note that the device is not shown in the figure and is handled as one layer of the base 11.
[0026]
On the wiring 15, only the surface of the wiring 15 is oxidized by, for example, exposure to oxygen plasma to form a copper oxide film. Then, the copper oxide film is removed, and copper is diffused only in the removed portion. The cap film 31 to be prevented is formed of, for example, silicon carbide, silicon nitride, or silicon nitride carbide. The method for forming the copper oxide film is not limited to a method using oxygen plasma, but may be formed by oxidation using an oxidizing agent such as an aqueous hydrogen peroxide solution. The cap film 31 needs to have a function of preventing the diffusion of copper, and therefore needs to have a thickness of 5 nm or more. In order not to reduce the effect of reducing the wiring capacitance, the cap film 31 has a thickness of 50 nm or less. It is desirable to be formed to a film thickness. Therefore, the copper oxide film is formed to have a thickness of 5 nm or more and 50 nm or less.
[0027]
The cap film 31 is formed so as to be flush with the surface of the interlayer insulating film 12 and is flattened. As described above, the first-layer wiring in which the cap film 31 for selectively preventing the diffusion of copper is formed on the wiring 15 is formed.
[0028]
Furthermore, an interlayer insulating film 42 is formed on the interlayer insulating film 12 so as to cover the cap film 31, for example, with a silicon oxide (SiO ₂ ) film. In the interlayer insulating film 42, a wiring 45 and a plug 46 that penetrates the wiring 45 and the cap film 31 and connects the wiring 15 to each other by, for example, a so-called dual damascene method (a groove wiring and a connection below the groove wiring). (A wiring forming method for simultaneously forming plugs to be formed). The wiring 45 and the plug 46 are formed of copper or a copper alloy via a barrier layer 47 for preventing the diffusion of copper into the wiring groove 43 and the connection hole 44, similarly to the wiring 15 described above. Similarly to the wiring 15, the wiring 45 is formed on the wiring 45 by oxidizing the upper part of the wiring 45 to form a copper oxide film. Only in a region where the copper oxide film is selectively removed, silicon carbide, A cap film 61 is formed to prevent diffusion of copper containing no oxygen, such as silicon or silicon nitride carbide, and to prevent oxidation of copper.
[0029]
Further, the combination of the interlayer insulating film 42 and the cap film 61 is limited to silicon oxide (SiO ₂ ) and silicon nitride (SiN), respectively, similarly to the combination of the interlayer insulating film 12 and the cap film 31 described above. However, a so-called low dielectric constant insulating film such as a fluorine-doped silicon oxide film (FSG), hydrogen silsequiosane (HSQ), silicon carbide oxide film (SiOC), and polyallyl ether (PAE) is used for the interlayer insulating film 42. For the cap film 31, an insulating film containing no oxygen, such as silicon nitride or silicon carbide, for preventing copper diffusion and oxidation generally used after chemical mechanical polishing of copper can be used.
[0030]
In the present semiconductor device, a copper oxide film is formed only on the surfaces of the wirings 15 and 45 made of copper or copper alloy embedded in the interlayer insulating films 12 and 42, and then diffusion of copper is performed only in a region where the copper oxide film is removed. Since the cap films 31 and 61 for prevention are provided, the cap films 31 and 61 are formed only in the minimum necessary portions. For this reason, the cap films 31 and 61 have oxidation resistance and hydrofluoric acid resistance without significantly increasing the capacitance between wirings and without significantly increasing wiring resistance, and also have an excellent copper diffusion preventing function. Materials such as silicon carbide, silicon nitride, and silicon carbonitride can be used. Therefore, as compared with the structure in which the cap film is formed not only on the wiring but also on the interlayer insulating film as in the conventional semiconductor device, it is one of the major causes of the RC delay in the copper wiring structure. The capacity of the cap film for preventing the diffusion of copper is reduced, and the effective dielectric constant of the entire semiconductor device is reduced.
[0031]
In the embodiment described with reference to FIG. 2, the wiring of the two-layer structure is shown. However, the structure of the present invention can be applied to a single-layer wiring, and the present invention can be applied to a multilayer wiring of three or more layers. Configuration can be applied.
[0032]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device of the present invention, since the cap film can be formed only on the minimum necessary portion on the wiring, the inter-wiring capacitance is not significantly increased, and It is possible to use silicon carbide or silicon nitride, which has an oxidation resistance and a hydrofluoric acid resistance, and is also excellent in a copper diffusion preventing function, without significantly increasing the wiring resistance. Therefore, compared to the conventional technique of forming a cap film on the entire surface, the capacity of the cap film for preventing the diffusion of copper, which has been one of the major causes of RC delay in the copper wiring structure, can be reduced. The overall effective permittivity of the device can be reduced. Therefore, it becomes possible to manufacture a semiconductor device having high-performance multilayer wiring.
[0033]
According to the semiconductor device of the present invention, since the cap film is formed only on the minimum necessary portion on the wiring since the semiconductor device is formed by the method of manufacturing the semiconductor device of the present invention, the capacitance between the wirings is significantly increased. It is possible to use silicon carbide or silicon nitride which has an oxidation resistance and a hydrofluoric acid resistance, and is also excellent in a copper diffusion preventing function, without causing the wiring resistance to be greatly increased without causing the resistance. For this reason, compared with the conventional technology in which a cap film is formed on the entire surface, it is possible to reduce the capacitance of the cap film that prevents copper diffusion, which has been one of the major causes of RC delay in the copper wiring structure, The effective dielectric constant of the entire semiconductor device can be reduced. Therefore, a semiconductor device having high-performance multilayer wiring is obtained.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing one embodiment of a method for manufacturing a semiconductor device of the present invention.
FIG. 2 is a schematic sectional view showing one embodiment of a semiconductor device of the present invention.
[Explanation of symbols]
12 interlayer insulating film, 15 wiring, 21 copper oxide film, 31 cap film

Claims (6)

Forming a copper oxide film only on the surface of the wiring made of copper or copper alloy embedded in the insulating film,
Removing the copper oxide film;
Forming a cap film for preventing diffusion of copper only in a region where the copper oxide film has been removed. 2. The method according to claim 1, wherein the copper oxide film is formed by oxidizing the wiring surface at an oxidation rate of 20 nm / min or less. 2. The method according to claim 1, wherein the groove formed by removing the copper oxide film has a depth of 5 nm or more and 50 nm or less. A copper oxide film is formed only on the surface of a wiring made of copper or a copper alloy embedded in an insulating film, and then a cap film for preventing diffusion of copper is provided only in a region where the copper oxide film is removed. Semiconductor device. 5. The semiconductor device according to claim 4, wherein the copper oxide film is formed by oxidizing the wiring surface at an oxidation rate of 20 nm / min or less. The semiconductor device according to claim 4, wherein the groove formed by removing the copper oxide film has a depth of 5 nm or more and 50 nm or less.

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