JP2004172222A - Electronic device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic device which will hardly have arcing. <P>SOLUTION: On a substrate W, at least a mask layer 5, a dielectric layer 4, and a conductive layer 3 are formed in this order from the top. The dielectric layer 4 is plasma-etched according to a pattern of the mask layer 5 to expose the conductive layer 3. Part or all of the conductive layer 3 is formed of a high conductive material having the conductivity of Ti or higher. The conductive layer 3 has at least a first portion 3a and a second portion 3b which are electrically insulated from each other. An etching section 6 wherein the first portion 3a is exposed has an aspect ration of ≥4.5, being set higher than that of an etching section 7 wherein the second portion 3b is exposed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electronic device having a predetermined pattern formed on a substrate such as a semiconductor substrate by plasma etching, and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor device manufacturing process, plasma etching for etching a semiconductor wafer (hereinafter, simply referred to as a wafer), which is a substrate to be processed, with plasma is frequently used. Various types of plasma etching apparatuses are used, and among them, a capacitively coupled parallel plate plasma processing apparatus is mainly used. Further, a permanent magnet is disposed in such a capacitively coupled parallel plate plasma processing apparatus, and a magnetic field formed by the permanent magnet is applied horizontally to the semiconductor wafer, and a high-frequency electric field perpendicular to the semiconductor wafer is applied. A magnetron plasma processing apparatus that performs etching with extremely high efficiency using the drift motion of electrons generated at the time is also used. (For example, Patent Documents 1 and 2).
[0003]
[Patent Document 1]
JP-A-6-20794
[Patent Document 2]
JP-A-8-124912
[0004]
[Problems to be solved by the invention]
By the way, at the time of etching, the portion of the resist film near the plasma sheath is negatively charged, so that the electron from the plasma has a larger momentum in the lateral direction, and a portion where a hole having a large aspect ratio is formed. In this case, electrons hardly reach the hole, but positive ions are accelerated by the plasma sheath and reach the hole, so that the bottom of the hole becomes positively charged. On the other hand, electrons and ions reach the space and the trench where no hole is formed without difficulty. As a result, a large potential difference occurs between them. This is called a shading effect. In addition, the DC potential Vdc between the plasma and the plasma differs depending on the portion on the wafer, which also causes a large potential difference in the semiconductor wafer.
[0005]
When a large potential difference is generated due to such a difference in Vdc or a shading effect, a large electric field is formed in the horizontal direction. Therefore, at the moment when the etching reaches the underlayer, such a large electric field is generated, and arcing occurs on the wafer. For example, on a Si wafer, SiO ₂ A conductive layer made of TiN or the like; ₂ When a hole and a trench are etched after laminating a dielectric layer composed of the above in order from the top, the conductive layer portion where the hole is formed and the trench are formed at the moment when the etching reaches the conductive layer. A large potential difference is generated between the conductive layer and the conductive layer, and a large electric field is formed between the two to cause arcing. When arcing occurs on the wafer in this manner, circuits formed on the wafer are destroyed, causing a reduction in chip yield and generation of particles.
[0006]
The present invention has been made in view of such circumstances, and has as its object to provide an electronic device in which arcing is unlikely to occur and a method for manufacturing the same.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, according to a first aspect of the present invention, at least a mask layer, a dielectric layer, and a conductive layer are formed on a substrate in order from the top, and the dielectric layer corresponds to a pattern of the mask layer. An electronic device manufactured through a process in which a layer is plasma-etched to expose the conductive layer, wherein the conductive layer has a high conductivity having a conductivity equal to or higher than that of Ti. An etched portion formed of a material and having at least a first portion and a second portion that are electrically insulated, wherein the etched portion where the first portion is exposed has an aspect ratio of the second portion. An electronic device characterized by being set to be larger than an aspect ratio of an exposed etching portion.
[0008]
As described above, the conductive layer has at least the first part and the second part that are electrically insulated, and the aspect ratio of the etching part formed in the first part is formed in the second part. For an electronic device having a larger aspect ratio than the etched portion, the first and second portions of the conductive layer are formed by forming a part or the whole of the conductive layer with a highly conductive material having a conductivity equal to or higher than that of Ti. 2 can be reduced, and the arcing on the substrate can be suppressed even if the distance between them is equal to or more than 0.07 μm and less than 5 μm, which is the same as that of the conventional device. it can. Conventionally, TiN having a relatively high resistance has been frequently used as this kind of conductive layer. However, in the case of TiN, when the distance between the first portion and the second portion of the conductive layer is a normal distance, these are used. Was large, and a large electric field was generated between the two to easily cause arcing. On the other hand, such a disadvantage is solved by using a highly conductive material having a conductivity equal to or higher than that of Ti.
[0009]
In this case, the highly conductive material is any one of Ti, W, Al, Cu, Pt, Au, Ag, and doped polysilicon, or a material containing at least one of them. The electronic device according to claim 1.
[0010]
Further, it is preferable that the whole of the conductive layer is formed of the above-mentioned highly conductive material, but a part thereof is made of the above-mentioned highly conductive material, typically the above-mentioned highly conductive material, and has a higher conductivity than Ti. The above effect can be obtained by adjusting the quantitative ratio even in a laminated structure with a low conductive material having a low conductivity.
[0011]
In a second aspect of the present invention, at least a mask layer, a dielectric layer, and a conductive layer are formed on a substrate in order from the top, and the dielectric layer is plasma-etched in accordance with the pattern of the mask layer, An electronic device manufactured through a step of exposing the conductive layer, wherein the conductive layer has a distance of 5 μm or more from each other and has an electrically insulated first portion and a second portion. Wherein the etched portion where the first portion is exposed has an aspect ratio set to be larger than the aspect ratio of the etched portion where the second portion is exposed. .
[0012]
As described above, the conductive layer has at least the first part and the second part that are electrically insulated, and the aspect ratio of the etching part formed in the first part is formed in the second part. For an electronic device having a larger aspect ratio than an etched portion, the electric field intensity between the first portion and the second portion of the conductive layer is set to 5 μm or more, which is wider than before, to reduce the electric field intensity therebetween. And arcing on the substrate can be suppressed. That is, since the electric field intensity is divided by the electric potential difference / distance, even if the electric potential difference between the first portion and the second portion of the conductive layer is large, the electric field intensity can be reduced by increasing the distance in this manner. Arcing on the substrate can be suppressed. Therefore, arcing is unlikely to occur even if a part of or all of the conductive layer in this case is made of a material having a lower conductivity than Ti, such as conventional TiN.
[0013]
In a third aspect of the present invention, at least a mask layer, a dielectric layer, and a conductive layer are formed on a substrate in order from the top, and the dielectric layer is plasma-etched in accordance with the pattern of the mask layer, An electronic device manufactured through a step of exposing the conductive layer, wherein the dielectric layer is formed of a porous material formed by spin coating, and the conductive layer is an electrically insulated second layer. An etched part having at least a first part and a second part, and an aspect ratio of an etched part where the first part is exposed is set to be larger than an aspect ratio of an etched part where the second part is exposed. An electronic device is provided.
[0014]
As described above, the conductive layer has at least the first part and the second part that are electrically insulated, and the aspect ratio of the etching part formed in the first part is formed in the second part. For an electronic device having a larger aspect ratio than the etched portion, by forming the dielectric layer from a porous material formed by spin coating, the dielectric layer is formed between the first and second portions of the conductive layer. The potential difference can be reduced, and arcing on the substrate can be suppressed even if the distance between them is equal to or more than 0.07 μm and less than 5 μm, which is equivalent to that of a conventional device. That is, one cause of arcing on the substrate is that the dielectric material constituting the dielectric layer is inherently easy to hold a charge, and such a dielectric layer is conventionally formed by CVD, which tends to generate a charge. This is due to remaining charge during CVD. When etching reaches the conductive layer in the presence of such a large amount of charge, an extremely large electric field is generated at that moment, and arcing occurs. Therefore, the remaining charge is reduced by forming the dielectric layer from a porous material formed by spin coating. That is, in the case of spin coating, there is no charge such as CVD at the film forming stage, and the charge is easily escaped by using a porous material, so that the remaining charge can be reduced, and the charge on the substrate can be reduced. Arcing can be suppressed. Therefore, even in this case, arcing is unlikely to occur even if a part or all of the conductive layer is made of a material having a lower conductivity than Ti, such as conventional TiN.
[0015]
In the second and third aspects, the conductive layer may be partially or entirely made of a low conductive material having a lower conductivity than Ti. In addition, as the low conductive material, any of TiN, TaN, WN, and doped polysilicon, or a material containing at least one of them can be used. Further, the conductive layer may have a laminated structure of the low conductive material and a high conductive material having a conductivity equal to or higher than that of Ti.
[0016]
The first to third aspects are particularly effective when the etched portion where the first portion is exposed has a shape corresponding to a hole having an aspect ratio of 4.5 or more.
[0017]
In a fourth aspect of the present invention, a structure in which at least a mask layer, a dielectric layer, and a conductive layer are formed on a substrate in order from the top is prepared, and the dielectric layer is provided in accordance with the pattern of the mask layer. A method for manufacturing an electronic device, wherein the conductive layer is exposed by plasma etching to manufacture any one of the electronic devices described above.
[0018]
In the present invention, the plasma etching can be performed by a parallel plate type magnetic field etching apparatus having a magnetic field intensity at the center of the substrate of more than 6000 μT.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view showing a laminated structure having a layer configuration for forming an electronic device according to an embodiment of the present invention, and FIG. 2 is a state in which the structure of the electronic device according to one embodiment of the present invention is formed by etching. FIG.
[0020]
1 has a dielectric layer 2 formed on a Si substrate 1, a conductive layer 3 functioning as a stopper layer and an electrode formed thereon, and a dielectric layer functioning as an interlayer insulating layer formed thereon. 4 are formed. Further, a resist film 5 patterned by photolithography is formed thereon as a mask layer. The conductive layer 3 is separated into a first portion 3a in which a hole is formed and a second portion 3b in which a trench is formed, and is separated by a dielectric layer 4 therebetween.
[0021]
1, the hole 6 reaching the first portion 3a and the trench 7 reaching the second portion 3b of the conductive layer 3 are simultaneously formed using the resist film 5 as a mask until the conductive layer 3 is reached. By etching, the electronic device shown in FIG. 2 is obtained.
[0022]
Next, the etching at this time will be described.
FIG. 3 is a diagram showing a schematic configuration of an etching apparatus for performing such etching. Here, a magnetron RIE plasma etching apparatus is exemplified.
[0023]
This etching apparatus has a chamber 11 made of, for example, aluminum which is airtightly configured. In the chamber 11, a support table 12 for horizontally supporting a Si wafer (hereinafter, simply referred to as “wafer”) W having the layer configuration shown in FIG. 1 is provided. The support table 12 is made of, for example, aluminum. An exhaust port 13 is formed at the bottom of the chamber 11, and an exhaust device 14 is connected to the exhaust port 13. The evacuation device 14 can reduce the pressure in the chamber 11 to a predetermined degree of vacuum. A high-frequency power supply 16 for plasma formation is connected to the support table 12 via a matching unit 15, and a high-frequency power of a predetermined frequency of 13.56 MHz or more (for example, 13.56 MHz or 40 MHz) is supplied from the high-frequency power supply 16. Is supplied to the support table 12. On the other hand, shower heads 20 are provided above and in parallel with the support table 12 in parallel with each other. Therefore, the support table 12 and the shower head 20 function as a pair of electrodes. The shower head 20 is provided with a large number of gas discharge holes 21 on its lower surface, and has a gas inlet 20a on its upper part. A gas supply pipe 22 is connected to the gas introduction section 20a, and the other end of the gas supply pipe 22 is connected to an etching gas supply system 23 that supplies an etching gas. As the etching gas supplied from the etching gas supply system 23, a halogen-based gas, O ₂ Gases usually used in this field, such as gas and Ar gas, can be used.
[0024]
On the other hand, a dipole ring magnet 30 is disposed concentrically around the chamber 11. As shown in the horizontal sectional view of FIG. 4, the dipole ring magnet 30 includes a plurality of anisotropic segmented columnar magnets 31 attached to a ring-shaped magnetic casing 32. In this example, 16 cylindrical anisotropic segment columnar magnets 31 are arranged in a ring shape. In FIG. 4, the arrows shown in the anisotropic segment columnar magnets 31 indicate the direction of magnetization, and as shown in this figure, the directions of magnetization of the plurality of anisotropic segment columnar magnets 31 are slightly shifted. Thus, a uniform horizontal magnetic field B directed in one direction as a whole is formed.
[0025]
Therefore, in the space between the support table 12 and the shower head 20, as shown in FIG. 3, a vertical electric field E is formed by the high-frequency power supply 16, and a horizontal magnetic field B is formed by the dipole ring magnet 30, A magnetron discharge is generated by the orthogonal electromagnetic field formed as described above. As a result, a plasma of an etching gas in a high energy state is formed, and a predetermined film can be efficiently etched.
[0026]
In such a magnetron RIE plasma etching apparatus, first, a gate valve (not shown) is opened, and the wafer W having the structure shown in FIG. 1 is carried into the chamber 11 and placed on the support table 12. Next, the inside of the chamber 11 is evacuated by the exhaust device 14 to a predetermined degree of vacuum. In this state, a predetermined etching gas is introduced into the chamber 11 from the etching gas supply system 23, and in this state, a high frequency power having a frequency of, for example, 13.56 MHz and a power of, for example, 1000 to 5000 W is supplied from the high frequency power supply 16 to the support table 12. Supply. Thus, an electric field E is formed between the shower head 20 as the upper electrode and the support table 12 as the lower electrode. On the other hand, since a horizontal magnetic field B is formed in the chamber 11 by the dipole ring magnet 30, a magnetron discharge is generated by a drift of electrons in the processing space where the wafer W is present, and the plasma of the etching gas formed thereby causes Using resist film 5 as a mask, dielectric layer 4 is etched. In this case, it is preferable that the magnetic field strength at the center of the wafer W be larger than 6000 μT.
[0027]
Here, at the time of etching, as shown in FIG. 5, since the portion of the resist film 5 near the plasma sheath S between the plasma P and the wafer W is negatively charged, electrons from the plasma P Although the momentum in the lateral direction is larger and electrons are difficult to reach inside the hole 6 having an aspect ratio as large as 4.5 or more, positive ions reach the hole 6 by being accelerated by the plasma sheath. Is positively charged at the bottom. On the other hand, electrons and ions reach the trench 7 having a small aspect ratio without difficulty.
[0028]
Therefore, at the moment when the etching of the hole 6 and the trench 7 reaches the conductive layer 3, the first portion 3 a of the conductive layer 3 where the hole 6 is formed and the second portion where the trench 7 is formed are formed by the shading effect. A large potential difference is generated between the portion 3b and an electric field is generated in the horizontal direction due to the large potential difference. When the electric field strength in the horizontal direction is equal to or more than a predetermined value, arcing occurs on the wafer W.
[0029]
Conventionally, TiN by CVD is frequently used as the conductive layer 3, and the distance between the first portion 3 a and the second portion 3 b is generally 0.07 μm or more and less than 5 μm. , 4 as SiO ₂ And organic low dielectric constant materials are formed by CVD, and arcing frequently occurs.
[0030]
Therefore, in the first embodiment of the present invention, the distance between the first portion 3a and the second portion 3b is kept at 0.07 μm or more and less than 5 μm, and the conductive layer 3 has a conductivity equal to or more than Ti. And made of a highly conductive material having
[0031]
The volume resistivity of TiN is about 400 × 10 ^-6 Ω · cm, whereas the volume resistivity of Ti is 42.0 × 10 ^-6 Ω · cm, and the resistivity of Ti is about 1/10 of that of TiN. Therefore, the conductivity of Ti is about 10 times that of TiN. Since the conductive layer 3 is made of a highly conductive material having a conductivity equal to or higher than that of Ti, the charge amount is reduced as compared with the related art, and the first portion 3a and the second portion of the conductive layer 3 are formed. The potential difference between the portion 3b can be reduced. Even if the distance between these portions is equal to or more than 0.07 μm and less than 5 μm, which is the same as that of the conventional device, it is possible to suppress the arcing on the wafer W. it can. However, it is of course limited to the case where such a material is allowed in the device design.
[0032]
Examples of the highly conductive material include any of Ti, W, Al, Cu, Pt, Au, Ag, and doped polysilicon, or a material containing at least one of them.
[0033]
In order to achieve such an effect, it is preferable that the whole of the conductive layer 3 is formed of the above-mentioned highly conductive material, but a part thereof is formed of a highly conductive material, typically a highly conductive material. Even in the case of a laminated structure with a low conductive material having a lower conductivity than Ti, arcing can be suppressed by adjusting the amount ratio. For example, when formation of TiN is essential, a TiN layer can be formed on the Ti layer at an appropriate thickness ratio.
[0034]
Further, in the second embodiment of the present invention, the distance between the first part 3a and the second part 3b is set to 5 μm or more, which is larger than that in the related art. Since electric field intensity∝potential difference / distance, even if a large electric potential difference occurs between the first portion 3a and the second portion 3b, the electric field intensity can be reduced by increasing the distance in this manner, Arcing on the wafer W can be suppressed even when a material having lower conductivity than Ti, such as TiN, which has been conventionally used, is used as the material of the conductive layer 3. However, of course, it is limited to the case allowed in the device design.
[0035]
As the applicable low-conductivity material, any of TiN, TaN, WN, and doped polysilicon, or a material containing at least one of them can be used. The conductive layer 3 does not need to be entirely formed of such a low-conductivity material. For example, the conductive layer 3 has a laminated structure of such a low-conductivity material and the above-described high-conductivity material. Is also good.
[0036]
Furthermore, in the third embodiment of the present invention, the distance between the first portion 3a and the second portion 3b is kept at 0.07 μm or more and less than 5 μm, and the dielectric layer 4 is made of a porous material by spin coating. It is constituted as.
[0037]
One cause of the arcing on the wafer W is that the dielectric material which has conventionally constituted the dielectric layer 4 is inherently easy to hold the charge, and the dielectric layer is conventionally formed by CVD. When the etching reaches the conductive layer 3 in a state where such a large amount of charge is present, an extremely large electric field is generated at that moment, and arcing is caused. Therefore, by forming the dielectric layer 4 by spin coating in which no charge is generated and by using a porous material from which the charge can easily escape, the remaining charge can be reduced, and the arcing on the substrate can be suppressed. it can. Therefore, even if the thickness is not less than 0.07 μm and less than 5 μm, which is equivalent to that of a conventional device, or if a low conductivity material having a lower conductivity than Ti such as TiN is used as the material of the conductive layer 3, the wafer W The above arcing can be suppressed.
[0038]
Examples of the low-conductivity material that can also be used in the present embodiment include any of TiN, TaN, WN, and doped polysilicon, or a material containing at least one of them. Also in this case, the conductive layer 3 does not need to be entirely formed of such a low conductivity material. For example, the conductive layer 3 may be formed of such a low conductivity material and the high conductivity material as described above. It may have a laminated structure. As the porous dielectric layer 4 formed by spin coating, an organic low dielectric constant material (Low-k material) is preferable.
[0039]
In addition, although the first to third embodiments are used alone, the occurrence of arcing can be effectively suppressed. However, by combining two or more of them, the occurrence of arcing can be more effectively suppressed.
[0040]
Next, a description will be given of a result of an experiment for confirming the easiness of arcing in each embodiment.
[0041]
(1) Experiment corresponding to the first embodiment
As shown in FIG. 6A, a dielectric layer 41 made of BPSG having a thickness of 1700 nm is formed, and a conductive layer 42 having a changed ratio of Ti to TiN is formed thereon. And a 400 nm thick P-SiO ₂ A dielectric layer 43 made of (TEOS) and a BARC layer 44 having a thickness of 80 nm are formed, and finally a photoresist layer 45 having a predetermined pattern having a thickness of 700 nm is formed, and the photoresist layer 45 is used as a mask in FIG. As shown in FIG. 2B, a hole 46 having a width of 0.25 μm (corresponding to an aspect ratio of 4.72) is etched until it reaches the conductive layer 42, and a trench 47 having a width of 0.5 μm is formed up to the dielectric layer 41 made of BPSG. Etched. When the etching of the trench reaches the dielectric layer 41 made of BPSG, the conductive layer 42 is separated into a hole forming portion and a trench forming portion, and a state equivalent to FIG. 2 is realized.
[0042]
Here, a sample 1 in which the upper layer of TiN is 20 nm and a lower layer of Ti is 15 nm, a sample 2 in which the upper layer of TiN is 80 nm, and the lower layer of Ti is 20 nm, and a sample in which the conductive layer 42 is composed of only 20 nm thick Ti Experiments were conducted on four samples, namely, Sample No. 3 and Sample 4 in which the conductive layer 43 was composed of only 80 nm thick TiN.
[0043]
The etching conditions are as follows: when etching the BARC layer 44, pressure: 5.45 Pa, high frequency power: 600 W, gas flow rate CF ₄ / Ar / O ₂ = 40/200/10 mL / min. When etching the dielectric layer 43, the conductive layer 42 and the dielectric layer 41 thereunder, the pressure is 5.45 Pa, the high frequency power is 1700 W, and the gas flow rate is C. ₄ F ₈ / CO / Ar / O ₂ = 10/50/250/5 mL / min, and the wafer temperature was 60 ° C in all cases.
[0044]
As a result of experimenting two samples under each condition, at the moment when the etching of the trench 47 reaches the dielectric layer 41, no arcing occurs in both samples in the sample 3 in which the conductive layer 42 is made of Ti. On the other hand, arcing occurred in both of the other samples. From this result, it was confirmed that the occurrence of arcing was suppressed by changing the conductive layer from TiN having low conductivity to Ti having high conductivity. However, the degree of arcing was different for Samples 1, 2 and 4, and severe arcing occurred in the case of only TiN. However, as the thickness of TiN decreased, the degree of arcing was reduced. Arcing was minor. From this, it is presumed that even if TiN is laminated, arcing can be effectively suppressed if the ratio is low.
[0045]
(2) Experiment corresponding to the second embodiment
As shown in FIG. 7A, a dielectric layer 51 made of BPSG having a thickness of 1700 nm is formed, and a laminated film of TiN having an upper layer thickness of 40 nm and Ti having a lower layer thickness of 20 nm is formed thereon. A conductive layer 52 is formed, and a 400 nm-thick P-SiO layer is further formed thereon. ₂ A dielectric layer 53 made of (TEOS) and a BARC layer 54 having a thickness of 80 nm are formed, and finally a photoresist layer 55 having a predetermined pattern having a thickness of 700 nm is formed. The photoresist layer 55 shown in FIG. As shown in (b), a hole 56 having a width of 0.25 μm (corresponding to an aspect ratio of 4.72) is etched until reaching the conductive layer 52, and the width A of the trench 57 is changed to etch the dielectric layer 51. And a device similar to the device of FIG.
[0046]
Here, an experiment was performed on three samples: Sample 5, in which the width A of the trench 57 was 0.5 μm, Sample 6, in which the width was 1.0 μm, and Sample 7, in which the width A was 5.0 μm. The etching conditions were the same as in the experiment corresponding to the first embodiment.
[0047]
As a result of experimenting two samples under each condition, at the moment when the etching of the trench 57 reaches the dielectric layer 51, no arcing occurs in the two samples 7 in which the width A of the trench 57 is 5 μm. In the case of Sample 5 in which the width of the trench 57 was set to 0.5 μm, arcing occurred in both samples. In the case of the sample 6 in which the width of the trench 57 was set to 1.0 μm, arcing occurred in both of the two samples, though the degree was somewhat reduced. From this result, it was confirmed that the occurrence of arcing was suppressed by setting the width of the separation portion of the conductive layer to 5 μm or more.
[0048]
(3) Experiment corresponding to the third embodiment
As shown in FIG. 8A, a dielectric layer 61 made of BPSG having a thickness of 1700 nm is formed, and a dielectric film 61 of TiN having an upper layer thickness of 40 nm and Ti having a lower layer thickness of 20 nm is formed thereon. A conductive layer 62 is formed, and a 400 nm thick SiOCH-based (SiO ₂ Low-k material in which a part of O of the above is replaced by CH) or P-SiO ₂ 8B, a dielectric layer 63 and a BARC layer 64 having a thickness of 80 nm are formed, and finally a photoresist layer 65 having a predetermined pattern having a thickness of 700 nm is formed. Using the photoresist layer 65 as a mask, (b) of FIG. 6), a hole 66 having a width of 0.25 μm (corresponding to an aspect ratio of 4.72) is etched until the conductive layer 62 is reached, and a trench 67 having a width of 0.5 μm is etched down to the dielectric layer 61. (B).
[0049]
Here, the dielectric layer 63 was formed by CVD using Corral (trade name) which is a dense SiOCH-based material, and was formed by spin coating using LKD27 (trade name) which was a dense SiOCH-based material. Sample 9, Sample 10 formed by spin coating using LKD5109 (trade name) which is a porous SiOCH material, and P-SiO which is a normal material as a comparative material ₂ An experiment was conducted on four samples of Sample 11 formed by CVD using the method. The etching conditions were the same as in the experiment corresponding to the first embodiment. The magnetic field intensity at the center of the wafer was changed to 6000 μT, 9000 μT, and 12000 μT.
[0050]
As a result of an experiment of two samples under each condition, when the magnetic field strength at the center of the wafer was 6000 μT, no arcing occurred in any of the samples at the moment when the etching of the trench 67 reached the dielectric layer 61. . In the case of 9000 μT and 12000 μT, arcing did not occur in both samples 10 using the spin-coated LKD5109 which is a porous SiOCH material as the dielectric layer 64, whereas the other samples did not. Arcing occurred on both cards. From this result, it was confirmed that the occurrence of arcing was suppressed by forming the dielectric layer 64 into a porous film by spin coating.
[0051]
The present invention can be variously modified without being limited to the above embodiment. For example, in the above embodiment, the case where the etching is performed using the magnetron RIE etching apparatus is described. However, the present invention is not limited to this, and the semiconductor device of the present invention is effective for etching using any other plasma etching apparatus. Further, the semiconductor device in the above embodiment is merely an example, and is effective in all cases where a large potential difference may occur due to a shading effect or a difference in Vdc. Further, in the above embodiment, the semiconductor device has been described as an example, but the present invention can be applied to other electronic devices.
[0052]
【The invention's effect】
As described above, according to the present invention, the first and second portions of the conductive layer are formed by forming a part or the whole of the conductive layer from a highly conductive material having a conductivity equal to or higher than that of Ti. 2 can be reduced, and the arcing on the substrate can be suppressed even if the distance between them is equal to or more than 0.07 μm and less than 5 μm, which is the same as that of the conventional device. it can.
[0053]
Further, according to the present invention, since the distance between the first portion and the second portion of the conductive layer is set to 5 μm or more, which is wider than in the related art, the electric field strength is reduced even if the potential difference between them is large. And arcing on the substrate can be suppressed.
[0054]
Furthermore, according to the present invention, since the dielectric layer is formed of a porous material formed by spin coating, there is no charge such as CVD at the film formation stage, and the charge is easily released, and the remaining charge is reduced. It is possible to reduce the number, and to suppress arcing on the substrate.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a laminated structure having a layer configuration for forming an electronic device according to an embodiment of the present invention.
FIG. 2 is a sectional view showing a state in which the structure of the electronic device according to the embodiment of the present invention is formed by plasma etching.
FIG. 3 is a schematic configuration diagram showing an example of an etching apparatus for etching an electronic device of the present invention.
FIG. 4 is a cross-sectional view schematically showing a dipole ring magnet and a state inside a chamber in the etching apparatus of FIG. 3;
FIG. 5 is a diagram schematically showing a charged state when the semiconductor device of FIG. 2 is being etched.
FIG. 6 is a diagram illustrating an experiment corresponding to the first embodiment.
FIG. 7 is a view for explaining an experiment corresponding to the second embodiment.
FIG. 8 is a view for explaining an experiment corresponding to the third embodiment.
[Explanation of symbols]
1; Si substrate
2, 4; dielectric layer
3; conductive layer
5; resist film
6; hall
7; trench
W; semiconductor wafer

Claims (14)

On the substrate, at least a mask layer, a dielectric layer, and a conductive layer are formed in order from the top, and the dielectric layer is plasma-etched in accordance with the pattern of the mask layer to expose the conductive layer. An electronic device manufactured through
The conductive layer is partially or entirely formed of a highly conductive material having a conductivity equal to or higher than that of Ti, and has at least a first portion and a second portion that are electrically insulated. An electronic device characterized in that an etched portion where the first portion is exposed has an aspect ratio larger than an aspect ratio of an etched portion where the second portion is exposed. 2. The high-conductivity material is one of Ti, W, Al, Cu, Pt, Au, Ag, and doped polysilicon, or a material containing at least one of them. An electronic device according to claim 1. The electronic device according to claim 1, wherein the conductive layer has a laminated structure of the high conductive material and a low conductive material having a lower conductivity than Ti. 4. The electron according to claim 1, wherein a distance between the first portion and the second portion of the conductive layer is not less than 0.07 μm and less than 5 μm. 5. device. On the substrate, at least a mask layer, a dielectric layer, and a conductive layer are formed in order from the top, and the dielectric layer is plasma-etched in accordance with the pattern of the mask layer to expose the conductive layer. An electronic device manufactured through
The conductive layer has a distance of 5 μm or more from each other, and has at least a first part and a second part that are electrically insulated. The etching part where the first part is exposed has an aspect ratio of An electronic device, wherein a ratio is set to be larger than an aspect ratio of an etched portion where the second portion is exposed. On the substrate, at least a mask layer, a dielectric layer, and a conductive layer are formed in order from the top, and the dielectric layer is plasma-etched in accordance with the pattern of the mask layer to expose the conductive layer. An electronic device manufactured through
The dielectric layer is made of a porous material formed by spin coating,
The conductive layer has at least a first portion and a second portion that are electrically insulated, and an etched portion where the first portion is exposed has an aspect ratio where the second portion is exposed. An electronic device, wherein the aspect ratio is set to be larger than an aspect ratio of an etched portion to be formed. The electronic device according to claim 6, wherein a distance between the first portion and the second portion of the conductive layer is 0.07 µm or more and less than 5 µm. 8. The electronic device according to claim 5, wherein the conductive layer is partially or entirely formed of a low-conductive material having a lower electrical conductivity than Ti. 9. . 9. The electronic device according to claim 8, wherein the low conductive material is any one of TiN, TaN, WN, and doped polysilicon, or a material including at least one of them. 10. The electronic device according to claim 8, wherein the conductive layer has a laminated structure of the low conductive material and a high conductive material having a conductivity equal to or higher than that of Ti. The electronic device according to any one of claims 1 to 11, wherein the etched portion exposing the first portion has an aspect ratio of 4.5 or more. The electronic device according to any one of claims 1 to 11, wherein the plasma etching is performed by a magnetic field parallel plate type etching apparatus in which a magnetic field intensity at a central portion of the substrate is larger than 6000 µT. On a substrate, at least a mask layer, a dielectric layer, and a conductive layer are formed in order from the top to prepare a structure, and the dielectric layer is plasma-etched in accordance with the pattern of the mask layer to form the conductive layer. And manufacturing the electronic device according to claim 1. 14. The method according to claim 13, wherein the plasma etching is performed by a parallel plate etching apparatus having a magnetic field at a central portion of the substrate that is greater than 6000 [mu] T.

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