JP2004171620A - Manufacturing method of ferroelectric memory, and ferroelectric memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent data written at the manufacturing process from vanishing at the subsequent heating process. <P>SOLUTION: A ROM area of the ferroelectric memory is provided with a pair of memory cells having a pair of ferroelectric capacitors wherein the data of logical levels reverse to each other are written. After the ferroelectric capacitors are formed at the manufacturing process, prescribed data are written into the ferroelectrfic capacitors in the ROM area. After that, a baking process is executed for the prescribed time. The inprint of the ferroelectric capacitors in the ROM area is advanced by the baking process, and the read-out margin being the difference in residual polarized values of the ferroelectric capacitances is increased. Thus, the data to be preliminarily stored in the ROM area in the manufacturing process are surely read out. That is, the data to be preliminarily stored in the ROM area are prevented from vanishing. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ferroelectric memory including a ROM area formed of ferroelectric memory cells and a method of manufacturing the same.
[0002]
[Prior art]
As a semiconductor memory device having both the advantages of a DRAM and a flash memory / EEPROM, a ferroelectric memory having a ferroelectric capacitor in a memory cell has been developed. A ferroelectric memory operates by using a ferroelectric capacitor as a variable capacitance capacitor and utilizes the fact that remanent polarization remains even when the voltage applied to the ferroelectric capacitor is zero, so that data can be stored even when power is not supplied. Can be held.
The power supply voltage (operating voltage) of the ferroelectric memory has been lowered due to miniaturization of the transistor structure, reduction of power consumption, and the like. For this reason, the characteristics of writing data to the ferroelectric capacitor deteriorate, and the read margin tends to decrease. Specifically, as the write voltage decreases, the hysteresis loop indicating the data write characteristic decreases, so that the amount of charge generated due to the change in polarization charge in the read operation decreases.
[0003]
On the other hand, recently, an IC card having a security function equipped with a ferroelectric memory has been developed. A ferroelectric memory mounted on this type of IC card has a ROM area in a part of a memory cell area. The ROM area stores key data used in a public key infrastructure (PKI). The key data is written in a ROM area by a manufacturer that manufactures a ferroelectric memory (for example, see Patent Document 1).
[0004]
By writing the key data in the ROM area of the ferroelectric memory in advance, the personal authentication of the user using the IC card can be performed with high reliability.
[Patent Document 1]
JP 2001-243761 A
[Problems to be solved by the invention]
Generally, when a ferroelectric memory is mounted on an IC card, the ferroelectric memory chip is soldered to a printed circuit board of the IC card. When soldering is performed by an infrared reflow process, the ferroelectric memory temporarily receives about 250 ° C. heat. It is known that the hysteresis characteristic of a ferroelectric memory has temperature dependence, and the hysteresis loop becomes smaller as the temperature of the ferroelectric capacitor increases (the depolarization of the ferroelectric capacitor). Therefore, even when the key data is written in the ROM area so that the remanent polarization occurs sufficiently, the remanent polarization value is reduced by the subsequent soldering process (heat treatment), and the read margin is reduced. That is, the written data is lost. This problem is more remarkable as the operating voltage is lower (as the writing voltage is lower).
[0006]
An object of the present invention is to prevent data written in a manufacturing process from being lost in a subsequent heating process.
[0007]
[Means for Solving the Problems]
In the method for manufacturing a ferroelectric memory according to the first aspect and the ferroelectric memory according to the fifth aspect, the ferroelectric memory has a ROM area and a RAM area each including a memory cell including a ferroelectric capacitor. I have. The ROM area has a pair of memory cells having a pair of ferroelectric capacitors into which data of opposite logic levels are written.
In a ferroelectric memory, predetermined data is written to a ferroelectric capacitor pair in a ROM area after a ferroelectric capacitor is formed in a manufacturing process. Thereafter, a baking process is performed for a predetermined time. Imprinting of the ferroelectric capacitor pair in the ROM area progresses by the baking process, and the read margin, which is the difference between the residual polarization values of the ferroelectric capacitor pair, increases. As a result, data previously stored in the ROM area in the manufacturing process can be reliably read.
[0008]
In the method of manufacturing a ferroelectric memory according to the second aspect, the baking process is performed while the read margin is degraded due to depolarization of the ferroelectric capacitor pair due to heat applied in an assembly process after manufacturing the ferroelectric memory chip. Is set to a time supplemented by the improvement of the read margin by imprint. Therefore, even when the ferroelectric capacitor pair is depolarized in the assembling process, it is possible to prevent a read margin of data stored in the ROM area from deteriorating. In other words, loss of data stored in the ROM area in advance can be prevented.
[0009]
In the method of manufacturing a ferroelectric memory according to the third aspect, the temperature of the baking process is set lower than the processing temperature in the assembly process after manufacturing the ferroelectric memory chip. Generally, the depolarization of a ferroelectric capacitor increases as the temperature during the heat treatment increases. By lowering the temperature of the baking process, depolarization of the ferroelectric capacitor pair during the baking process can be minimized, and the read margin can be further improved.
[0010]
In the method of manufacturing a ferroelectric memory according to the fourth aspect, the predetermined data written to the ferroelectric capacitor pair is written using the maximum voltage of the operating voltage specification of the ferroelectric memory. Generally, imprinting of a ferroelectric capacitor proceeds as the voltage applied to the ferroelectric capacitor increases. Therefore, imprint efficiency can be improved and the bake time can be reduced by applying the maximum voltage that can be applied to the ferroelectric capacitor pair. Further, since a voltage exceeding the allowable voltage is not applied, the ferroelectric memory can be prevented from being broken.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the figure, a signal line indicated by a bold line is composed of a plurality of bits.
FIG. 1 shows an embodiment of a method for manufacturing a ferroelectric memory and a ferroelectric memory according to the present invention. The ferroelectric memory is formed on a silicon substrate using a CMOS process.
The ferroelectric memory includes a command buffer CMDB, a command decoder CMDD, an address buffer ADB, a control circuit CONT, a row decoder RDEC, a column decoder CDEC, a word driver row WD, a memory cell array ARY, a plate driver row PD, a sense amplifier row SA, and It has a data input / output circuit I / O.
[0012]
The command buffer CMDB receives a command signal such as a write enable signal via an external terminal, and outputs the received signal to the command decoder CMDD. Address buffer ADB receives an address signal via an external terminal, and outputs the received signal to row decoder RDEC and column decoder CDEC.
The command decoder CMDD decodes the command signal and outputs a result of the decoding to the control circuit CONT. The control circuit CONT generates a control signal for operating the plate driver row PD, the word driver row WD, the sense amplifier row SA, and the data input / output circuit I / O. The row decoder RDEC decodes an upper address signal to generate a decode signal, and outputs the generated signal to the word driver row WD. The column decoder CDEC decodes the lower address signal to generate a decoded signal, and outputs the generated signal to the column decoder column CDEC.
[0013]
The plate driver array PD has a plurality of plate drivers. The plate driver array PD changes a predetermined plate line PL to a plate voltage or a ground voltage in response to a control signal from the control circuit CONT. The word driver row WD has a plurality of word drivers. Word driver array WD changes a predetermined word line WL to a high voltage or a ground voltage in response to a control signal from control circuit CONT and a decode signal from row decoder RDEC.
[0014]
In the memory cell array ARY, a plurality of memory cell pairs MCP (broken frame in the figure) are arranged in a matrix. The ROM area RO (within the dashed-dotted frame in the figure) is formed by a predetermined number of memory cell pairs MCP connected to the same word line WL. The remaining memory cell pairs MCP form a RAM area RA (within a frame indicated by a two-dot chain line in the figure). In the ROM area RO, for example, key data used on a public key basis in a test process at the time of manufacturing a ferroelectric memory is written. After that, the word line WL connected to the ROM area RO is selected only during the read operation.
[0015]
The memory cell pair MCP includes a memory cell MC1 having a transfer transistor T1 and a ferroelectric capacitor C1, and a memory cell MC2 having a transfer transistor T2 and a ferroelectric capacitor C2. A ferroelectric capacitor pair is formed by the ferroelectric capacitors C1 and C2. In a write operation, data of complementary logic levels (complementary data) are written in the memory cells MC1 and MC2.
[0016]
In the transfer transistor T1 of the memory cell MC1, one of the source and the drain is connected to the bit line BL, the other of the source and the drain is connected to one end of the ferroelectric capacitor C1, and the gate is connected to the word line WL. In the transfer transistor T2 of the memory cell MC2, one of the source and the drain is connected to the bit line / BL, the other of the source and the drain is connected to one end of the ferroelectric capacitor C2, and the gate is connected to the word line WL. . The other ends of the ferroelectric capacitors C1 and C2 are connected to a plate line PL.
[0017]
The sense amplifier array SA has a plurality of sense amplifiers and column switches connected to the bit line pairs BL and / BL. The sense amplifier amplifies the voltage difference between the bit lines BL and / BL generated according to the residual polarization values of the ferroelectric capacitors C1 and C2 in the read operation. The column switch is turned on in response to the decode signal output from the column decoder CDEC, and outputs a part of the data amplified by the sense amplifier to the data input / output circuit I / O as read data.
[0018]
The data input / output circuit I / O outputs write data from the outside to the sense amplifier array SA or outputs read data from the sense amplifier array SA to the outside in response to a control signal from the control circuit CONT.
FIG. 2 shows an outline of a manufacturing process of the ferroelectric memory of the present invention.
First, in a wafer process, devices such as transistors and ferroelectric capacitors are formed on a silicon wafer. In addition, an insulating film, wiring, and the like are also formed to form an element (FIG. 2A).
[0019]
Next, in a test process, an operation test of each of the plurality of ferroelectric memory chips formed on the wafer is performed (FIG. 2B).
Thereafter, key data and the like are written into the ROM area RO using an LSI tester or the like (FIG. 2C).
Thereafter, wafer baking is performed (FIG. 2D). Wafer baking is performed, for example, in a baking furnace at 150 ° C. for 4 hours with a DC bias applied to the ferroelectric capacitors C1 and C2 in the ROM area RO. Here, the DC bias is set to 4.5 V which is the maximum value of the operating power supply voltage specification of the ferroelectric memory. Therefore, the input circuit and the like of the ferroelectric memory are not broken by the application of the DC bias. Generally, imprinting of the ferroelectric capacitors C1 and C2 proceeds as the voltage applied to the ferroelectric capacitors C1 and C2 increases. Therefore, by applying the maximum voltage that can be applied to the ferroelectric capacitor pair C1 and C2, the imprint efficiency is improved and the bake time is shortened.
[0020]
By the wafer baking, as shown in FIGS. 3 and 4 described later, the ferroelectric capacitor is imprinted, and the hysteresis characteristic of the ferroelectric capacitor shifts in the voltage direction. As will be described in detail with reference to FIG. 4, the remanent polarization value of the ferroelectric capacitor pair C1 and C2 of the memory cell pair MCP changes due to imprint, so that the read margin is improved.
[0021]
Actually, the baking time, the baking temperature, and the applied voltage are accompanied by the depolarization of the ferroelectric capacitor pair C1 and C2 due to the heat applied in the infrared reflow (FIG. 2E) after manufacturing the ferroelectric memory chip. The time is set such that the deterioration of the read margin is compensated by the improvement of the read margin due to the imprint in the bake processing. The baking temperature is set to 150 ° C. which is lower than the temperature (about 250 ° C.) applied to the ferroelectric memory by infrared reflow.
[0022]
The baking temperature is desirably lower than the Curie point and as high as possible. At this time, it is desirable to minimize the depolarization of the ferroelectric capacitor pair C1, C2. When the ferroelectric memory is baked at 150 ° C., the read margin is hardly reduced due to the depolarization of the ferroelectric capacitors C1 and C2.
Next, in an assembling process, the ferroelectric memory chips cut out from the wafer are soldered to a substrate constituting an IC card or the like. The soldering is performed, for example, by infrared reflow (FIG. 2E). The residual polarization value (absolute value) of the ferroelectric capacitor is reduced (depolarized) by heat (approximately 250 ° C.) applied to the ferroelectric memory during the infrared reflow process. Therefore, the read margin decreases. However, since the read margin is improved by the above-described wafer baking, a decrease in the read margin is prevented in the entire manufacturing process of the ferroelectric memory. In other words, the key data written in advance to the ferroelectric capacitor is prevented from being lost by the heat treatment in the assembly process.
[0023]
Thereafter, an operation test is performed with the ferroelectric memory mounted on the IC card (FIG. 2 (f)).
FIG. 3 shows a hysteresis characteristic that changes by the baking process shown in FIG.
First, when key data is written in the ferroelectric capacitors C1 and C2 in the ROM area RO shown in FIG. 1, as shown in FIG. The remanent polarization value P is located in a black circle in the figure, and the remanent polarization value P of the ferroelectric capacitor in which the logic “0” is written is located in a white circle in the figure.
[0024]
The amount of charge generated from the ferroelectric capacitors C1 and C2 when data is read from the memory cell becomes a value corresponding to the residual polarization values R1 and R0 in logic "1" and logic "0". In the example shown in FIG. 3, this charge amount is a value generated when a 3 V electric field is applied to both ends of the ferroelectric capacitor.
FIG. 3B shows a hysteresis characteristic of the ferroelectric capacitor in which the logic “1” is written after the baking process. The hysteresis characteristic is shifted rightward in the figure by the baking process (solid line in the figure). Therefore, the remanent polarization value P (black circle in the figure) shifts to the negative side. Therefore, the remanent polarization value BR1 increases as compared with the remanent polarization value R1 before the baking process.
[0025]
On the other hand, FIG. 3C shows the hysteresis characteristic of the ferroelectric capacitor into which the logic “0” has been written after the baking process. The hysteresis characteristic shifts to the left in the drawing due to the baking process (solid line in the drawing). Therefore, the remanent polarization value P (open circle in the figure) shifts to the positive side. Therefore, the remanent polarization value BR0 is smaller than the remanent polarization value R0 before the baking process.
[0026]
As described above, in this embodiment, after complementary data is written in the ferroelectric capacitor pair C1 and C2, the baking process is performed, so that the remanent polarization value P corresponding to the logic “1” increases, and The remanent polarization value P corresponding to "0" decreases. As a result, the read margin of the memory cell pair MCP is improved.
FIG. 4 shows a change in the read margin depending on the bake time.
[0027]
Generally, the shift (imprint) of the hysteresis characteristic due to the baking process largely depends on the baking time. Therefore, the difference between the charge amounts of the ferroelectric capacitor pairs C1 and C2 in which the complementary data is written increases as the baking time increases. The voltage difference between the pair of bit lines BL and / BL in the read operation increases as the difference between the charge amounts increases. Therefore, the read margin improves as the bake time increases.
[0028]
FIG. 5 shows a change (experimental value) of the read margin depending on the baking condition. In this experiment, baking was performed at 150 ° C. for 4 hours as a condition of the baking treatment shown in FIG. 2D (bake 1), and as a condition assuming infrared reflow shown in FIG. A bake 2 at 30 ° C. for 30 minutes was performed (bake 2). Under these conditions, the read margin was evaluated using the write voltage and the presence / absence of a DC bias at the time of baking 1 as parameters. The write voltage was set to 3.3 V or 4.5 V, and when a DC bias was applied, the voltage was set to the same value as the write voltage. Here, the write voltage is a voltage applied to both ends of the ferroelectric capacitors C1 and C2.
[0029]
As a result, it was confirmed that the read margin (the amount of charge per unit area) was improved as the write voltage was higher, and that the application of a DC bias was improved. Similar to the results of this experiment, there is a report that imprinting proceeds more when the bias is applied during the bake than when no bias is applied (Takashi Hase, et. Composition "Jpn. J. Appl. Phys. Vol. 37 (1998) pp. 5198-5102).
[0030]
As described above, in the present embodiment, in the ferroelectric memory having the ROM area RO in which key data and the like are previously written in the manufacturing process, the baking process is performed for a predetermined time in the test process after the key data is written. Imprinting of the ferroelectric capacitor pairs C1 and C2 in the ROM area RO proceeds by the baking process, so that the read margin, which is the difference between the residual polarization values of the ferroelectric capacitor pairs C1 and C2, can be increased. As a result, key data and the like stored in the ROM area RO in advance can be reliably read.
[0031]
The time required for the bake processing depends on the deterioration of the read margin caused by the depolarization of the ferroelectric capacitor pair C1 and C2 due to the heat of the infrared reflow added in the assembly process after the manufacture of the ferroelectric memory chip. Is set to a time that is compensated for by the improvement of the read margin. Therefore, even when the ferroelectric capacitor pair C1 and C2 are depolarized by the heat treatment by the infrared reflow, it is possible to prevent the read margin of the key data stored in the ROM area RO from being deteriorated. In other words, it is possible to prevent the key data previously stored in the ROM area RO from being lost.
[0032]
The temperature of the baking process is set to 150 ° C., which is lower than the processing temperature (about 250 ° C.) of the infrared reflow in the assembling process after manufacturing the ferroelectric memory chip. By lowering the temperature of the baking process, depolarization of the ferroelectric capacitor pair C1 and C2 during the baking process can be minimized, and the read margin can be further improved.
The key data written to the ferroelectric capacitor pair C1 and C2 is written at the maximum voltage of 4.5 V of the operating voltage specification of the ferroelectric memory. By applying a maximum voltage of 4.5 V that can be applied to the ferroelectric capacitor pair C1 and C2, imprint efficiency can be improved and baking time can be reduced. Further, since a voltage exceeding the allowable voltage is not applied, the ferroelectric memory can be prevented from being broken.
[0033]
In the above-described embodiment, an example has been described in which the key data is written into the ROM area RO and then the baking process is performed. The present invention is not limited to such an embodiment. For example, as shown in FIG. 6, writing of key data and baking processing may be performed simultaneously. That is, the key data may be written in a high-temperature baking furnace and the DC bias may be continuously applied.
[0034]
In the above-described embodiment, the example in which the DC bias is applied at the time of baking has been described. The present invention is not limited to such an embodiment. For example, the same effect can be obtained by applying a unipolar pulse during baking. However, the imprint characteristics change depending on the time during which a bias is applied to the ferroelectric capacitor. For this reason, the application of the DC bias is more efficient than the application of the pulse, and the baking time is shorter.
[0035]
Further, in the above-described embodiment, a test circuit for applying a DC bias at the time of baking is not particularly mentioned. However, for example, a test pad for applying a DC bias to the ferroelectric memory and a test circuit for directly applying the DC bias supplied to the test pad to the ferroelectric capacitor in the ROM area RO are provided with a ferroelectric capacitor. By forming it in the body memory, a DC bias can be easily applied at the time of baking, and imprinting can be efficiently performed. When a unipolar pulse is applied during baking, no special test circuit is required.
[0036]
As described above, the present invention has been described in detail. However, the above-described embodiment and its modifications are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the present invention.
[0037]
【The invention's effect】
In the method for manufacturing a ferroelectric memory according to the first aspect and the ferroelectric memory according to the fifth aspect, the imprint of the ferroelectric capacitor pair in the ROM area in which data is written in advance in the manufacturing process is performed by baking. The read margin, which is the difference between the residual polarization values of the ferroelectric capacitor pair, can be increased. As a result, data stored in the ROM area in advance can be reliably read.
According to the method of manufacturing a ferroelectric memory of the second aspect, even when the ferroelectric capacitor pair is depolarized in the assembling process, it is possible to prevent the read margin of data stored in the ROM area from deteriorating. In other words, loss of data stored in the ROM area in advance can be prevented.
[0038]
In the method of manufacturing a ferroelectric memory according to the third aspect, by lowering the temperature of the baking process, depolarization of the ferroelectric capacitor pair during the baking process can be minimized, and the read margin can be further improved.
In the method of manufacturing a ferroelectric memory according to the fourth aspect, imprint efficiency can be improved and baking time can be reduced by applying the maximum voltage that can be applied to the ferroelectric capacitor pair. Further, since a voltage exceeding the allowable voltage is not applied, the ferroelectric memory can be prevented from being broken.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a flowchart showing an outline of a manufacturing process of the ferroelectric memory of the present invention.
FIG. 3 is an explanatory diagram showing hysteresis characteristics that change by baking shown in FIG. 2;
FIG. 4 is an explanatory diagram showing a change in a read margin depending on a bake time.
FIG. 5
9 is experimental data showing a change in a read margin depending on a bake condition.
FIG. 6 is a flowchart showing another example of the manufacturing process of the ferroelectric memory of the present invention.
[Explanation of symbols]
ADB Address buffer ARY Memory cell array BL, / BL Bit lines C1, C2 Ferroelectric capacitor CDEC Column decoder CMDB Command buffer CMDD Command decoder CONT Control circuit I / O Data input / output circuit MC1, MC2 Memory cell MCP Memory cell vs. PD Plate driver Column PL Plate line RA RAM area RDEC Row decoder RO ROM area SA Sense amplifier row T1, T2 Transfer transistor WD Word driver row WL Word line

Claims (5)

The ROM area includes a ROM area and a RAM area each including a memory cell having a ferroelectric capacitor, and the ROM area includes a memory cell pair including a ferroelectric capacitor pair to which data of opposite logic levels are written. A method for manufacturing a ferroelectric memory, comprising:
In order to increase the read margin, which is the difference between the remanent polarization values of the ferroelectric capacitor pairs, by advancing the imprinting of the ferroelectric capacitor pairs in the ROM area, predetermined data is written to the ferroelectric capacitor pairs. A method of manufacturing a ferroelectric memory, comprising performing a baking process for a predetermined time after writing. The method for manufacturing a ferroelectric memory according to claim 1,
Deterioration of the read margin due to the depolarization of the ferroelectric capacitor pair due to heat applied in the assembly process after the manufacture of the ferroelectric memory chip compensates for the time of the bake processing by the improvement of the read margin by the imprint. A method of manufacturing a ferroelectric memory, wherein the method is set to time. The method for manufacturing a ferroelectric memory according to claim 1,
A method of manufacturing a ferroelectric memory, wherein a temperature of the baking process is set lower than a processing temperature in an assembling process after manufacturing a ferroelectric memory chip. The method for manufacturing a ferroelectric memory according to claim 1,
A method of manufacturing a ferroelectric memory, wherein the predetermined data to be written to the ferroelectric capacitor pair is written using a maximum voltage of an operating voltage specification of the ferroelectric memory. A ROM area and a RAM area each including a memory cell having a ferroelectric capacitor,
The ROM area includes a memory cell pair having a ferroelectric capacitor pair in which data of opposite logic levels are written,
The ferroelectric capacitor pairs in the ROM area are imprinted by baking for a predetermined time after writing predetermined data in order to increase a read margin, which is a difference in remanent polarization value. Ferroelectric memory.

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