JP2004171232A - Integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a programmable integrated circuit with the high degree of freedom in developing software. <P>SOLUTION: This integrated circuit is provided with an instruction bus 18 for connecting a processor 11 to an instruction memory 12, a data bus 19 for connecting the processor 11 to a data memory 13, shared memory banks 14-0 to 14-3 which can be mapped as the instruction memory 12 or the data memory 13, multiplexers 15-0 to 17-3 for selectively connecting a shared memory to the instruction bus or the data bus according to selection signals SEL0 to SEL3, and a bus control circuit 20 having a shared memory setting register 201 for holding status information indicating which of the instruction memory and the data memory has the shared memory bank mapped at present for outputting the selection signals SEL0 to SEL3 to the multiplexers 15-0 to 17-3 on the basis of the set status information. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a processor having a Harvard architecture and an integrated circuit having an instruction memory and a data memory mounted on one chip.
[0002]
[Prior art]
In a system LSI on which a microprocessor is mounted, a memory is mounted on a chip to speed up the processing.
In order to process more programs and data at a time, it is desirable that the amount of memory installed is as large as possible.
[0003]
However, although the miniaturization of the process is progressing, the memory, especially the SRAM for the processor for realizing the high-speed processing, is still large in area and consumes large power.
For this reason, it is common to mount a necessary minimum memory size on an LSI to increase chip cost.
[0004]
[Problems to be solved by the invention]
However, software development is often performed after the LSI is manufactured, and if the amount of memory estimated at the time of examining the specifications of the LSI is not sufficient, it takes much time and effort to develop the software to reduce the amount of code. Conversely, if the estimated amount of memory is too large, it tends to lead to an increase in chip cost.
[0005]
In particular, in the Harvard architecture, the instruction memory and the data memory are connected to independent buses. Therefore, if the estimation of the code amount and the estimation of both the data amount to be used are not performed with high accuracy, the instruction memory must be integrated after the LSI. Since the data memory and the data memory cannot be interchanged as the instruction memory, a problem tends to occur.
[0006]
To put it bluntly, a typical Harvard architecture processor has instructions to read and write data to and from the instruction memory, but switching from the instruction pipeline to the data pipeline requires multiple instruction cycles, The throughput is greatly reduced as compared with the case of accessing a normal data memory.
[0007]
The present invention has been made in view of such circumstances, and has as its object to reduce the amount of instruction memory and data memory used by software when designing an LSI equipped with a Harvard architecture microprocessor and built-in memory. An object of the present invention is to provide a programmable integrated circuit having a high degree of freedom during software development even if the estimation is not so accurate.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention is a processor having a Harvard architecture, an integrated circuit having an instruction memory and a data memory, and an instruction bus connecting the processor and the instruction memory. A data bus connecting the processor and the data memory, a shared memory that can be mapped as an instruction memory or a data memory, and selectively connecting the shared memory and the instruction bus or the data bus according to a selection signal Connection switching means, shared memory status holding means for holding at least status information indicating whether the shared memory is currently mapped to the instruction memory or the data memory, and access from the processor to the shared memory. When the instruction is received, the above shared memory status is retained And a bus control means for outputting said selection signal to said connection switching means on the basis of the status information of the stage.
[0009]
A second aspect of the present invention is an integrated circuit including a processor having a Harvard architecture, an instruction memory and a data memory, the instruction bus connecting the processor and the instruction memory, the processor and the data memory. , A plurality of shared memory banks that can be mapped as an instruction memory or a data memory, and selectively connect the desired shared memory bank and the instruction bus or the data bus according to a selection signal. Connection switching means, a shared memory setting register for holding status information as to whether at least the shared memory bank is currently mapped to the instruction memory or the data memory, and an access instruction from the processor to the shared memory Received, the shared memory setting register It said selection signal based on the status information and a bus control means for outputting to said connection switching means.
[0010]
Preferably, there is further provided a coincidence detecting circuit for comparing the address held in advance at a timing of accessing a specific address of the shared memory bank, and outputting an interrupt control signal to the processor when the addresses match.
[0011]
The match detection circuit detects a match between a shared memory interrupt address register for writing a value of a specific address of the instruction memory or the data memory to each bank and an instruction address or a data address. A match detection register for outputting a signal to the processor.
[0012]
Preferably, the shared memory setting register exists for each shared memory bank, and is at least always mapped as an instruction memory, always mapped as a data memory, and mapped as an instruction memory, but is also used as a data memory. Possible, and status information that is mapped as a data memory but can also be used as an instruction memory can be set and changed.
[0013]
The shared memory setting register further considers one bank as a predetermined page, and sets information on whether the shared memory is to be mapped to an instruction memory or a data memory and to which page the bank is assigned, Can be changed.
[0014]
The bus control circuit includes an address decoder that decodes an instruction address and a data address output from the processor, and permits access to a corresponding memory bank based on the address decoded by the address decoder.
[0015]
Preferably, the address decoder is kept inactive when not using the shared memory bank.
[0016]
According to the present invention, for example, an instruction address and a data address output from the processor are decoded by the address decoder of the bus control means, and access to the corresponding memory bank is permitted.
In the bus control means, based on management information of the shared memory bank, that is, based on status information set in the shared memory setting register, whether each bank is mapped to the instruction memory or the data memory, and Determine which page each is mapped to.
The bus control means activates a necessary selection signal according to the determination result, and permits access between a necessary bus and a memory.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
[0018]
FIG. 1 is a circuit diagram showing an embodiment of an integrated circuit in which a processor having a Harvard architecture according to the present invention and an instruction memory and a data memory are mounted on one chip.
[0019]
As shown in FIG. 1, the present integrated circuit 10 includes four shared memory banks that can be mapped as a Harvard architecture processor (CPU) 11, an instruction memory (IMEM) 12, a data memory (DMEM) 13, and an instruction memory or a data memory. 14-0 to 14-3 (SMEM, BNK0 to BNK3), multiplexers 15-0 to 15-3, multiplexers 16-0 to 16-3, multiplexers 17-0 to 17-3, instruction address bus 18-A, instruction It has a write bus 18-W, an instruction read bus 18-R, a data address bus 19-A, a data write bus 19-W, a data read bus 19-R, and a bus control circuit (BSCTL) 20.
Of these components, the connection switching means is constituted by the multiplexers 15-0 to 15-3, the multiplexers 16-0 to 16-3, and the multiplexers 17-0 to 17-3.
[0020]
In the integrated circuit 10, the processor 11 and the instruction memory 12 are connected via an instruction address bus 18-A, an instruction write bus 18-W, and an instruction read bus 18-R.
Further, the processor 11 and the data memory 13 are connected via a data address bus 19-A, a data write bus 19-W, and a data read bus 19-R.
The processor 11 and the bus control circuit 20 are connected to the instruction address bus 18-A, the instruction write bus 18-W, the instruction read bus 18-R, the data address bus 19-A, the data write bus 19-W, And a data read bus 19-R.
[0021]
The instruction memory 11, the data memory 12, and the shared memory banks 14-0 to 14-3 according to the present embodiment are configured by SRAMs.
[0022]
FIG. 2 is a diagram for explaining a memory configuration of the system according to the present embodiment. In FIG. 2, ADR indicates an address, WD indicates write data, CTL indicates a control signal, and RD indicates read data.
FIGS. 3A to 3C are diagrams illustrating examples of a memory map of the instruction memory, the data memory, and the shared memory according to the present embodiment.
[0023]
In the present embodiment, as shown in FIG. 2, the memory of one bank has n address lines, m write data signals, and m read data signals, and an interface for control signals. The total number of bits is mx2n.
In this example, the size of 4 Kb per bank is assumed, but the bit width is arbitrary, and the instruction and the data are the same.
As shown in FIG. 3, the instruction memory 12 maps four banks (BNK0 to BNK3) to a total space of 16 Kb and 0x0000-0x3FFF, and the data memory 13 maps four banks total 16Kb and a space of 0x0000-0x3FFF. ing.
The rest of the space is empty.
The capacity per bank is 1 Kb, and the address is 0x0-0x0FFF.
[0024]
The multiplexer 15-0 connects the shared memory bank 14-0 to the instruction address bus 18-A or the data address bus 19-A in accordance with the instruction of the memory bank selection signal SEL0 from the bus control circuit 20.
The multiplexer 15-1 connects the shared memory bank 14-1 to the instruction address bus 18-A or the data address bus 19-A according to the instruction of the memory bank selection signal SEL1 from the bus control circuit 20.
The multiplexer 15-2 connects the shared memory bank 14-2 to the instruction address bus 18-A or the data address bus 19-A according to the instruction of the memory bank selection signal SEL2 from the bus control circuit 20.
The multiplexer 15-3 connects the shared memory bank 14-3 with the instruction address bus 18-A or the data address bus 19-A in accordance with the instruction of the memory bank selection signal SEL3 from the bus control circuit 20.
[0025]
The multiplexer 16-0 connects the shared memory bank 14-0 to the instruction write bus 18-W or the data write bus 19-W according to the instruction of the memory bank selection signal SEL0 by the bus control circuit 20.
The multiplexer 16-1 connects the shared memory bank 14-1 to the instruction write bus 18-W or the data write bus 19-W according to the instruction of the memory bank selection signal SEL1 from the bus control circuit 20.
The multiplexer 16-2 connects the shared memory bank 14-2 to the instruction write bus 18-W or the data write bus 19-W according to the instruction of the memory bank selection signal SEL2 from the bus control circuit 20.
The multiplexer 16-3 connects the shared memory bank 14-3 to the instruction write bus 18-W or the data write bus 19-W according to the instruction of the memory bank selection signal SEL3 from the bus control circuit 20.
[0026]
The multiplexer 17-0 connects the shared memory bank 14-0 to the instruction read bus 18-R or the data read bus 19-R in accordance with the instruction of the memory bank selection signal SEL0 from the bus control circuit 20.
The multiplexer 17-1 connects the shared memory bank 14-1 to the instruction read bus 18-R or the data read bus 19-R according to the instruction of the memory bank selection signal SEL1 from the bus control circuit 20.
The multiplexer 17-2 connects the shared memory bank 14-2 to the instruction read bus 18-R or the data read bus 19-R according to the instruction of the memory bank selection signal SEL2 from the bus control circuit 20.
The multiplexer 17-3 connects the shared memory bank 14-3 to the instruction read bus 18-R or the data read bus 19-R in accordance with the instruction of the memory bank selection signal SEL3 from the bus control circuit 20.
[0027]
The bus control circuit 20 has a shared memory setting register (SMEM SREG) 201 as an shared memory status holding unit, an address decoder (ADRDEC) 202, and a coincidence detection circuit (DTC) 203.
[0028]
The shared memory setting register (SMEMSREG) 201 holds status information indicating whether the shared memories 14-0 to 14-3 are currently mapped to the instruction memory 12 or the data memory 13.
The address decoder (ADRDEC) 202 decodes the instruction address IA and the data address DA from the processor 11 through the instruction address bus 18-A or the data address bus 19-A, and permits access to the corresponding shared memory bank.
The match detection circuit (DTC) 203 compares the stored address at a timing of accessing a specific address of the shared memories 14-0 to 14-3, and outputs a interrupt control signal INTRPT when the addresses match. Output to
[0029]
When the address decoder 202 receives an instruction to access the shared memories 14-0 to 14-3 by the address decoder 202, the bus control circuit 20 changes the memory bank selection signal SEL0 based on the status information set in the shared memory setting register (SMEMSREG) 201. The multiplexers 15-0, 16-0, 17-0, the memory bank selection signal SEL1 is applied to the multiplexers 15-1, 16-1, 17-1, and the memory bank selection signal SEL2 is applied to the multiplexers 15-2, 16-2, 17. -2, the memory bank selection signal SEL3 is selectively supplied to the multiplexers 15-3, 16-3, and 17-3.
[0030]
When the shared memory is not used, the address decoder 202 is controlled so as not to operate, and the read data is not read indefinitely. Processing such as connecting GND to the inputs of the multiplexers 17-0 to 17-3 is performed. It is necessary to keep it.
[0031]
FIG. 4 is a diagram for describing the shared memory setting register according to the present embodiment.
[0032]
As shown in FIG. 4, one shared memory setting register 201 exists for each of the shared memory banks 14-0 to 14-3, and BKnst (n = bank number) corresponds to the bank number 0-3. It is named.
The contents of each setting register are mapped as P = always program memory, D = always mapped as data memory, PS = mapped as program memory but can be used as data memory, and DS = mapped as data memory. Can also be used as a program memory.
Further, 4Kw per bank is regarded as one page, and information on which page the shared memory is mapped to is a program memory or a data memory and which page is mapped is held.
[0033]
FIGS. 5A and 5B are diagrams illustrating an example in which a value is set or changed in the shared memory setting register according to the present embodiment.
[0034]
5A and 5B show a case where the register setting is rewritten so that the shared memory in which the bank status information BK2ST is set as the bank 6 for the program is used as the bank 5 for the data. ing.
[0035]
FIGS. 6A and 6B are diagrams showing an instruction memory map and a data memory map before changing the setting of the shared memory setting register. FIGS. 7A and 7B are diagrams showing the shared memory setting register. FIG. 7 is a diagram showing an instruction memory map and a data memory map after changing the setting of FIG.
[0036]
As shown in the figure, the memory allocated to the address 0x6000-0x6FFF before the setting change and the bank 6 of the program memory becomes the bank 5 of the data memory after the setting change.
[0037]
In the default state, the instruction memory is 16 Kb and the data memory is 16 Kb. However, as shown in FIG. 4, by setting the register, each bank of the shared memory is mapped to which page (address area) and mapped to the program area. Or mapping to the data area can be set.
[0038]
FIGS. 5A and 5B show an example in which a shared memory is actually mapped.
The statuses BK0ST to BK3ST of the banks 0 to 3 are shown in order from the top.
In the status shown in FIG. 5A, bank 0 is fixed to bank 4 of the program memory, bank 1 is fixed to bank 5 of the program memory, and bank 2 is bank 6 of the program memory. Bank 3 is fixed to bank 4 of the data memory.
[0039]
When the bank assignment of each bank is managed by software, the status of this register can be determined, and the assignment of the necessary program or data memory can be changed.
The status in FIG. 5B indicates a state in which the assignment of the shared memory bank 2 is determined and the assignment to the data memory bank 5 is changed.
With this change, as shown in FIGS. 6A and 6B and FIGS. 7A and 7B, the bank 6 of the program (instruction) memory is replaced with the bank of 0x5000-0x5FFF, which was a free area of the data memory. 5 represents an image to be mapped.
[0040]
This management information needs to be notified to a software development tool such as a debugger. However, since the value of the shared memory setting register 201 is generally mapped to the data space of the processor 11, the shared memory setting register 201 is used for the shared memory setting register. The value of the register can be read at any time, and the debugger can dynamically know the change in the memory area.
If an area becomes insufficient during data memory access and there is a free shared memory, the present mechanism can be used to add a data memory during operation.
[0041]
FIG. 8 is a block diagram illustrating a configuration example of the coincidence detection circuit according to the present embodiment.
[0042]
As shown in FIG. 8, the coincidence detection circuit 203 includes a bank 0 interrupt address register (INTAREG0) 2031 as a shared memory interrupt address register for writing a value of a specific address of the instruction memory 11 or the data memory 12 to each bank. 1 interrupt address register (INTAREG1) 2032, bank 2 interrupt address register (INTAREG2) 2033, and bank 3 interrupt address register (INTAREG3) which detects a match with program address IA or data address DA and outputs it as an interrupt control signal. ) 2034, a match detection 0 register (DTREG0) 2035, a match detection 1 register (DTREG1) 2036, a match detection 2 register (DTREG2) 2037, and a match detection 3 register. And static (DTREG3) 2038, a program address register (IAREG) 2039, a data address register (DIREG) 2040, and has a multiplexer 2041.
[0043]
For example, in FIG. 8, the last address of the fixed data memory is set in the data address register 2039.
Further, a memory bank selection signal SEL4 for determining which bank of data or program is to be subjected to match detection is set on the data address side. The last address of bank 3 is set in the bank 3 interrupt address register 2034, and the match detection 3 register is enabled.
[0044]
Then, during execution of the program, the above-described coincidence detection works, that is, the last address of the data memory is accessed, and the interrupt control signal INTRPT3 becomes active. As a result, the processor 11 enters the interrupt processing state, and the execution of the user program stops.
In the interrupt processing, the corresponding interrupt is programmed to perform processing for switching the available shared memory to the bank of the data memory.
Thus, the user program after returning from the interrupt processing can continuously use the data memory of the added bank.
[0045]
In addition, by implementing hardware, it is possible to automatically change the shared memory setting register 201 by accessing a certain area. Also in this case, since the information is managed by the control register, it is possible to manage the program area by the debug monitor.
[0046]
Next, an access operation to the shared memory bank in the configuration of FIG. 1 will be described.
[0047]
The instruction address IA and the data address DA output from the processor 11 are decoded by the address decoder 202 of the bus control circuit 20, and access to the corresponding memory bank is permitted.
[0048]
Here, although PWD = instruction bus write data, DWD = data bus write data, PRD = instruction read data, and DRD = data read data, the bus control circuit 20 uses the shared memory banks 14-0 to 14-3. Of each of the banks 14-0 to 14-3 is mapped to the instruction memory 12 or to the data memory 13 based on the management information, that is, the status information set in the shared memory setting register 201. , And which page each is mapped to.
The bus control circuit 20 activates the necessary memory bank selection signals SEL0 to SEL3 according to the determination result, and permits the necessary access between the bus and the memory.
The read / write signal accompanies the access and is supplied as a necessary memory control signal.
[0049]
Further, by inputting the interrupt signal INTRPT by the coincidence detection circuit 203 to the processor 11, it is possible to automatically and efficiently switch banks by software by accessing a specific address.
[0050]
According to the management information, if there is a bank with a status PS (mapped as a program memory but can also be used as a data memory), the status of the bank is set to D (always mapped as data memory) or DS (mapped as data memory). But can also be used as program memory). Normally, status information rewriting is completed in 1 CPUCLK. However, if switching is not possible due to a continuous access command, the control signal is treated as a busy (BUSY) signal and the processor can be stopped for one cycle. It is.
[0051]
As described above, according to the present embodiment, in the integrated circuit 10 including the processor 11 having the Harvard architecture and the instruction memory 12 and the data memory 13, the instruction bus 18 connecting the processor 11 and the instruction memory 12 A data bus 19 connecting the processor 11 and the data memory 13, a shared memory bank 14-0 to 14-3 that can be mapped as the instruction memory 12 or the data memory 13, and a shared memory in accordance with the selection signals SEL0 to SEL3. Multiplexers 15-0 to 15-3, 16-0 to 16-3, 17-0 to 17-3 for selectively connecting an instruction bus or a data bus, and a shared memory bank which is Shared memory setting level that holds status information of which Bus control circuit having a star 201 and outputting selection signals SEL0 to SEL3 to multiplexers 15-0 to 15-3, 16-0 to 16-3, 17-0 to 17-3 based on the set status information. Since the number 20 is provided, the following effects can be obtained.
[0052]
When designing an LSI with a Harvard architecture microprocessor and built-in memory, even if the amount of instruction memory and data memory used in software is not so accurately estimated, there is a high degree of flexibility in software development. A simple integrated circuit can be realized.
As a result, it is possible to shorten the software development TAT, and to reduce the number of LSI prototypes due to lack of memory or the like.
[0053]
【The invention's effect】
As described above, according to the present invention, when designing an LSI equipped with a Harvard architecture microprocessor and a built-in memory, the amount of instruction memory and the amount of data memory used by software are estimated very accurately. Even if it is not, there is an advantage that a programmable integrated circuit with a high degree of freedom can be realized during software development.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of an integrated circuit in which a processor having a Harvard architecture according to the present invention and an instruction memory and a data memory are mounted on one chip.
FIG. 2 is a diagram for explaining a memory configuration of a system according to the embodiment;
FIGS. 3A to 3C are diagrams illustrating examples of a memory map of an instruction memory, a data memory, and a shared memory according to the embodiment;
FIG. 4 is a diagram for explaining a shared memory setting register according to the embodiment;
FIGS. 5A and 5B are diagrams illustrating an example of setting and changing a value in a shared memory setting register according to the embodiment;
FIGS. 6A and 6B are diagrams showing an instruction memory map and a data memory map before changing a setting of a shared memory setting register.
FIGS. 7A and 7B are diagrams showing an instruction memory map and a data memory map after the setting of a shared memory setting register is changed.
FIG. 8 is a block diagram illustrating a configuration example of a match detection circuit according to the embodiment;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Integrated circuit, 11 ... Processor (CPU), 12 ... Instruction memory (IMEM), 13 ... Data memory (DMEM), 14-0 to 14-3 ... Shared memory bank (SMEM, BNK0 to BNK3), 15-0 15-3, 16-0 to 16-3, 17-0 to 17-3 ... multiplexer, 18-A ... instruction address bus, 18-W ... instruction write bus, 18-R ... instruction read bus, 19-A ... data address bus, 19-W ... data write bus, 19-R ... data read bus, 20 ... bus control circuit (BSCTL), 201 ... shared memory setting register (SMEMSREG), 202 ... address decoder (ADRDEC), 203 ... Match detection circuit (DTC), 2031 ... Bank 0 interrupt address register (INTAREG0), 2032 ... Bank 1 interrupt Address register (INTAREG1), 2033 ... Bank 2 interrupt address register (INTAREG2), 2034 ... Bank 3 interrupt address register (INTAREG3), 2035 ... Match detection 0 register (DTREG0), 2036 ... Match detection 1 register (DTREG1), 2037 ... Match detection 2 register (DTREG2), 2038 ... Match detection 3 register (DTREG3), 2039 ... program address register (IAREG), 2040 ... data address register (DIREG), 2041 ... multiplexer.

Claims (9)

An integrated circuit including a processor having a Harvard architecture, an instruction memory and a data memory,
An instruction bus connecting the processor and the instruction memory;
A data bus connecting the processor and the data memory;
A shared memory that can be mapped as an instruction memory or a data memory;
Connection switching means for selectively connecting the shared memory and the instruction bus or the data bus according to a selection signal;
Shared memory status holding means for holding status information as to whether at least the shared memory is currently mapped to the instruction memory or the data memory;
A bus control means for outputting the selection signal to the connection switching means based on status information of the shared memory status holding means when receiving an access instruction to the shared memory from the processor. 2. The integrated circuit according to claim 1, further comprising: a coincidence detecting circuit for comparing the address held in advance at a timing of accessing a specific address of the shared memory, and outputting an interrupt control signal to the processor when the addresses match. circuit. An integrated circuit including a processor having a Harvard architecture, an instruction memory and a data memory,
An instruction bus connecting the processor and the instruction memory;
A data bus connecting the processor and the data memory;
A plurality of shared memory banks that can be mapped as instruction memory or data memory;
Connection switching means for selectively connecting the desired shared memory bank and the instruction bus or the data bus according to a selection signal;
A shared memory setting register that holds status information as to whether at least the shared memory bank is currently mapped to the instruction memory or the data memory;
An integrated circuit comprising: a bus control unit that outputs the selection signal to the connection switching unit based on status information of the shared memory setting register when an instruction to access the shared memory is received from the processor. 4. The coincidence detecting circuit according to claim 3, further comprising: comparing with a previously held address at a timing of accessing a specific address of the shared memory bank, and outputting an interrupt control signal to the processor when the addresses match. Integrated circuit. The match detection circuit detects a match between an instruction address or a data address and a shared memory interrupt address register for writing a value of a specific address of an instruction memory or a data memory to each bank, and outputs an interrupt control signal when the match occurs. 5. The integrated circuit according to claim 4, further comprising a coincidence detection register for outputting to said processor. The shared memory setting register exists for each shared memory bank, and is at least always mapped as an instruction memory, always mapped as a data memory, mapped as an instruction memory, but can also be used as a data memory. 4. The integrated circuit according to claim 3, wherein status information that is mapped as a memory but can also be used as an instruction memory can be set and changed. The shared memory setting register further treats one bank as a predetermined page, and can set and change information as to whether the shared memory is mapped to an instruction memory or a data memory and to which page the bank is mapped. Is,
An integrated circuit according to claim 6. 2. The bus control circuit includes an address decoder that decodes an instruction address and a data address output from the processor, and permits access to a corresponding memory bank based on the address decoded by the address decoder. An integrated circuit as described. 9. The integrated circuit according to claim 8, wherein the address decoder is kept in an inactive state when the shared memory bank is not used.

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