JP2004166291A - Signal output circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal output circuit capable of detecting discontinuity of an electric wire or short-circuiting to the ground potential without separately providing a detection circuit. <P>SOLUTION: The signal detecting circuit is equipped with a limiter means provided between the source and the drain of a first transistor 5 connecting its gate to an output terminal of a first differential amplifier 26 wherein a signal is inputted to one input terminal and a first reference voltage setting means 28 is connected to the other input terminal, and connecting a first constant current source 21 to its source, for controlling the first transistor 5, such that an output voltage does not get out of a predetermined limit voltage, and a releasing means 35 provided in the limiter means and operated by a release signal for controlling the limiter means to perform outputting corresponding to the input signal in the region where the output voltage gets out of the predetermined limit voltage. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a signal output circuit used for a sensor for detecting acceleration, angular velocity, pressure, and the like.

  Sensors that detect acceleration, angular velocity, pressure, etc. generally have a conversion element for converting the amount of displacement of these detection targets into an electric signal, and electrically amplify a weak electric signal output from this element. Output circuit. The output circuit shown in FIG. 6 is known.

  In FIG. 6, reference numeral 26 denotes a first differential amplifier. The first differential amplifier 26 is connected between the source-coupled transistors 1 and 2 and the source of the transistors 1 and 2 and the first power supply terminal 33. An electric signal from a sensor is input to the gate of the transistor 1, and a first reference voltage setting unit 28 is provided to the gate of the transistor 2.

  Reference numeral 30 denotes a first current mirror as an active load of the first differential amplifier 26. The first current mirror 30 has a diode-coupled transistor 3 and a gate connected to the gate of the transistor 3. A gate and a drain of the transistor 3 are connected to a drain of the transistor 1, a source is connected to a second power supply terminal 34, and a drain of the transistor 4 is connected to a drain of the transistor 2. Connected, and the source is connected to the second power terminal 34.

  Reference numeral 5 denotes a transistor for pre-amplification. The gate is connected to the drain of the transistor 2 which is the output of the first differential amplifier 26. The source is connected to the second power supply terminal 34 via the constant current source 21. And the drain is connected to the first power supply terminal 33.

  An output transistor 6 has a gate connected to the source of the transistor 5, a source connected to the second power terminal 34, and a drain connected to the first power terminal 33 via the constant current source 22. Connected. The drain of the transistor 6 is connected to the output terminal 32.

  In this output circuit, the sum of the current flowing from the drain of the transistor 3 to the drain of the transistor 1 and the current flowing from the drain of the transistor 4 to the drain of the transistor 2 is kept constant. Increases, the drain voltage of the transistor 2, which is the output of the first differential amplifier 26, increases, and the gate voltage of the transistor 5 is the same as the drain voltage of the transistor 2. Source voltage increases. When the source voltage of the transistor 5 increases, the drain voltage of the transistor 6 decreases, and as a result, the output voltage of the output terminal 32 decreases.

As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
JP-A-2-62106

  However, in the conventional signal output circuit, when the output voltage is transmitted to the power receiving side circuit using an electric wire, the following problem occurs when the electric wire is disconnected or short-circuited to the ground potential.

  That is, although the input voltage to the power receiving side circuit is 0 V, it can be determined only by this output circuit whether this 0 V is the voltage as the normal output of the sensor or the voltage due to the disconnection of the electric wire or the short to the ground potential. However, there is a problem that a detection circuit for detecting a short circuit must be separately provided.

  An object of the present invention is to provide an output circuit capable of detecting disconnection of an electric wire or short-circuit to a ground potential without providing this detection circuit.

  In order to achieve this object, the invention according to claim 1 of the present invention provides a first differential amplifier in which a signal is inputted to one input terminal and a first reference voltage setting means is connected to the other input terminal. A first transistor having a gate connected to the output terminal of the first differential amplifier, and a first constant current source connected to the source; and a first transistor connected to the first transistor and the first constant current source. A second transistor having a gate connected to a connection point and a drain connected to a second constant current source and an output terminal, and a second transistor provided between a source and a drain of the first transistor; Limiter means for controlling the first transistor so that the voltage does not deviate from a predetermined limit voltage; and a limiter means provided in the limiter means, the output voltage at the output terminal being activated by a limiter release signal and changing the output voltage at the output terminal to the predetermined limit value. A limiter releasing means for controlling the limiter means so as to output in accordance with the input signal in a region deviated from the voltage, wherein a separate detection circuit is provided by providing the limiter means. It is possible to detect a disconnection of an electric wire, a short circuit to a ground potential, or a short circuit to a power supply potential, and by providing a limiter releasing means in a limiter means, for example, a means for inputting a signal to this signal output circuit. When the system is not stable immediately after the power is turned on or the like, an effect of receiving an output signal and preventing the signal output circuit from making an erroneous determination can be obtained.

  According to a second aspect of the present invention, the limiter means includes a second differential amplifier having an output terminal connected to one input terminal and a second reference voltage setting means as a limit voltage connected to the other input terminal. 2. The signal output circuit according to claim 1, further comprising at least a third transistor having a gate connected to the output terminal of said second differential amplifier and having a source coupled to said first transistor. Since the output voltage is not lower than the second reference voltage, setting the second reference voltage to a value larger than 0 V eliminates the output voltage being 0 V in a normal state. Therefore, when the output voltage is 0 V, it is possible to determine that disconnection or short-circuit to the ground potential has occurred.

  In a preferred embodiment of the present invention, the second reference voltage setting means includes a fourth transistor having a source connected to the other input terminal of the second differential amplifier and a drain connected to the ground potential; 4. The signal output circuit according to claim 2, comprising a second reference voltage source connected to the gate of the fourth transistor, and has an operation and effect that the second reference voltage can be easily set.

  According to a fourth aspect of the present invention, the second differential amplifier includes source-coupled sixth and seventh transistors, and a third constant current source connected to the sources of the sixth and seventh transistors. The signal output circuit according to claim 2, wherein an operation and an effect are provided in which the comparison between the output voltage and the second reference voltage can be accurately performed with a simple configuration. In addition, since the output voltage is directly input to the second differential amplifier, there is an operational effect that the response speed is faster than when the output voltage passes through another circuit or the like.

  According to a fifth aspect of the present invention, in the limiter release means, the drain is connected to the source of the fourth transistor of the second reference voltage setting means, the source is connected to the ground potential, and the gate is an input terminal of the limiter release signal. The signal output circuit according to claim 2, which is configured by the fifth transistor described above, and has the same operation and effect as claim 1.

  According to a sixth aspect of the present invention, the limiter releasing means connects the source to the common source of the sixth and seventh transistors constituting the second differential amplifier, connects the drain to the power supply potential, and connects the gate to the limiter. A signal output circuit according to claim 2, which is constituted by an eighth transistor serving as an input terminal of a release signal, and has the same effect as that of claim 1.

  According to a seventh aspect of the present invention, in the limiter releasing means, the source is connected to the gate of the third transistor constituting the limiter means, the drain is connected to the power supply potential, and the gate is used as the input terminal of the limiter releasing signal. A signal output circuit according to claim 2 comprising nine transistors, and has the same operation and effect as claim 1.

  As described above, the present invention provides a first differential amplifier in which a signal is input to one input terminal and a first reference voltage setting means is connected to the other input terminal, and an output of the first differential amplifier. A first transistor having a gate connected to an end and a first constant current source connected to a source; a gate connected to a connection point between the first transistor and the first constant current source; A second transistor connecting the constant current source and the output terminal of the second transistor, and a second transistor provided between the source and the drain of the first transistor so that the output voltage at the output terminal does not deviate from a predetermined limit voltage. A limiter means for controlling one of the transistors; and a limiter means provided in the limiter means, the limiter being activated by a limiter release signal and responding to the input signal in a region where the output voltage at the output terminal deviates from the predetermined limit voltage. And a limiter releasing means for controlling the limiter means so as to output the output signal.The provision of the limiter means enables disconnection of the electric wire or short-circuit to the ground potential without providing a separate detection circuit. Alternatively, the short circuit to the power supply potential can be detected, and the limiter releasing means is provided in the limiter means. For example, the means for inputting a signal to this signal output circuit is stabilized as a system immediately after the power is turned on. When not, it is possible to prevent the signal output circuit from making an erroneous determination due to receiving the output signal.

  Hereinafter, a signal output circuit of the present invention will be described with reference to embodiments and drawings. Note that a sensor was used as a means for inputting a signal to this signal output circuit.

(Embodiment 1)
With reference to the first embodiment and FIG. 1, the invention of the present invention will be described.

  First, the configuration of the signal output circuit according to the first embodiment will be described.

  In FIG. 1, reference numeral 26 denotes a first differential amplifier. The first differential amplifier 26 includes source-coupled transistors 1 and 2, a common source of the transistors 1 and 2, and a first power supply terminal 33. A signal from a sensor is input to the gate of the transistor 1, and a first reference voltage setting means 28 connects the first reference voltage setting means 28 to the gate of the transistor 2. Voltage is applied.

  Reference numeral 30 denotes a first current mirror as an active load of the first differential amplifier 26. The first current mirror 30 includes a diode-coupled transistor 3 and a transistor having a gate connected to the gate of the transistor 3. 4. The gate and the drain of the transistor 3 are connected to the drain of the transistor 1, the source of the transistor 3 is connected to a second power supply terminal 34, the drain of the transistor 4 is connected to the drain of the transistor 2, 4 is connected to the second power terminal 34.

  Reference numeral 5 denotes a first transistor for pre-amplification, a gate is connected to a drain of the transistor 2 which is an output of the first differential amplifier 26, and a source is connected via a first constant current source 21. The drain is connected to the second power terminal 34 and the drain is connected to the first power terminal 33.

  Reference numeral 6 denotes a second transistor for output, the gate is connected to the source of the first transistor 5, the source is connected to the second power supply terminal 34, and the drain is the output terminal 32 and the second constant current. The power supply 22 is connected to the first power supply terminal 33 via the power supply 22.

  Reference numeral 27 denotes a second differential amplifier. The second differential amplifier 27 includes source-coupled sixth and seventh transistors 8 and 9 and sources of the sixth and seventh transistors 8 and 9. And a third constant current source 23 connected between the first power terminal 33 and the gate of the sixth transistor 8 via the constant current source 24. 34 and to the source of the transistor 12 for output monitoring. The drain of the transistor 12 is connected to the first power supply terminal 33, and the gate is connected to the output terminal 32.

  The gate of the seventh transistor 9 is connected to the second power supply terminal 34 via the constant current source 25 and to the source of the fourth transistor 13 of the second reference voltage setting means 38. . The drain of the fourth transistor 13 is connected to the first power supply terminal 33, and the gate is connected to a second reference voltage 29 which is a limit voltage.

  Reference numeral 31 denotes a second current mirror as an active load of the second differential amplifier 27. The second current mirror 31 includes a diode-coupled transistor 14 and a transistor having a gate connected to the gate of the transistor 14. The gate and the drain of the transistor 14 are connected to the drain of the sixth transistor 8, and the source is connected to the second power supply terminal 34. The drain of the transistor 15 is connected to the drain of the seventh transistor 9, and the source is connected to the second power terminal 34.

  Reference numeral 7 denotes a third transistor for limitation. The gate of the third transistor 7 is connected to the drain of the seventh transistor 9 which is the output of the second differential amplifier 27, and the source is the first transistor. The source of the transistor 5 and the gate of the second transistor 6 are connected to the first constant current source 21, and the drain is connected to the first power supply terminal 33.

  The limiter includes at least the third transistor 7, the second differential amplifier 27, and the second reference voltage setting unit 38.

  Further, in the signal output circuit, the limiter release means 35 is provided in the limiter means, and the output saturation means 36 is provided in the first differential amplifier 26.

  The limiter releasing means 35 comprises a fifth transistor 16 connected in parallel with the fourth transistor 13, and the output saturation means 36 is provided between the first reference voltage setting means 28 and the first power supply terminal 33. , And a tenth transistor 17 provided in the memory cell. The operation of the limiter releasing means 35 and the output saturation means 36 is controlled by an abnormality detecting means 37.

  The abnormality detecting means 37 generates a control signal when an excessive or abnormal disturbance (vibration, electromagnetic wave, or the like) is applied to the sensor during a period until the output reaches a stable area at the time of activation of the sensor. is there.

  Next, the operation of the signal output circuit of this embodiment will be described.

  Since the sum of the current flowing from the drain of the transistor 3 to the drain of the transistor 1 and the current flowing from the drain of the transistor 4 to the drain of the transistor 2 is kept constant, the input to the gate of the transistor 1 When the signal increases, the drain voltage of the transistor 2, which is the output of the first differential amplifier 26, increases. Since this drain voltage and the gate voltage of the first transistor 5 have the same potential, the source voltage of the transistor 5 increases and the drain voltage of the second transistor 6 decreases. As a result, the output voltage of the output terminal 32 decreases.

  Here, when the output voltage is lower than the second reference voltage 29, which is the limit voltage, and the output voltage decreases, the gate voltage of the transistor 12 decreases, and the gate voltage of the sixth transistor 8 becomes equal to the gate voltage of the transistor 12. It decreases in conjunction with it.

  A second reference voltage 29, which is a limit voltage applied to the gate of the fourth transistor 13, is applied as a gate voltage of the seventh transistor 9.

  Therefore, the drain voltage of the seventh transistor 9, which is the output of the second differential amplifier 27, that is, the gate voltage of the third transistor 7, decreases, and in conjunction with this, the source voltage of the third transistor 7, that is, , The gate voltage of the second transistor 6 decreases, and the drain voltage of the second transistor 6 increases to the second reference voltage 29 which is the limit voltage.

  As a result, even if an input voltage such that the output voltage becomes equal to or lower than the second reference voltage 29 is input, the output voltage does not become equal to or lower than the second reference voltage 29 and is maintained at the second reference voltage 29. . At this time, the first and third transistors 5 and 7 have both sources and both drains connected to each other and have a common source voltage. Therefore, the third transistor 7 is turned on and the first transistor 5 is turned off. The output of the first differential amplifier 26 is cut off and does not affect the output voltage.

  On the other hand, when the output voltage is higher than the second reference voltage 29, which is the limit voltage, the first and third transistors 5 and 7 have the same source voltage, so that the third transistor 7 is off and the first transistor 5 is turned on, the output of the second differential amplifier 27 is cut off, and does not affect the output voltage.

  As described above, since the output voltage output from the output terminal 32 does not become lower than the second reference voltage, by setting the second reference voltage to a value larger than 0 V, the output voltage becomes 0 V in a normal state. Will not be. Therefore, when the output voltage is 0 V, the power receiving side circuit can determine that a disconnection or a short circuit to the ground potential has occurred.

  Further, the voltage at which the output voltage limiter means operates, that is, the limit voltage can supply a voltage that is accurate and stable with respect to temperature, etc., and the limit voltage can be easily changed only by changing the second reference voltage 29. Can be changed.

  By the way, when the input voltage inputted to the gate of the transistor 1 rises and the output voltage is going to fall below the second reference voltage 29 which is the limit voltage, the abnormality detecting means 37 sets the limiter to the gate of the fifth transistor 16. When the abnormality detection signal is input as the release signal, the fifth transistor 16 serving as the limiter release means 35 is turned on, thereby short-circuiting the source and the drain of the fourth transistor 13, and as a result, The gate-source voltage of the fourth transistor 13 and the second reference voltage 29 are removed. Therefore, the gate voltage of the seventh transistor 9 is adjusted by the level of the forward voltage of the transistor 16 only, that is, the gate-source voltage of the fourth transistor 13 and the second reference voltage are higher than the level adjustment voltage of the sixth transistor 8. The level is adjusted lower by the voltage 29. This means that the apparent reference voltage has decreased by the gate-source voltage of the fourth transistor 13 and the second reference voltage 29 minutes, and the output voltage is always higher than the second reference voltage 29 which is the limit voltage. Condition. At this time, the drain voltage of the seventh transistor 9, which is the output of the second differential amplifier 27, that is, the gate voltage of the third transistor 7, increases, and the source voltages of the third transistor 7 and the first transistor 5 are increased. Since they are common, the third transistor 7 is turned off and the first transistor 5 is turned on, the output of the second differential amplifier 27 is cut off, and the output voltage is not affected. As a result, even if an input voltage such that the output voltage is equal to or lower than the second reference voltage 29 is input, the output voltage can be output according to the input even in a region equal to or lower than the second reference voltage 29.

  The following configuration is also possible as the limiter releasing means 35. That is, as shown in FIG. 2, an eighth transistor 18 is provided, the source of the eighth transistor 18 is connected to the common source of the sixth and seventh transistors 8, 9, and the drain is connected to the second power supply terminal. 34, and a gate connected to the output of the abnormality detecting means 37.

  Further, a configuration as shown in FIG. That is, the ninth transistor 19 is provided, the source of the ninth transistor 19 is connected to the gate of the third transistor 7, the drain is connected to the second power supply terminal 34, and the gate is connected to the output of the abnormality detecting means 37. Connected to. 2 and 3, as in FIG. 1, the third transistor 7 and the first transistor 5 have a common source voltage, so that the third transistor 7 is off and the first transistor 5 is on. In this state, the output of the second differential amplifier 27 is shut off, and does not affect the output voltage. As a result, even if an input voltage such that the output voltage is equal to or lower than the second reference voltage 29 is input, the output voltage can be output according to the input even in a region equal to or lower than the second reference voltage 29.

  Here, when the abnormality detection output of the abnormality detecting means 37 is simultaneously applied to the gate of the tenth transistor 17 of the output saturation means 36 and the gate of the fifth transistor 16 of the limiter releasing means 35, the limiter is released as described above. Further, since the tenth transistor 17 is turned on and the gate of the transistor 2 is grounded to the first power supply terminal 33, the input voltage input to the gate of the transistor 1 is always higher than the gate voltage of the transistor 2. Therefore, the drain voltage of the transistor 2 which is the output of the first differential amplifier 26 increases, and the gate voltage of the first transistor 5 which has the same potential also increases, so that the source voltage of the first transistor 5 also increases. . As a result, the drain voltage of the second transistor 6 decreases, so that the output voltage of the output terminal 32 also decreases. Since the output voltage of the output terminal 32 is further reduced from the gate voltage of the transistor 2, the output voltage is fixed to the ground potential.

  With the above configuration, an output similar to the voltage due to disconnection or short-circuit to the ground potential can be output at the time of detection of an abnormality. The abnormality detection information can be transmitted to the power receiving side circuit.

  In this embodiment, the signal output circuit is not provided with the level adjusting means, but may be provided as necessary. For example, as shown in FIG. 4, diode-coupled transistors 10 and 11 are used to interpose between the sixth transistor 8 and the transistor 12 and between the seventh transistor 9 and the fourth transistor 13, respectively. You may let it.

  The same effect can be obtained by using a bipolar transistor instead of the transistor used in the present embodiment (not shown). In this case, the source corresponds to the emitter, the drain corresponds to the collector, and the gate corresponds to the base.

  In addition, as shown in FIG. 5, the upper limit of the output voltage can be defined when all the transistors in FIG. 1 are obtained by inverting PN. That is, in the signal output circuit of the present invention, the limit voltage, that is, the lower limit voltage is set by the second reference voltage setting means 38, but the upper limit voltage can be set in the same manner. As a result, there is an operational effect that a short circuit to the power supply terminal can be detected without providing a detection circuit. In this case, the same operation and effect can be obtained by using the bipolar transistor as described above.

  In the above embodiment, a sensor is used as a means for inputting a signal to the signal output circuit. However, the present invention is not limited to this.

  INDUSTRIAL APPLICABILITY The signal output circuit of the present invention can detect a disconnection of a wire, a short circuit to a ground potential, or a short circuit to a power supply potential without providing a separate detection circuit on the power receiving side, and is particularly useful as a signal output circuit of a sensor or the like. It is.

Signal output circuit diagram of one embodiment of the present invention Signal output circuit diagram Signal output circuit diagram Signal output circuit diagram Signal output circuit diagram Conventional signal output circuit diagram

Explanation of reference numerals

1, 2, 3, 4, 10, 11, 12, 14, 15 transistor 5 first transistor 6 second transistor 7 third transistor 8 sixth transistor 9 seventh transistor 13 fourth transistor 16th 5th transistor 17 10th transistor 18 8th transistor 19 ninth transistor 20, 24, 25 constant current source 21 first constant current source 22 second constant current source 23 third constant current source 26 first Differential amplifier 27 second differential amplifier 28 first reference voltage setting means 29 second reference voltage 30 first load resistance 31 second load resistance 32 output terminal 33 first power supply terminal 34 second Power supply terminal 35 Limiter release means 36 Output saturation means 37 Abnormality detection means 38 Second reference voltage setting means

Claims (7)

A first differential amplifier having a signal input to one input terminal and a first reference voltage setting means connected to the other input terminal;
A first transistor having a gate connected to the output terminal of the first differential amplifier and a first constant current source connected to the source;
A second transistor having a gate connected to a connection point between the first transistor and the first constant current source, and having a drain connected to a second constant current source and an output terminal;
Limiter means provided between a source and a drain of the first transistor, for controlling the first transistor so that an output voltage at the output terminal does not deviate from a predetermined limit voltage;
Limiter releasing means provided in the limiter means, the limiter releasing means being operated by a limiter releasing signal and controlling the limiter means so as to output according to the input signal in an area where an output voltage at the output terminal deviates from the predetermined limit voltage. And a signal output circuit comprising: A second differential amplifier having an output terminal connected to one input terminal and a second reference voltage setting device as a limit voltage connected to the other input terminal;
2. The signal output circuit according to claim 1, wherein a gate is connected to an output terminal of said second differential amplifier, and at least a third transistor is source-coupled to said first transistor. A second reference voltage setting means, a fourth transistor having a source connected to the other input terminal of the second differential amplifier and a drain connected to the ground potential;
3. The signal output circuit according to claim 2, further comprising a second reference voltage source connected to a gate of said fourth transistor. A second differential amplifier comprising source-coupled sixth and seventh transistors;
3. The signal output circuit according to claim 2, further comprising a third constant current source connected to the sources of said sixth and seventh transistors. The limiter releasing means is constituted by a fifth transistor having a drain connected to the source of the fourth transistor of the second reference voltage setting means, a source connected to the ground potential, and a gate having an input terminal for a limiter releasing signal. The signal output circuit according to claim 2. The limiter releasing means connects the source to the common source of the sixth and seventh transistors constituting the second differential amplifier, connects the drain to the power supply potential, and uses the gate as the input terminal of the limiter releasing signal. 3. The signal output circuit according to claim 2, comprising a transistor. 3. The limiter releasing means comprises a ninth transistor having a source connected to a gate of a third transistor constituting the limiter means, a drain connected to a power supply potential, and a gate having an input terminal for a limiter releasing signal. The signal output circuit as described.

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