JP2004166250A - Retention register having ordinary functionality independent of retention power source - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a state retention register for use in low-power standby modes. <P>SOLUTION: The state retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1-M3, M1-M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to store data from the shadow latch to the normal functional latch is a "don't care" signal while the shadow latch is retaining data during low-power standby mode; retained data from the shadow latch are restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data are provided; and a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates generally to digital integrated circuits and, more particularly, to reducing leakage current in a power saving standby mode of digital integrated circuit operation.

  This application is based on 35 USC 119 (e) 1 and is filed concurrently with US Provisional Application No. 60 / 395,123, filed July 11, 2002 (case number TI-34822), August 2002 No. 60 / 405,902 filed on 26th (Case No. TI-35107), No. 60 / 437,079 filed on Dec. 30, 2002 (Case No. TI-35107), and on Dec. 30, 2002 Claim the priority of the same application number 60 / 437,061 (case number TI-34822), all of which are incorporated herein by reference.

The demand for faster clock rates and lower power supply voltages in digital integrated circuits such as CMOS circuits has led to a sudden rise in the level of standby leakage current (ie, the current consumed by CMOS circuits when the clock is not active). It has increased. As an example, millions of gate ICs operating in the gigahertz range at supply voltages below 1.5 V may have standby leakage of 100 mA or more. This level of leakage current is a major problem in portable (battery operated) applications. Heretofore, this problem has been addressed by introducing a product that features a state-holding, low-leakage standby mode.
Most conventional state retention schemes weaken the power supply partially or entirely while maintaining the state of all register elements. When restoring its power, all circuit nodes return to their previous state, as all nodes can be directly derived from the state of the register elements.
In conventional power-down applications, the power to the circuit can be turned off to reduce standby power consumption. State-holding flip-flops that store the state of operation of the circuit need to store data in low-leakage latches during the power-down phase. Retention latches (hereinafter referred to as shadow latches) are formed of thick oxide (low leakage) transistors and are powered by a separate permanent power supply to retain data in a power down or retention mode. Disadvantages of such a method include the following. When a large number of holding flip-flops are needed, the additional circuitry required for such a shadow latch implementation is scaled at the chip level, driving the flip-flops into and out of the holding mode. The generation of the additional control signals needed to restore not only increases the flip-flop area but also causes block-level routing problems, additional shadow latches and The control circuit may worsen the propagation delay of the flip-flop, load the speed-critical path of the flip-flop, and so on.

As mentioned above, some conventional approaches use holding registers (including shadow latches) to maintain state while reducing device leakage. One such scheme has two power supplies, a permanent power supply for holding and a virtual power supply for conventional logic power. Low V _t (leaky) devices are powered by the virtual power supply, while high V _t (low leak) devices are used for retention and are powered from the permanent power supply. This architecture has limitations. Either power supply must be present for normal operation. This has the physical design overhead of routing additional power rails to all registers. Furthermore, the minimum operating voltage is limited by the high V _t devices, effectively hinders conventional Vbox-min test.
In view of the foregoing, it is desirable to provide a state holding register that avoids the above-mentioned disadvantages of conventional approaches. Various disadvantages of the conventional approach can be avoided by various exemplary embodiments of the present invention. These embodiments use a differential circuit to load the shadow latch from the normal function latch, during the low power standby mode, while the shadow latch holds data, That the signal used to restore the data to the latch is a "don't care" signal, via a transistor gate connected to the node of the shadow latch to which the retained data is supplied, That the retained data from the shadow latch is restored to the normal function latch, that a power supply other than the power supply of the shadow latch powers the data restore operation, and that the normal function latch retains state. that the operating state of the high V _t transistors used to perform the functions operable regardless No. Further, an isolation device is provided to hold the output of the logic module while the logic module is powered down.

  FIG. 1 shows a schematic of a power switching arrangement according to an exemplary embodiment of the present invention. As shown in FIG. 1, a suitable transistor as a header switch for selectively (in response to signals UP / DN) connecting and disconnecting the module level power supply VDD and the chip level (permanent) power supply VCC. Is provided. The module level power supply VDD provides operating power for a logic module including a state holding register according to the present invention. VDD is connected to VCC when UP / DN is activated and disconnected from VCC when UP / DN is deactivated.

FIG. 2 schematically illustrates an exemplary embodiment of a flip-flop having state holding capability for use in a state holding register according to the present invention. 2 is an MTCMOS (multi-threshold CMOS) flip-flop. The MTCMOS flip-flop includes a conventional core transistor used throughout the logic module and having a first gate oxide thickness, and further has a thicker gate oxide (and correspondingly) than a conventional core transistor. (With low leakage). These thick gate oxide transistors are used to perform the flip-flop's state holding function. The inverter connected back-to-back between nodes N10 and N11 forms a shadow latch for holding data while power is removed from the normal function (DQ in this example) flip-flop circuit. These inverters are formed of thick oxide (low leakage) transistors and are powered by a separate power supply VRETAIN generated from a permanent power supply VCC (see also FIG. 1). As an example, VRETAIN may be powered by a VRETAIN power supply in some embodiments and may be connected to VCC in another embodiment (shown in dashed lines in FIG. 1). The remainder of the flip-flop of FIG. 2 is powered by the module level power supply VDD, which also powers the other logic of the logic module with the state holding register. The entire flip-flop of FIG. 2, including the shadow latch, shares a common ground with the rest of the associated logic module.
The complementary clock signals CLK and CLKZ are used in a conventional manner for operating a normal function flip-flop circuit. The save signal SAVE and the restore signal REST (and its inverted signal RESTZ) are used to transition the flip-flop of FIG. 2 between an active mode of operation and a state holding mode. During the active mode of operation (ie, normal function flip-flop operation), the SAVE and REST signals are maintained at a logic zero level.
Before disconnecting VDD from VCC (see also FIG. 1), the data stored in the normal function flip-flop circuit must be stored in the shadow latch. To do this, the SAVE signal is strobed high, thereby activating the differential pull down networks of M1, M2 and M3. The pull-down network includes a pair of legs, which are the inputs and outputs of the inverter 21 of the slave latch of the normal function flip-flop, respectively, connected to the complementary storage nodes. Depending on the logic state of the normal function flip-flop, one of the legs of the differential pull-down network is activated to store data in the shadow latch. The pull-down network can be designed to fight off shadow oxide weak thick oxide PMOS transistors. In some embodiments, the M1, M2 and M3 transistors and the shadow latch transistors are used to ensure that the contents of the normal function flip-flop are written to the shadow latch in a worst case process corner scenario. In addition, the size is determined. In a worst case scenario, the weak process corner NMOS transistors M1 and M2 need to fight off the associated PMOS transistor of the strong process corner shadow latch. The flip-flop of FIG. 2 can be made even stronger and more reliable in some embodiments by designing for the aforementioned worst-case process corner scenario at low temperatures and low supply voltages.
After the SAVE signal has been strobed and the data has been stored in the shadow latch from the normal function flip-flop, the flip-flop of FIG. 2 is ready to enter hold mode. Since the header switch of FIG. 1 is used to decouple VCC and VDD, all nodes of the logic module powered by VDD will decay to near zero volts. However, since the shadow latch is still powered by a separate power supply VRETAIN, data is being held in the shadow latch. With the normal function flip-flop circuit powered down, the shadow latch data storage nodes N10 and N11 are isolated from the powered down circuit to reduce leakage current while the shadow latch holds data. There must be. This is achieved by the thick oxide transistors M1, M2, M5 and M6. The transistor stack of M4-M7 switchably connects state storage node N10 to node N8 of the normal function flip-flop. For example, by using this transistor stack arrangement rather than the passgate arrangement between nodes N11 and N8, instead of connecting storage node N11 to the source (or drain) of the passgate arrangement, storage node N10 is connected to transistor M5. And the gate of M6. The connection of node N10 to the gates of thick oxide transistors M5 and M6 advantageously reduces the potential for current leakage from the shadow latch.
Complementary signals REST and RESTZ are used to restore data from shadow latches to normal function flip-flops. When VDD is reconnected to VCC (see also FIG. 1), signal REST is driven to a logic 1 voltage. This activates the thin oxide transistors M4 and M7 to power the M5-M6 inverter, thereby moving from the shadow latch to the slave latch of the normal function flip-flop to restore the retained data. A read back pass is created. Further, when signal REST is driven to a logic one voltage, the thin oxide transistors of M8 and M9 disable the feedback path of the slave latch of the normal function flip-flop. Upon reconnection of VDD to VCC, only the shadow latch drives node N8 through the M4-M7 inverter. This ensures that node N8 is restored to the voltage that was there before disconnecting VDD from VCC. After the shadow latch drives node N8 to its previous voltage, VDD is reconnected to VCC, after which the REST signal is returned to logic zero. At this point, the shadow latch is isolated from the normal function flip-flop portion of FIG. 2 and is ready to resume its normal function DQ flip-flop operation.

  FIG. 3 shows a schematic of the pertinent parts of a further exemplary embodiment of a state holding flip-flop arrangement for use in a state holding register according to the invention. FIG. 3 shows that thin oxide transistors M4 and M7 drive node N8, while thick oxide transistor M5 is connected between VDD and M4, and thick oxide transistor M6 is connected between M7 and ground. FIG. Gate signals for controlling the transistors M4 to M7 are the same as those shown in FIG. The rest of the state holding flip-flop may be identical to the structure shown in FIG. 2, and the arrangement of FIG. 3 functions in a similar manner as generally described above in connection with FIG.

FIG. 8 shows a schematic diagram of a further exemplary embodiment of a flip-flop with state holding capability for use in a state holding register according to the present invention. In FIG. 8 (and also in FIGS. 9 and 10), the reference characters M1, M2, etc. of FIGS. 2 and 3 are again used, but as can be seen, they are referred to in FIGS. 2 and 3. Does not necessarily refer to the same type of transistor (NMOS or PMOS, thick or thin oxide). The flip-flop in FIG. 8 is an MTCMOS (multi-threshold CMOS) flip-flop. As in FIG. 2, the flip-flop of FIG. 8 includes a normal core transistor used throughout the logic module and having a first gate oxide thickness, and further includes a thicker gate oxide than the normal core transistor. (And correspondingly low leakage). These thick gate oxide transistors are used to perform the flip-flop's state holding function. The inverter connected back-to-back between nodes N10 and N11 forms a shadow latch for holding data while power is removed from the normal function flip-flop circuit, where the normal function flip-flop is The circuit may be, for example, generally the same as described above in connection with FIG. The inverter between nodes N10 and N11 is formed of a thick oxide (low-leakage) transistor and is powered by a separate power supply VRETAIN, described above in connection with FIGS. The rest of the flip-flop of FIG. 8 is powered by the module level power supply VDD, which also powers the other logic of the logic module with the state holding register. Like FIG. 2, the entire flip-flop of FIG. 8, including the shadow latch, shares a common ground with the rest of the associated logic module. As in FIG. 2, the SAVE and REST signals are used to transition the flip-flop between an active mode of operation and a hold mode. During the active (normal) mode of operation, the SAVE and REST signals are maintained at a logic zero level.
As in FIG. 2, before disconnecting VDD from VCC (see also FIG. 1), the data stored in the normal function flip-flop circuit must be stored in the shadow latch. To do this, the SAVE signal is strobed high, thereby activating a differential pull-down network including transistors M1, M2, M3 and M4. The pull-down network includes a pair of legs, which are the inputs and outputs of the inverter 21 of the slave latch of the normal function flip-flop, respectively, connected to the complementary storage nodes. Depending on the logic state of the normal function flip-flop, one of the legs of the differential pull-down network is activated in response to the SAVE signal to save data from the normal function flip-flop to the shadow latch. The pull-down network can be designed to fight off shadow oxide weak thick oxide PMOS transistors. In some embodiments, transistors M1-M4 and the transistors of the shadow latch are sized to ensure that the contents of the normal function flip-flop are written to the shadow latch in a worst case process corner scenario. Is determined. In a worst case scenario, the weak process corner NMOS transistors M3 and M4 need to fight off the strong process corner shadow latch PMOS transistor. The flip-flop of FIG. 8 may be made even stronger and more reliable in some embodiments by designing for the worst-case process corner scenario at low temperatures and low supply voltages.
After the SAVE signal has been strobed and the data has been stored in the shadow latch from the normal function flip-flop, the flip-flop of FIG. 8 is ready to enter hold mode. Since the header switch of FIG. 1 is used to decouple VCC and VDD, all nodes of the logic module powered by VDD will decay to near zero volts. However, since the shadow latch is still powered by a separate power supply VRETAIN (not explicitly shown in FIG. 8), data is being held in the shadow latch. With the normal function flip-flop circuit powered down, the shadow latch data storage nodes N10 and N11 are isolated from the powered down circuit to reduce leakage current while the shadow latch holds data. There must be. This is achieved by the thick oxide transistors M3, M4, M5 and M6. Transistors M5, M6, M7 and M8 form a differential pull down structure, which allows data stored at nodes N10 and N11 to be restored to nodes N7 and N8, respectively. For example, by using this pull-down network, rather than connecting the storage nodes N10 and N11 to the sources (or drains) of the passgate arrangement, rather than connecting the storage nodes N10 and N11 to the sources (or drains) of the nodes N10 and N11 and the nodes N7 and N8. And N11 can be connected to the gates of transistors M6 and M5. Connecting nodes N10 and N11 to the gates of thick oxide transistors M6 and M5, respectively, advantageously reduces the potential for current leakage from the shadow latch.
The REST signal is used to restore data from the shadow latch to a normal function flip-flop. Before VDD is reconnected to VCC (see also FIG. 1), signal REST is driven to a logic 1 voltage. This activates the pull-down network of M5-M8, and transistors M9 and M10 provide positive feedback to latch the data held in the shadow latch. This creates a read-back path from the shadow latch to the slave latch of the normal function flip-flop to restore the retained data. Further, when signal REST is driven to a logic one voltage, the thin oxide transistor of M11 disables the feedback path of the slave latch of the normal function flip-flop. Upon reconnection of VDD to VCC, only the shadow latch drives nodes N7 and N8. This ensures that nodes N7 and N8 are restored to their respective voltages prior to disconnecting VDD from VCC. After the shadow latch drives nodes N7 and N8 to their previous voltages, VDD is reconnected to VCC and the REST signal is then returned to logic zero. At this point, the shadow latch is isolated from the normal function flip-flop portion of FIG. 8 and is ready to resume its normal function DQ flip-flop operation.

  FIG. 9 shows a schematic diagram of a further exemplary embodiment of a flip-flop having state holding capability for use in a state holding register according to the present invention. In the arrangement of FIG. 9, the normal function flip-flop circuit is of a negative edge trigger type design instead of a positive edge trigger type design as shown in FIGS. In this situation, the state holding circuit is connected to nodes N2 and N3 of the normal function flip-flop circuit as shown, so that save and restore operations can be performed in relation to the master latch of the normal function flip-flop circuit. Connected. That is, data from the master latch of the normal function flip-flop circuit can be stored in the shadow latch, and data stored in the shadow latch can be restored to the master latch of the normal function flip-flop circuit. The state holding circuits of FIG. 9, namely, the shadow latches, the SAVE pull-down networks M1-M4, and the RESTORE pull-down networks M5-M10 are, in some embodiments, the same as those described above in connection with FIG. There may be. In FIG. 9, when the REST signal is driven to a logic one voltage, the thin oxide transistor 91 disables the feedback path of the master latch of the normal function flip-flop.

FIG. 10 shows a schematic diagram of a further exemplary embodiment of a flip-flop having state holding capability for use in a state holding register according to the present invention. The flip-flop of FIG. 10 uses a clock-free holding scheme, in which the state holding function can be performed independently of the clock input CLK. This is useful for flip-flops whose clock input is unknown at power-up, for example, a flip-flop whose clock input is derived from the data output of another flip-flop. The flip-flop of FIG. 10 is generally similar to the flip-flop of FIG. 8, but between the master latch node N3 and the node N9 defined by the connection point of the transistors M8 and M10 connected in series. , A transfer gate TG3 is added, and a transfer gate TG4 is added between the node N9 and the node N8 of the slave latch. The SAVE operation of the flip-flop of FIG. 10 may be the same as described above in connection with FIG. When the REST signal is activated, node N7 is restored independent of the CLK state. Further, the node N9 is restored. Node N9 then drives master latch node N3 (when CLK is high) or slave latch node N8 (when CLK is low) depending on whether CLK is high or low. If CLK is low, data is restored to node N8 to end the slave latch loop. When CLK is high, node N7 drives nodes N2 and N4 via transfer gates TG1 and TG2, and node N9 drives node N3 via transfer gate TG3. This terminates the master latch loop.
In some exemplary embodiments, transistors M9 and M10 may have a width of 0.2 um and a length of 0.4 um, respectively. The flip-flop of FIG. 10 further includes a transistor 91 as described above in connection with FIG. 9 such that activation of the REST signal disables the master latch feedback path.

FIG. 4 shows a schematic of the relevant parts of an exemplary embodiment of a wireless communication device according to the invention. The wireless communication device of FIG. 4 includes an antenna structure 41 for enabling communication via the air interface. The data processing unit 43 can perform data processing operations related to communication on the air interface 42. The wireless communication interface may use conventional techniques for interfacing the data processing device 43 to the antenna structure 41. User interface 44 may use conventional techniques for interfacing data processing device 43 to a user of a wireless communication device.
The data processing unit 43 includes a plurality of logic modules including logic for performing a data processing operation, and a state holding register for storing data related to the data processing operation. These registers include a plurality of corresponding state holding flip-flops, such as the state holding flip-flops shown in FIGS. 2, 3 and 8-10. Data processing unit 43 further includes a power state controller 45, which in some embodiments uses a state machine to provide appropriate control signals to header switches and logic modules. As shown in FIG. 4, the power state controller provides a control signal UP / DN to each header switch to control signals REST, RETZ (described below) and SAVE for distribution to each of the logic modules. I will provide a. Power state controller 45 activates these control signals to properly perform the exemplary operations described above in connection with FIGS. 2, 3, and 8-10.

FIG. 5 is a timing chart showing a timing relationship of a control signal generated by the power state controller 45. Note that the VDD waveform of FIG. 5 generally corresponds in time to the activation (VDD on) and deactivation (VDD off) of the UP / DN signal of FIG.
In some embodiments, the high-level control logic 46 commands the power state controller 45 to perform a low-power standby (hold state) mode of operation, such that the power state controller 45 enters the standby mode. To do so, the typical signaling described above can be made and reported to the high level control logic 46. Logic 46 and controller 45 may be powered by VRETAIN in some embodiments.
The wireless communication device of FIG. 4 may be, for example, a mobile phone or other mobile communicator, a laptop computer, a PDA, or the like. In some embodiments, data processing unit 43 is provided as a single integrated circuit, such as a microprocessor, microcontroller, or digital signal processor.
Referring again to FIGS. 2 and 8-10, during the state hold, the SAVE signal must be guaranteed to be low. In some embodiments, the SAVE is distributed using a buffer tree powered by a holding power supply VRETAIN (hereinafter also referred to as VRET). In these embodiments, the buffer tree that distributes SAVE to the state holding circuit of a given logic module includes a plurality of buffer cells embedded in the area of the integrated circuit where the associated logic module is located. . These buffer cells are suitably interconnected to provide a SAVE to the state holding circuit. In some embodiments, each buffer cell is located beneath the unswitched VDD metal, ie, the metal layer connected to VRET. Each buffer cell is connected to the unswitched VDD metal by a vertical stack of all metal and via layers. An example of this arrangement is shown generally in FIG. 6B.
Referring now to FIG. 6B, a typical buffer cell includes thick oxide transistors 610 and 620 interconnected at 630 and 640 to form an inverter. The metal layer MET6 connected to the holding voltage VRET is also connected to the transistor 620 (eg, a PMOS transistor) by a vertical stack of all metal and via layers, generally indicated at 650. The vertical stack of 650 extends between the metal layer MET6 and the further metal layer MET1. Metal layer MET1 provides connectivity to the gate, source, and drain of transistors 610 and 620. The vertical stack at 650 connects VRET to transistor 620. N-well 660, including transistor 620, is electrically isolated from adjacent cells as indicated generally at 670. In the arrangement of FIG. 6B, N-well 660 follows the 570 nm spacing rule for the N-well of an adjacent buffer cell.

In FIG. 6B, vertical stack 650 is track-centered on horizontal track 5. In order to avoid long-run jogging of the metal layer routing between layers MET1 and MET6, in some embodiments, a horizontal arrangement of vertically adjacent buffer cells is used. Some optimization is used. In some embodiments, the minimum area rule for the metal of the metal layer is adhered to in a manner that does not block one or more tracks in the preferred routing direction. This may reduce the effect of the vertical stack 650 on routability.
With the buffer cell arrangement shown in FIG. 6B, the SAVE and RETZ signals (discussed below) have the same general structure as that shown in FIG. 7, but with a buffer tree powered by the holding power supply VRET. May be distributed across a given logic module.
Some embodiments use a VDD powered buffer tree to distribute SAVE (and / or RETZ). In such an embodiment, since VDD is removed from the logic module during state holding, a single inverter is connected between power state controller 45 (see FIG. 4) and the state holding circuit of the logic module. Only can be arranged. This is shown generally in FIG. 6A. The power state controller 45 generates SAVE ′ or RET (the respective inverted signals of SAVE and RETZ) in the arrangement of FIG. 6A. If the signal SAVE '(or RET) is high, the SAVE (or RETZ) signal will remain low (as desired) even while the inverter of FIG. 6A is not receiving power.
The exemplary embodiment described above offers a number of advantages, some examples of which are given below. Each state holding flip-flop has only eight of the larger thick oxide transistors, four transistors in the shadow latch, two transistors to write to the shadow latch, and a read in the shadow latch. Only two transistors are required. Only two thick oxide PMOS transistors, the PMOS transistors of the shadow latch inverter, are included in separate N-wells (see also FIGS. 2 and 8-10). During state holding, current leakage during state holding is reduced because only the thick oxide (low leakage) transistors remain biased.
During the state holding mode, the REST signal may be undefined. This advantageously allows a fully active buffer tree (powered by VDD) to be used to distribute the REST signal to the state holding registers, as shown generally in FIG. Thus, when VDD is reconnected to VCC, the REST signal can propagate very quickly (eg, in a few nanoseconds), so the data from the shadow latch will be very fast, eg, 100 nanoseconds. In seconds, it can be restored to a normal function flip-flop. With a restore time in the range of 100 nanoseconds, the logic module can be placed in a low power state retention mode at any time because the restore operation occurs so quickly that it cannot be detected by system software or hardware. Thus, the state retention mode is transparent to the data processing system.

The transistors M4 and M7 of FIGS. 2 and 3 and the transistors M7-M10 of FIGS. 8-10 do not draw switching current from the VREATIN power supply during state holding or during the transition from state holding to normal operation. This allows the VREATIN power supply voltage to be conveniently distributed as a conventional logic signal (e.g., distributed to multiple registers in parallel as shown in FIG. 7), and thus a conventional VRETIN for distributing VRETAIN. Power grid is no longer needed. When placed as a logic signal, the VREATIN power supply may be weakened when the SAVE signal is asserted, but sufficient time may be provided for VRETAIN to return to its DC level before the SAVE signal is deasserted. Although this increases the time required to perform a save state operation, the save state operation does not limit the system response time.
The thick oxide (high V _t , low leakage) transistors of FIGS. 2, 3 and 8-10 can all be disabled (ie, any conductivity / resistance) without affecting the normal operation of the normal function flip-flop. Level). Accordingly, even when unable operations predict such high V _t transistors at low V _t levels, conveniently, it is conventional Vbox-min test at low V _t levels.
Referring again to FIG. 4, in some applications it may be desirable to power down one or more logic modules independently of the remaining logic modules to reduce current consumption. . In these situations, to ensure that any powered-up logic module driven by the output signal of the powered-down logic module is not affected by the power-down of the driving logic module, The output signal voltage of the powered down logic module must be maintained.

FIG. 11 schematically illustrates the need to maintain the output signal from a powered down logic module. In FIG. 11, modules A, B, and C are powered by different power supplies, VDD _A , VDD _B , and VDD _C , respectively. VRET (previously also called VRETAIN) is a holding power supply, which is common to all three logic modules. If only module A is powered down (by removing VDD _A ), the signal voltage level at its output must be maintained to allow continued operation of modules B and C. As shown in FIG. 11, each output of module A may have an associated device S to maintain an associated output signal voltage while module A is powered down.
FIG. 12 shows a schematic of an exemplary embodiment of an apparatus S for maintaining the output voltage signal level of a logic module that is powered down (see module A of FIG. 11). In FIG. 12, reference characters M1, M2, etc. of FIGS. 2, 3, and 8-10 are again used, but as can be seen, these are FIGS. 2, 3, and 8-10. Do not necessarily refer to the same type of transistor (NMOS or PMOS, thick or thin oxide). The input node IN of the device of FIG. 12 may be connected, for example, to the Q output of any of the flip-flops of FIGS. 2, 3, and 8-10. During normal power-up operation of logic module A, inverters M1, M2 and M5, M6 connected in series form a driver that buffers signals from node IN to output node OUT. The driver, an inverter M5, M6 of the second stage, the power input, i.e., to disconnect from VDD _A and ground (VSS),, selectively disabled by using transistors M3, M4, and M7 obtain. The shadow latch and differential pull-down network, generally designated 121 in FIG. 12, may be the same as the corresponding structure in FIGS. 8-10. As shown, the data inputs to the structure 121 are the signal at the input node IN of the first-stage inverters M1, M2 and the signal at the output node INZ of the first-stage inverters M1, M2. The SAVE signal of FIG. 12 may be the same as described above in connection with FIGS. 2, 3, and 8-10. The transistors of the shadow latch inverter and the transistors M12 and M14 of the pull-down network are thick oxide transistors, and the transistors of the shadow latch inverter are powered by the holding power supply VRET.
The output node 122 of the shadow latch drives the inputs of the inverting driver stages M8-M11. Specifically, transistors M9 and M10 form an inverter between node 122 and the OUT node. Transistors M8 and M11 provide the ability to selectively disable inverters M9, M10 by disconnecting them from their power inputs, ie, VRET and ground. Transistors M8-M11 are all thick oxide transistors.
During normal power-up operation of logic module A, signal RET is low and complementary signal RETZ is high. Under these circumstances, the transistors M3 and M4 in parallel combination, the transistor M7, an inverter M5, M6 of the second stage, the power input, i.e., to provide a connection between the VDD _A and ground . During the hold mode, there may be some leakage through transistor M3 when RET is high and RETZ is low to disable the second stage inverter. To reduce the effects of such leakage, the W / L (width-to-length) ratio of transistor M3 may be relatively small, for example, in the range of about 3 to about 10. Conversely, for thick oxide transistor M4 (or M7), the leakage in the holding mode is not a problem, and to increase speed, the W / L ratio of M4 (and M7) is relatively large, eg, about 30 To greater than 100.
Transistor M3 has a lower V _t than the transistor M4, therefore, VDD _A is very low, for example, even when low as 0.7 volts, it is possible to normal operation of the arrangement of FIG. 12. Therefore, the arrangement of Figure 12, even if the operation of the high V _t transistor M4 unpredictable low V _t levels, can undergo Vbox-min test at low V _t levels.

After the data signals defined by IN and INZ are latched into the shadow latch of 121 by strobed the SAVE signal high, signal RETZ is pulled low to invoke the hold mode of operation. The SAVE strobe also provides data to an internal shadow latch in logic module A, for example, one of the state holding flip-flops described above in connection with FIGS. 2, 3 and 8-10. Latch the signal. When RETZ is low and its complementary signal RET is high, the second stage inverters M5 and M6 are disabled and the output inverter drivers M9 and M10 are enabled, thereby changing the contents of the 121 shadow latch. , Such as module B or module C of FIG. 11, at the input of another powered up logic module.
After the data signal from logic module A has been restored at node IN (by operation of restore signal REST of the corresponding state-holding flip-flop of module A), signal RETZ is resumed to resume normal output operation of module A. May be brought high again, thereby disabling inverters M9, M10 and enabling inverters M5, M6.

FIG. 13 is a timing diagram illustrating exemplary operations (described above) that may be performed by the power state controller 45 of FIG. 4 to control the operation of the apparatus of FIG. In some embodiments, the SAVE signal and the restore signal REST may be generated and distributed in a manner similar to that described above in connection with FIGS. 2-10, and RETZ may be generated and distributed in a manner similar to SAVE. obtain. Figure 5 is VDD slightly before returning to the high value, while indicating that the restore signal REST is high, in the example of FIG. 13, the restore signal REST, after returning to VDD _A high value, high become. As described above in connection with FIG. 7, this difference is not functionally significant because the restore signal REST is distributed within a given logic module by a buffer tree powered by VDD. Thus, even if the power state controller 45 of FIG. 4 drives the restore signal REST high before VDD returns to the corresponding logic module, it supplies power to the buffer tree that distributes REST across the logic modules. Therefore, the restore signal REST does not become active in the logic module until VDD returns to a high value.
While exemplary embodiments of the present invention have been described above in detail, the description is not intended to limit the scope of the invention, which can be accomplished in various embodiments.

5 is a schematic diagram illustrating an example of a logic block having a low power standby mode according to the present invention. 1 is a schematic diagram illustrating an exemplary embodiment of a flip-flop having state holding capability for use in a state holding register according to the present invention. FIG. 4 is a schematic diagram illustrating a further exemplary embodiment of a flip-flop having state holding capability for use in a state holding register according to the present invention. 1 is a schematic diagram illustrating the relevant parts of an exemplary embodiment of a wireless communication device according to the present invention. FIG. 5 is a timing diagram illustrating exemplary operation of the power state controller of FIG. 4 is a schematic diagram illustrating an exemplary scheme for distributing control signals used by a state holding circuit according to the present invention. 5 is a schematic diagram illustrating an arrangement of buffer cells. 5 is a schematic diagram illustrating another scheme for distributing control signals used by a state holding circuit according to the present invention. FIG. 4 is a schematic diagram illustrating a further exemplary embodiment of a flip-flop having state holding capability for use in a state holding register according to the present invention. FIG. 4 is a schematic diagram illustrating a further exemplary embodiment of a flip-flop having state holding capability for use in a state holding register according to the present invention. FIG. 4 is a schematic diagram illustrating a further exemplary embodiment of a flip-flop having state holding capability for use in a state holding register according to the present invention. 4 is a schematic diagram illustrating a plurality of logic modules that can be selectively powered down. 4 is a schematic diagram illustrating an exemplary embodiment of a holding device for holding an output of a logic module while the logic module is powered down. FIG. 5 is a timing diagram illustrating further exemplary operations that may be performed by the power state controller of FIG.

Explanation of reference numerals

M1-M3 differential circuit REST, RESTZ restore signal N10 of the shadow latch node VDD power VRETAIN separate power M1, M2, M5 and M6 high _{V t} transistors

Claims (10)

A data latch device,
A first latch for latching a data signal;
A second latch connected to the first latch to hold the data signal while the first latch is inactive;
A restore device connected between the first and second latches and driven by a first power supply to transfer the data signal from the second latch to the first latch;
A second latch powered by a second power supply other than the first power supply.   2. The apparatus of claim 1, wherein the second latch includes a first node for providing the data signal to the restore device, wherein the restore device is connected to the first node. An apparatus including first and second transistors having respective gates connected.   3. The apparatus of claim 2, wherein the first latch includes a plurality of transistors, each transistor of the plurality of transistors has a gate oxide, and wherein the first and second transistors are the plurality of transistors. A third transistor having a gate oxide thicker than the gate oxide of the first transistor and the restore device connected in series with the first and second transistors to form a serially connected transistor stack. And a fourth transistor, wherein the third and fourth transistors have a gate oxide that is thinner than the gate oxide of the first and second transistors.   2. The apparatus of claim 1, wherein the second latch includes a node for providing the data signal to the restore device, the restore device having a gate connected to the node. A device that includes a transistor.   2. The apparatus of claim 1, wherein the second latch is for retaining the data signal while the first latch is inactive due to removal of power therefrom. apparatus.   2. The apparatus of claim 1, wherein the second latch includes first and second nodes for providing the data signal to the restore device, wherein each of the restore devices includes the first and second nodes. An apparatus including first and second transistors having respective gates connected to the first and second nodes. A data processing device,
Data processing logic for performing data processing operations;
A plurality of registers coupled to the data processing logic for storing data associated with the data processing operation, wherein each of the registers includes a plurality of data latch structures;
A first latch for latching a data signal, a second latch connected to the first latch for holding the data signal while the first latch is inactive, and And a restore device connected between a second latch and a second latch and driven by a first power supply to transfer the data signal from the second latch to the first latch. A latch structure;
The second latch powered by a second power supply other than the first power supply.   The apparatus of claim 7, wherein the apparatus is provided as one of a microprocessor, a microcontroller, and a digital signal processor.   The apparatus of claim 7, comprising a logic signal path connected to the restore device for distributing the first power supply thereto. A wireless communication device,
An antenna structure to enable communication over the air interface;
A digital data processor for performing digital data processing operations;
A wireless communication interface connected between the antenna structure and the digital data processor for interfacing between the antenna structure and the digital data processor;
The digital data processor including a plurality of data latch structures, wherein each data latch structure includes a first latch for latching a data signal, while the first latch is inactive. A second latch connected to the first latch for holding the data signal; and a second latch connected between the first latch and the second latch to transfer the data signal from the second latch to the second latch. Said digital data processor including a restore device driven by a first power supply for transfer to a first latch;
The second latch powered by a second power source other than the first power source.