JP2004165434A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device wherein polishing is prevented from being undone between wirings, and errosion, dishing, and thinning of the wiring are prevented . <P>SOLUTION: The manufacturing method for a semiconductor device comprises the steps of forming an interlayer insulating film composed of an interwiring insulating layer 12 and a protective layer 13 on a substrate 11, and further forming a sacrificial film 21 on the interlayer insulating film; forming a trench pattern 14 on the interlayer insulating film and the sacrificial film 21, and further forming a conductive material film composed of a barrier metal layer 15 and a wiring material layer 17 on the sacrificial film 21 such that the inside of the trench pattern 14 is embedded; and polishing and removing the conductive material film until the surface of the sacrificial film 21 is exposed. The surface of the interlayer insulating film is exposed by selectively removing the sacrificial film 21. The method further comprises the steps of bringing about a state where the conductive material film is protruded from the trench pattern 14, and flattening a protruded portion of the conductive material film by polishing and removing the protruded portion while taking the interlayer insulating film as a stopper. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and particularly to forming wirings and vias by burying a copper film in a wiring groove pattern or a via hole groove pattern formed in an interlayer insulating film and flattening the copper film. The present invention relates to a method for manufacturing a semiconductor device.
[0002]
[Prior art]
The performance of LSIs has been improved by reducing the design dimensions, and at present, design rules called the 90 to 100 nm generation are being mass-produced. As the design dimensions have been reduced, materials have been changed to accommodate the reduction. Representatively, a gate material is changed from polysilicon (Poly-Si) to metal polycide, a wiring material is changed from aluminum (Al) to copper (Cu), and a silicon oxide film (SiO ₂ ) is used as an interlayer insulating film material. ) To a low dielectric constant film.
[0003]
Here, one of the reasons for the change of the wiring material from Al to Cu in particular is that the wiring width is reduced due to the reduction of the wiring design rule, and the wiring resistance of Al is increased.
This increase in the wiring resistance affects the wiring delay obtained by the product of the wiring resistance (R) and the capacitance between wirings (C), and when the wiring delay exceeds a specified value, the required specifications of the semiconductor device are satisfied. become unable. Therefore, Cu having a lower specific resistance than Al was selected.
[0004]
Another reason is that the wiring width of Al is reduced, the current density flowing in the wiring is increased, and not only the electromigration (EM) is accelerated, but also the size of the crystal in the wiring is larger than the wiring width. Since the crystal becomes large, there is a problem that the crystal forms a bamboo structure with respect to the wiring and stress migration (SM) is accelerated.
The resistance of EM and SM as described above largely depends on the wiring material, and Cu is superior to Al.
[0005]
With the change of the wiring material, the semiconductor forming process is also changed.
That is, in the case of the generation of Al as the wiring material, after the Al film is formed on the substrate, the Al film serving as the wiring portion is covered with a resist mask by lithography technology, and the exposed Al film is removed by etching to form the Al wiring. Had formed.
[0006]
However, in the generation of Cu as the wiring material, the process of processing the wiring like Al is not common because the corrosiveness of Cu is large, and a buried wiring process called a damascene process is widely used.
[0007]
Here, a general Cu wiring process will be described below with reference to FIGS.
First, as shown in FIG. 4A, an inter-wiring insulating layer 12 made of a low dielectric constant material is formed on a substrate 11.
Next, since the low dielectric constant material has low resistance to a chemical mechanical polishing (CMP) method performed in a later step, a protective layer 13 serving as a polishing stopper is formed on the inter-wiring insulating layer 12.
[0008]
Next, as shown in FIG. 4B, a groove pattern 14 is formed in the inter-wiring insulating layer 12 and the protective layer 13 by ordinary lithography and etching.
[0009]
Subsequently, as shown in FIG. 4C, a barrier metal layer 15 made of, for example, titanium nitride (TiN) is formed on the protective layer 13 so as to cover the inner wall of the groove pattern 14 by a sputtering method or the like. As shown in FIG. 4D, a seed layer 16 made of Cu is formed on the surface of the barrier metal layer 15 by a sputtering method or the like.
[0010]
Next, as shown in FIG. 5E, a wiring material layer 17 made of Cu is formed on the seed layer 16 (see FIG. 4D) so as to fill the groove pattern 14 by electrolytic plating or the like. .
Thereafter, as shown in FIG. 5F, the wiring material layer 17 (including the seed layer 16) is removed by a CMP method until the surface of the barrier metal layer 15 is exposed, and the polishing conditions are changed. The barrier metal layer 15 is removed until the surface of the protective layer 13 serving as a stopper is exposed, and a Cu wiring is formed in the groove pattern 14.
[0011]
As a semiconductor device having such a configuration, there has been reported a similar example in which a protective layer 13 serving as a polishing stopper for CMP is provided on an inter-wiring insulating layer 12 made of a low dielectric constant film (for example, Patent Document 1). reference).
[0012]
[Patent Document 1]
JP 2000-100818 A
[Problems to be solved by the invention]
However, according to the above-described method of manufacturing a semiconductor device, the wiring material layer 17 (including the seed layer 16) and the barrier metal layer 15 other than those in the groove pattern 14 are polished and removed by the CMP method, thereby forming the groove. Since the Cu wiring is formed in the pattern 14, if the polishing is insufficient, the polishing residue of the wiring material layer 17 or the barrier metal layer 15 occurs on the protective layer 13 between the wirings. There was a problem that it reduced.
[0014]
Further, when the wiring material layer 17 and the barrier metal layer 15 are sufficiently polished so that no polishing residue occurs between the wirings, the wiring material layer 17 formed of Cu, which is a relatively soft material, in the groove pattern 14 becomes Problems such as dishing in which excessive polishing progresses in a wide pattern, erosion in which excessive polishing advances in a dense pattern, and thinning in which a film to be polished becomes thinner occur, and the wiring formed in the groove pattern 14 becomes thinner. There has been a problem that reliability is reduced.
[0015]
When the wiring in the groove pattern 14 becomes thin, when applied to a multilayer wiring, a step is generated, and the step becomes larger as the number of wiring layers is increased. At the time of forming the next buried wiring, if Cu remains in such a depression of the step, a short circuit between the wirings is caused. Therefore, excessive polishing was necessary to remove Cu on the step. However, excessive polishing not only reduces the thickness of the wiring portion, but also reduces the thickness of the interlayer insulating film, which causes a problem that it is difficult to secure insulation between wirings above and below the thinned interlayer insulating film. I was
[0016]
In particular, Cu used as the wiring material layer 17 is a soft material, whereas the underlying barrier metal layer 15 is formed of a hard material having a lower polishing rate than Cu, such as TiN. Since a polishing pressure is required for removal by polishing, the wiring material layer 17 tends to be excessively polished.
[0017]
Therefore, there has been a demand for a method of manufacturing a semiconductor device that prevents polishing residue between wires and prevents erosion, dishing, and thinning of wires.
[0018]
[Means for Solving the Problems]
In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film on a substrate, and then forming a sacrificial film on the interlayer insulating film; Forming a groove pattern on the sacrificial film so as to fill the groove pattern, polishing and removing the conductive material film until the surface of the sacrificial film is exposed, The step of exposing the surface of the interlayer insulating film and projecting the conductive material film from the groove pattern by selectively removing the film, and the step of projecting the conductive material film using the interlayer insulating film as a stopper. Polishing and removing to planarize.
[0019]
According to the method for manufacturing a semiconductor device of the present invention, the conductive material film is embedded in the groove pattern formed in the interlayer insulating film and the sacrificial layer, and after removing the conductive material film until the surface of the sacrificial layer is exposed, By selectively removing the sacrificial layer, the conductive material film remains only on the groove pattern, and by removing the sacrificial layer forming the upper sidewall of the groove pattern, the conductive material film is removed. It will be in the state protruding from the groove pattern.
For this reason, when polishing and removing the conductive material film protruding from the groove pattern, since the conductive material film is not formed on the interlayer insulating film, the polishing residue of the conductive material film between the wirings is removed. Can be prevented.
In addition, the conductive material film protruding from the groove pattern is easy to polish and requires less pressure during polishing. Therefore, even if the protruding portion of the conductive material film is removed by polishing, the conductive material in the groove pattern is removed. Dishing, erosion, and thinning of the conductive material film can be prevented.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
An example of an embodiment according to a method for manufacturing a semiconductor device of the present invention will be described with reference to manufacturing process sectional views of FIGS.
[0021]
As shown in FIG. 1A, after a device is formed on a substrate 11 (for example, a silicon substrate) by a normal LSI process, for example, a chemical vapor deposition (CVD) method or a coating method is used. Thereby, the inter-wiring insulating layer 12 made of a low dielectric constant material is formed to a thickness of 0.1 μm to 0.5 μm.
The low dielectric constant material, e.g., SiOF-based film obtained by mixing F to silicon oxide (SiO _2), SiOC-based film obtained by mixing methyl group SiO _2, porous SiO ₂ film obtained by introducing pores into SiO _2, polyaryl An organic material-based film or the like such as an ether-based resin (for example, product name: Silk manufactured by Dow Chemical Company) is preferably used.
[0022]
Next, a protective layer 13 made of, for example, silicon nitride (SiN) is formed on the inter-wiring insulating layer 12.
Here, the protection layer 13 is in a polishing step for removing a barrier metal layer on the protection layer 13 by a CMP method in a step described later, and is in a state protruding from a groove pattern formed in the interwiring insulating layer 12 and the protection layer 13. In the polishing step for removing the barrier metal layer and the wiring material layer by the CMP method, it functions as a polishing stopper layer of the inter-wiring insulating layer 12 having low CMP resistance.
Therefore, the protective layer 13 is formed of a material having a lower polishing rate by the CMP method than the barrier metal layer and the wiring material layer.
[0023]
Here, SiN is used for the protective film 13. However, the present invention is not limited to this. For example, SiO ₂ , silicon carbide (SiC), boron nitride (BN), diamond-like carbon, TEOS oxide film, and the like can be used. It is preferably used.
The protective layer 13 made of the above-described material has a higher dielectric constant than the inter-wiring insulating layer 12 made of a low dielectric constant material.
[0024]
Therefore, the protective layer 13 may have a thickness enough to prevent the inter-wiring insulating layer 12 from being polished during the polishing step by the above-described CMP method. Since the protective layer 13 is formed of a material having a higher dielectric constant than the inter-wiring insulating layer 12, it is preferable to specifically form the protective layer 13 with a thickness of 30 to 200 nm in order to suppress the inter-wiring capacitance.
[0025]
Subsequently, a sacrificial film 21 characteristic of the present invention is formed on the protective layer 13.
The sacrificial film 21 may be made of any material that can be selectively removed from the protective layer 13, a barrier metal layer and a wiring material layer described later when the sacrificial film 21 is removed in a later step.
Here, since the sacrificial film 21 is removed by a CMP method in a later step, a material that can be removed with a CMP selectivity of 10 or more with respect to the protective layer 13, the barrier metal layer, and the wiring material layer is preferable.
[0026]
As a material of such a sacrificial film 21, a porous oxide film such as phosphorus-containing silicon oxide (PSG), boron-containing silicon oxide (BSG), phosphorus-boron-containing silicon oxide (BPSG), nano-glass, or the like is preferable. Used for
Further, the thickness of the sacrificial film 21 is equal to or more than a thickness having a CMP resistance such that the barrier metal layer formed on the sacrificial film 21 in a later step is not removed together with the barrier metal layer when the barrier metal layer is removed by the CMP method. In addition, when the groove pattern is formed in the inter-wiring insulating layer 12, the protective layer 13, and the sacrificial film 21 which are formed in a laminated manner, the thickness is set to be equal to or less than a thickness that allows easy processing.
Specifically, it is preferable to form the sacrificial film 21 with a thickness of 100 nm to 500 nm.
[0027]
Next, as shown in FIG. 1B, a wiring groove reaching the substrate 11 is formed in the inter-wiring insulating layer 12, the protective layer 13, and the sacrificial film 21 by reactive etching using a resist pattern (not shown) as a mask. Is formed, and the resist pattern is removed.
[0028]
Next, as shown in FIG. 1C, a barrier metal is formed on the sacrificial film 21 so as to cover the inner wall of the groove pattern 14 by a physical vapor deposition (PVD) method such as a sputtering method. The layer 15 is formed.
Here, the barrier metal layer 15 is for preventing diffusion of a wiring material layer made of Cu to be embedded in the groove pattern 14 in a step described later.
Further, as described with reference to FIG. 1A in the above-described process, the barrier metal layer 15 is formed of a material having a higher polishing rate by the CMP method than the protective layer 13. Specifically, the CMP selectivity is preferably 10 or more.
[0029]
As a material of such a barrier metal layer 15, for example, TiN, titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN) and the like are preferably used. .
Here, the barrier metal layer 15 is formed by the PVD method, but the present invention is not limited to this, and the chemical vapor deposition (Chemical Vapor Deposition (CVD)) method, the atomic layer deposition (Atomic Layer Deposition ( ALD)) method.
[0030]
Subsequently, as shown in FIG. 2D, a seed layer 16 made of, for example, Cu is formed on the surface of the barrier metal layer 15. The seed layer 16 is formed by a PVD method, a CVD method, or an ALD method.
Here, when the Cu used for the seed layer 16 is formed on an oxide, the Cu forms an oxide of Cu and easily peels off. Therefore, the barrier metal layer 15 is not exposed to the air after the formation of the barrier metal layer 15. Thus, the seed layer 16 is subsequently formed.
[0031]
Next, as shown in FIG. 2E, a wiring material layer 17 made of Cu is formed on the seed layer 16 so as to fill the groove pattern 14 by electrolytic plating or CVD.
Here, as described with reference to FIG. 1A in the above process, the wiring material layer 17 is formed of a material having a higher polishing rate by the CMP method than the protective layer 13. Specifically, the CMP selectivity is preferably 10 or more, and when Cu is used for the wiring material layer 17, the material of the protective layer 13 should be selected so that the CMP selectivity of Cu is 10 or more. preferable.
Note that the seed layer 16 is also included in the wiring material layer 17 after this step.
[0032]
Thereafter, as shown in FIG. 2F, the wiring material layer 17 is polished and removed by, for example, a CMP method until the surface of the barrier metal layer 15 is exposed (first stage polishing).
Examples of the CMP conditions in this case include abrasive grains such as silica and alumina in the polishing liquid, hydrogen peroxide solution (H ₂ O ₂ ) for oxidizing and removing Cu, and manganese peroxide (MnO _x ). An oxidizing agent, a complexing agent such as a Cu chelating complexing agent for complexing Cu oxidized to improve polishing characteristics, and a complexing agent such as a carboxylic acid chelating agent are used.
[0033]
The polishing pad has a structure in which a processing surface side is a foamed polyurethane resin (for example, product name IC1000 manufactured by Rodale) and a pad (for example, Suba400 manufactured by Rodale) is laminated on the back side (product name IC1000 / made by Rodale). Suba400) and a polishing pressure in the range of 210 to 490 g / cm ² .
In this polishing step, dishing and erosion occur, and the wiring material layer 17 and the barrier metal layer 15 are shaved in the upper part in the groove pattern 14.
[0034]
Next, as shown in FIG. 3G, the barrier metal layer 15 is polished and removed by the CMP method until the surface of the sacrificial film 21 is exposed (second stage polishing).
Here, the polishing conditions for the CMP are the same as those for polishing the wiring material layer 17 described above.
[0035]
Next, as shown in FIG. 3H, the sacrificial film 21 (see FIG. 3G) is applied to the underlying protective layer 13, the barrier metal layer 15 in the groove pattern 14, and the wiring material layer 17. Selectively remove.
Here, the sacrificial film 21 is removed by, for example, a CMP method (third stage polishing).
As an example of the CMP conditions here, a neutral to alkaline (pH 6 to 13) slurry in which a silica-based abrasive such as colloidal silica or fumed silica is mixed in a polishing liquid is used.
Note that the oxidizing agent and the complexing agent are not mixed because they oxidize the surface of Cu constituting the wiring material layer 17.
[0036]
Further, as the polishing pad, it is only necessary to remove only the sacrificial film 21 in the polishing, and therefore, a relatively soft polishing pad is preferably used because flatness is not emphasized.
As such a polishing pad, polyvinyl alcohol, a nonwoven fabric, or the like can be suitably used.
Further, since the flatness is not emphasized as described above, the polishing pressure is set relatively high and the polishing speed is set relatively low.
As an example, in the case of a turntable type CMP apparatus, the polishing pressure is 350 to 490 g / cm ² , and the polishing speed is 20 to 50 rpm. In the case of the orbital type CMP apparatus, the polishing speed is 50 to 490 g / cm ² and the polishing speed is 75. Use at ~ 100 rpm.
[0037]
By selectively polishing and removing the sacrificial film 21, the surface of the protective layer 13 is exposed, and the wiring material layer 17 and the wiring material layer 17 are removed from the groove pattern 14 formed by the sacrificial layer 21 from which the upper sidewall has been removed. The upper portion of the barrier metal layer 15 is in a protruding state.
[0038]
Here, the sacrificial film 21 is removed by the CMP method, but the present invention is not limited to this, and the sacrificial film 21 is selectively formed with respect to the protective layer 13, the barrier metal layer 15, and the wiring material layer 17. If possible, wet etching or dry etching may be used.
Here, when the sacrificial film 21 is selectively removed by wet etching, for example, SiO ₂ is used for the sacrificial film 21 and sacrificial is performed using dilute hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF) as an etchant. The film 21 is removed.
[0039]
Thus, since the etching rate of the protective layer 13 made of, for example, SiN is low with hydrofluoric acid (HF), the etching rate of the sacrificial film 21 can be controlled by performing process management.
Further, the barrier metal layer 15 is relatively excellent in HF resistance, and since a passivation layer is formed on the surface of the wiring material layer 17 made of Cu, etching is suppressed.
Therefore, the sacrificial film 21 can be selectively removed.
When the sacrificial film 21 made of SiO ₂ is removed by wet etching using HF as described above, the protective layer 13 is formed of a material other than SiO ₂ .
[0040]
When the sacrificial film 21 is selectively removed by dry etching, ordinary oxide film dry etching can be applied by using an oxide film for the sacrificial film 21. In this case, the surface of the conductive material film 14 made of Cu may be oxidized and corroded by the etching gas, but a portion exposed to the etching gas during the dry etching is removed in a step described later. no problem.
[0041]
The above-described wet etching or dry etching is more preferable because the sacrificial film 21 can be selectively removed while maintaining the shapes of the protruding wiring material layer 17 and the barrier metal layer 15.
[0042]
Next, as shown in FIG. 3 (i), the wiring material layer 17 and the barrier metal layer 15 projecting from the groove pattern 14 by the CMP method are removed until the height becomes equal to the surface of the protective layer 13, Flatten (fourth stage polishing).
As an example of the CMP conditions here, the same polishing liquid and polishing pad as those in the first-stage polishing can be applied.
Further, in this polishing, since flatness is more important than the first-stage polishing, a single-layer pad of a relatively hard foaming polyurethane resin (for example, product name IC1000 manufactured by Rodale) may be applied.
The polishing pressure is 140 to 280 g / cm ² , and the polishing rotation speed is 100 rpm or more in a turntable type and 200 rpm or more in an orbital type.
[0043]
According to such a method of manufacturing a semiconductor device, the inner wall of the groove pattern 14 formed in the inter-wiring insulating layer 12, the protective layer 13 and the sacrificial layer 21 is covered with the barrier metal layer 15, and the wiring material layer 17 is formed in the groove pattern 14. And the wiring material layer 17 and the barrier metal layer 15 are removed until the surface of the sacrificial layer 21 is exposed, and then the sacrificial layer 21 is selectively removed.
As a result, the barrier metal layer 15 and the wiring material layer 17 remain only on the groove pattern 14, and the upper side wall of the groove pattern 14 formed of the sacrificial film 21 is removed. The wiring material layer 17 projects from the groove pattern 14.
[0044]
Therefore, when the barrier metal layer 15 and the wiring material layer 17 protruding from the groove pattern 14 are polished and removed, since the barrier metal layer 15 and the wiring material layer 17 are not formed on the protective layer 13, Since polishing residue between the wirings can be prevented and a short circuit between the wirings can be prevented, the yield can be improved.
[0045]
Further, since the barrier metal layer 15 and the wiring material layer 17 projecting from the groove pattern 14 are easily polished and require less pressure during polishing, even if the projecting portion is removed by polishing, the groove pattern 14 The dishing, erosion, and thinning of the wiring material layer 17 in the inside can be prevented, the thinning of the wiring in the groove pattern 14 can be suppressed, and the flattening is easy.
This not only prevents a decrease in the reliability of the wiring due to the thinning of the wiring, but also allows the height of the wiring formed in the groove pattern 14 to be formed as designed, thereby improving EM resistance and SM resistance. Can reliably obtain the reliability of the wiring.
[0046]
Further, since the wiring height can be formed as designed, even when the present invention is applied to a multilayer wiring, there is no step unlike the conventional case, so that the lithography at the time of forming the groove pattern 14 is surely performed. be able to.
Further, since there is no step, it is not necessary to perform excessive polishing to remove the wiring material on the step. Therefore, since the interlayer insulating film is not excessively polished, the interlayer insulating film including the interwiring insulating layer 12 and the protective layer 13 can be made thinner in order to reduce the effective dielectric constant.
Therefore, a highly accurate semiconductor device can be obtained.
[0047]
In the present embodiment, an example is described in which the protective layer 13 is formed on the inter-wiring insulating layer 12 because a low dielectric constant material having low CMP resistance is used for the inter-wiring insulating layer 12, but the present invention is not limited to this. However, for example, when a film made of a material having relatively high CMP resistance is used for the inter-wiring insulating layer 12, the protective layer 13 may not be formed.
[0048]
In this case, the sacrificial film 21 is formed on the inter-wiring insulating layer 12, and the groove pattern 14 is formed in the inter-wiring insulating layer 12 and the sacrificial film 21.
Further, when removing the wiring material layer 17 and the barrier metal layer 15 protruding from the groove pattern 14, the inter-wiring insulating layer 12 serves as a stopper. The inter-wiring insulating layer 12 is formed using a material that preferably has a selection ratio of 10 or more so as to increase the CMP selection ratio.
Further, the sacrificial film 21 is made of a material that can be selectively removed from the inter-wiring insulating layer 12, the barrier metal layer 15, and the wiring material layer 17.
[0049]
In the present embodiment, the example in which the barrier metal layer 15 is formed is described. However, when the wiring material layer 17 is made of a material that does not diffuse into the inter-wiring insulating layer 12, the barrier metal layer 15 is not formed. You may.
In this case, the second-stage polishing is not performed, and in the first-stage polishing, the wiring material layer 17 is removed until the protective layer 13 is exposed.
[0050]
In the above-described embodiment, the so-called single damascene process in the embedded wiring process has been described. However, the present invention is also applicable to a dual damascene process in which a via hole is formed at the bottom of a wiring groove.
[0051]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device of the present invention, when the conductive material film protruding from the groove pattern is removed by polishing, the conductive material film remains on the interlayer insulating film. Since no polishing remains between the wirings, a short circuit between the wirings can be prevented, so that the yield can be improved.
[0052]
In addition, the conductive material film protruding from the groove pattern is easy to polish and requires less pressure during polishing. Therefore, even if the protruding portion of the conductive material film is removed by polishing, the conductive material in the groove pattern is removed. By preventing dishing, erosion, and thinning of the conductive material film, it is possible to suppress the wiring in the groove pattern from being thinned, and it is easy to flatten the wiring.
This not only prevents a decrease in the reliability of the wiring due to the thinning of the wiring, but also allows the height of the wiring formed in the groove pattern to be formed as designed, thereby ensuring the reliability of the wiring. Obtainable.
[0053]
Further, since the height of the wiring can be formed as designed, a highly accurate semiconductor device can be obtained, and a remarkable effect can be obtained particularly when applied to a multilayer wiring.
[Brief description of the drawings]
FIG. 1 is a sectional view (part 1) of a manufacturing process showing an example of an embodiment according to a method of manufacturing a semiconductor device of the present invention.
FIG. 2 is a cross-sectional view (part 2) illustrating an example of an embodiment of the method for manufacturing a semiconductor device according to the present invention;
FIG. 3 is a sectional view (No. 3) illustrating an example of an embodiment of the method for manufacturing a semiconductor device according to the present invention;
FIG. 4 is a cross-sectional view of a manufacturing step showing a method of manufacturing a semiconductor device according to a conventional technique (part 1).
FIG. 5 is a cross-sectional view of a manufacturing step showing a method of manufacturing a semiconductor device according to a conventional technique (part 2).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... board | substrate, 12 ... insulating layer between wirings, 13 ... protective layer, 14 ... groove pattern, 15 ... barrier metal layer, 17 ... wiring material layer, 21 ... sacrificial film

Claims (4)

After forming an interlayer insulating film on the substrate, forming a sacrificial film on the interlayer insulating film,
Forming a groove pattern in the interlayer insulating film and the sacrificial film, forming a conductive material film on the sacrificial film so as to fill the groove pattern;
Polishing and removing the conductive material film until the surface of the sacrificial film is exposed,
A step of selectively removing the sacrificial film to expose the surface of the interlayer insulating film and to project the conductive material film from the groove pattern;
Polishing the protruding portion of the conductive material film by using the interlayer insulating film as a stopper to remove the protruding portion, thereby planarizing the conductive material film. The interlayer insulating film includes an inter-wiring insulating layer and a protective layer on the inter-wiring insulating layer,
2. The method according to claim 1, wherein the protective layer is formed of a material having a lower polishing rate than the conductive material film. 2. The conductive material film includes a barrier metal layer formed on the sacrificial film so as to cover an inner wall of the groove pattern, and a wiring material layer on the barrier metal layer. Manufacturing method of a semiconductor device. 4. The method according to claim 3, wherein the polishing rate of the barrier metal layer is lower than that of the wiring material layer.

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